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drm/gf100-/gf: split tpc state into its subunits 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2014-03-03 16:18:56 +10:00
parent 97af71fa40
commit 7e19453349
19 changed files with 374 additions and 270 deletions
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24
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
View File

@ -458,10 +458,7 @@ nv108_grctx_pack_gpc[] = {
};
static const struct nvc0_graph_init
nv108_grctx_init_tpc_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
nv108_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000100f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000421 },
@ -472,14 +469,11 @@ nv108_grctx_init_tpc_0[] = {
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419a30, 1, 0x04, 0x00000001 },
{ 0x419ac4, 1, 0x04, 0x0037f440 },
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3efbefbe },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000203 },
{}
};
static const struct nvc0_graph_init
nv108_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
@ -508,7 +502,11 @@ nv108_grctx_init_tpc_0[] = {
static const struct nvc0_graph_pack
nv108_grctx_pack_tpc[] = {
{ nv108_grctx_init_tpc_0 },
{ nvd7_grctx_init_pe_0 },
{ nv108_grctx_init_tex_0 },
{ nvf0_grctx_init_mpc_0 },
{ nvf0_grctx_init_l1c_0 },
{ nv108_grctx_init_sm_0 },
{}
};

42
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
View File

@ -894,19 +894,29 @@ nvc0_grctx_pack_zcull[] = {
{}
};
static const struct nvc0_graph_init
nvc0_grctx_init_tpc_0[] = {
const struct nvc0_graph_init
nvc0_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x0000012a },
{ 0x419888, 1, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvc0_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
{ 0x419a0c, 1, 0x04, 0x00020000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{}
};
const struct nvc0_graph_init
nvc0_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
@ -916,15 +926,35 @@ nvc0_grctx_init_tpc_0[] = {
{ 0x419bd0, 1, 0x04, 0x00900103 },
{ 0x419be0, 1, 0x04, 0x00000001 },
{ 0x419be4, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvc0_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x00000002 },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvc0_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00060048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{}
};
const struct nvc0_graph_init
nvc0_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x02180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{}
};
static const struct nvc0_graph_init
nvc0_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
@ -938,7 +968,13 @@ nvc0_grctx_init_tpc_0[] = {
const struct nvc0_graph_pack
nvc0_grctx_pack_tpc[] = {
{ nvc0_grctx_init_tpc_0 },
{ nvc0_grctx_init_pe_0 },
{ nvc0_grctx_init_tex_0 },
{ nvc0_grctx_init_wwdx_0 },
{ nvc0_grctx_init_mpc_0 },
{ nvc0_grctx_init_l1c_0 },
{ nvc0_grctx_init_tpccs_0 },
{ nvc0_grctx_init_sm_0 },
{}
};

19
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
View File

@ -105,11 +105,23 @@ extern const struct nvc0_graph_init nvc0_grctx_init_gcc_0[];
extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[];
extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[];
extern const struct nvc0_graph_init nvc0_grctx_init_pe_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_wwdx_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_mpc_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_tpccs_0[];
extern const struct nvc0_graph_init nvc4_grctx_init_tex_0[];
extern const struct nvc0_graph_init nvc4_grctx_init_l1c_0[];
extern const struct nvc0_graph_init nvc4_grctx_init_sm_0[];
extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[];
extern const struct nvc0_graph_init nvc1_grctx_init_gpm_0[];
extern const struct nvc0_graph_init nvc1_grctx_init_pe_0[];
extern const struct nvc0_graph_init nvc1_grctx_init_wwdx_0[];
extern const struct nvc0_graph_init nvc1_grctx_init_tpccs_0[];
extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[];
extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[];
@ -124,6 +136,10 @@ extern const struct nvc0_graph_init nvd9_grctx_init_prop_0[];
extern const struct nvc0_graph_init nvd9_grctx_init_gpc_unk_1[];
extern const struct nvc0_graph_init nvd9_grctx_init_crstr_0[];
extern const struct nvc0_graph_init nvd9_grctx_init_sm_0[];
extern const struct nvc0_graph_init nvd7_grctx_init_pe_0[];
extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[];
extern const struct nvc0_graph_init nve4_grctx_init_ds_0[];
extern const struct nvc0_graph_init nve4_grctx_init_scc_0[];
@ -137,5 +153,8 @@ extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[];
extern const struct nvc0_graph_init nvf0_grctx_init_gpc_unk_2[];
extern const struct nvc0_graph_init nvf0_grctx_init_mpc_0[];
extern const struct nvc0_graph_init nvf0_grctx_init_l1c_0[];
#endif

47
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
View File

@ -678,22 +678,18 @@ nvc1_grctx_pack_gpc[] = {
{}
};
static const struct nvc0_graph_init
nvc1_grctx_init_tpc_0[] = {
const struct nvc0_graph_init
nvc1_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
{ 0x419a0c, 1, 0x04, 0x00020000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{ 0x419a1c, 1, 0x04, 0x00000000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419ac4, 1, 0x04, 0x0007f440 },
{}
};
const struct nvc0_graph_init
nvc1_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
@ -703,31 +699,26 @@ nvc1_grctx_init_tpc_0[] = {
{ 0x419bd0, 1, 0x04, 0x00900103 },
{ 0x419be0, 1, 0x04, 0x00400001 },
{ 0x419be4, 1, 0x04, 0x00000000 },
{ 0x419c00, 1, 0x04, 0x00000002 },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{}
};
const struct nvc0_graph_init
nvc1_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x12180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{ 0x419d44, 1, 0x04, 0x02180218 },
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000000f },
{ 0x419e50, 17, 0x04, 0x00000000 },
{ 0x419e98, 1, 0x04, 0x00000000 },
{ 0x419ee0, 1, 0x04, 0x00011110 },
{ 0x419f30, 11, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_pack
nvc1_grctx_pack_tpc[] = {
{ nvc1_grctx_init_tpc_0 },
{ nvc1_grctx_init_pe_0 },
{ nvc4_grctx_init_tex_0 },
{ nvc1_grctx_init_wwdx_0 },
{ nvc0_grctx_init_mpc_0 },
{ nvc4_grctx_init_l1c_0 },
{ nvc1_grctx_init_tpccs_0 },
{ nvc4_grctx_init_sm_0 },
{}
};

42
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c
View File

@ -28,13 +28,8 @@
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_graph_init
nvc4_grctx_init_tpc_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x0000012a },
{ 0x419888, 1, 0x04, 0x00000000 },
const struct nvc0_graph_init
nvc4_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@ -44,24 +39,19 @@ nvc4_grctx_init_tpc_0[] = {
{ 0x419a1c, 1, 0x04, 0x00000000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419ac4, 1, 0x04, 0x0007f440 },
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
{ 0x419b0c, 1, 0x04, 0x0e629062 },
{ 0x419b10, 1, 0x04, 0x0a418820 },
{ 0x419b14, 1, 0x04, 0x000000e6 },
{ 0x419bd0, 1, 0x04, 0x00900103 },
{ 0x419be0, 1, 0x04, 0x00000001 },
{ 0x419be4, 1, 0x04, 0x00000000 },
{ 0x419c00, 1, 0x04, 0x00000002 },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvc4_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{ 0x419d20, 1, 0x04, 0x02180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{}
};
const struct nvc0_graph_init
nvc4_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
@ -76,7 +66,13 @@ nvc4_grctx_init_tpc_0[] = {
static const struct nvc0_graph_pack
nvc4_grctx_pack_tpc[] = {
{ nvc4_grctx_init_tpc_0 },
{ nvc0_grctx_init_pe_0 },
{ nvc4_grctx_init_tex_0 },
{ nvc0_grctx_init_wwdx_0 },
{ nvc0_grctx_init_mpc_0 },
{ nvc4_grctx_init_l1c_0 },
{ nvc0_grctx_init_tpccs_0 },
{ nvc4_grctx_init_sm_0 },
{}
};

32
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
View File

@ -94,11 +94,16 @@ nvd7_grctx_pack_gpc[] = {
{}
};
static const struct nvc0_graph_init
nvd7_grctx_init_tpc_0[] = {
const struct nvc0_graph_init
nvd7_grctx_init_pe_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvd7_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@ -108,30 +113,27 @@ nvd7_grctx_init_tpc_0[] = {
{ 0x419a1c, 1, 0x04, 0x00008000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419ac4, 1, 0x04, 0x0017f440 },
{}
};
static const struct nvc0_graph_init
nvd7_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3efbefbe },
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000000f },
{ 0x419e50, 17, 0x04, 0x00000000 },
{ 0x419e98, 1, 0x04, 0x00000000 },
{ 0x419ee0, 1, 0x04, 0x00010110 },
{ 0x419f30, 11, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_pack
nvd7_grctx_pack_tpc[] = {
{ nvd7_grctx_init_tpc_0 },
{ nvd7_grctx_init_pe_0 },
{ nvd7_grctx_init_tex_0 },
{ nvd7_grctx_init_mpc_0 },
{ nvc4_grctx_init_l1c_0 },
{ nvd9_grctx_init_sm_0 },
{}
};

40
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
View File

@ -445,12 +445,7 @@ nvd9_grctx_pack_gpc[] = {
};
static const struct nvc0_graph_init
nvd9_grctx_init_tpc_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
nvd9_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@ -460,27 +455,22 @@ nvd9_grctx_init_tpc_0[] = {
{ 0x419a1c, 1, 0x04, 0x00000000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419ac4, 1, 0x04, 0x0017f440 },
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
{ 0x419b0c, 1, 0x04, 0x0e629062 },
{ 0x419b10, 1, 0x04, 0x0a418820 },
{ 0x419b14, 1, 0x04, 0x000000e6 },
{ 0x419bd0, 1, 0x04, 0x00900103 },
{ 0x419be0, 1, 0x04, 0x00400001 },
{ 0x419be4, 1, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvd9_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3cf3cf3c },
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{ 0x419d20, 1, 0x04, 0x12180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{ 0x419d44, 1, 0x04, 0x02180218 },
{}
};
const struct nvc0_graph_init
nvd9_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
@ -495,7 +485,13 @@ nvd9_grctx_init_tpc_0[] = {
static const struct nvc0_graph_pack
nvd9_grctx_pack_tpc[] = {
{ nvd9_grctx_init_tpc_0 },
{ nvc1_grctx_init_pe_0 },
{ nvd9_grctx_init_tex_0 },
{ nvc1_grctx_init_wwdx_0 },
{ nvd9_grctx_init_mpc_0 },
{ nvc4_grctx_init_l1c_0 },
{ nvc1_grctx_init_tpccs_0 },
{ nvd9_grctx_init_sm_0 },
{}
};

26
drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
View File

@ -751,10 +751,7 @@ nve4_grctx_pack_gpc[] = {
};
static const struct nvc0_graph_init
nve4_grctx_init_tpc_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
nve4_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000021 },
@ -765,14 +762,29 @@ nve4_grctx_init_tpc_0[] = {
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419a30, 1, 0x04, 0x00000001 },
{ 0x419ac4, 1, 0x04, 0x0037f440 },
{}
};
static const struct nvc0_graph_init
nve4_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3efbefbe },
{}
};
static const struct nvc0_graph_init
nve4_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00003203 },
{}
};
static const struct nvc0_graph_init
nve4_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000402 },
{ 0x419e44, 1, 0x04, 0x0013eff2 },
@ -792,7 +804,11 @@ nve4_grctx_init_tpc_0[] = {
static const struct nvc0_graph_pack
nve4_grctx_pack_tpc[] = {
{ nve4_grctx_init_tpc_0 },
{ nvd7_grctx_init_pe_0 },
{ nve4_grctx_init_tex_0 },
{ nve4_grctx_init_mpc_0 },
{ nve4_grctx_init_l1c_0 },
{ nve4_grctx_init_sm_0 },
{}
};

26
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
View File

@ -719,10 +719,7 @@ nvf0_grctx_pack_gpc[] = {
};
static const struct nvc0_graph_init
nvf0_grctx_init_tpc_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
nvf0_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000021 },
@ -733,14 +730,29 @@ nvf0_grctx_init_tpc_0[] = {
{ 0x419a20, 1, 0x04, 0x00020800 },
{ 0x419a30, 1, 0x04, 0x00000001 },
{ 0x419ac4, 1, 0x04, 0x0037f440 },
{}
};
const struct nvc0_graph_init
nvf0_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3efbefbe },
{}
};
const struct nvc0_graph_init
nvf0_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000203 },
{}
};
static const struct nvc0_graph_init
nvf0_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
@ -769,7 +781,11 @@ nvf0_grctx_init_tpc_0[] = {
static const struct nvc0_graph_pack
nvf0_grctx_pack_tpc[] = {
{ nvf0_grctx_init_tpc_0 },
{ nvd7_grctx_init_pe_0 },
{ nvf0_grctx_init_tex_0 },
{ nvf0_grctx_init_mpc_0 },
{ nvf0_grctx_init_l1c_0 },
{ nvf0_grctx_init_sm_0 },
{}
};

33
drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
View File

@ -86,19 +86,18 @@ nv108_graph_init_setup_1[] = {
};
static const struct nvc0_graph_init
nv108_graph_init_tpc_0[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
nv108_graph_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
{ 0x419aa8, 2, 0x04, 0x00000000 },
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x419850, 1, 0x04, 0x00000004 },
{ 0x419854, 2, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nv108_graph_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@ -109,19 +108,6 @@ nv108_graph_init_tpc_0[] = {
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x00000230 },
{ 0x419ccc, 2, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00000000 },
{ 0x419eb4, 1, 0x04, 0x00000000 },
{ 0x419ebc, 2, 0x04, 0x00000000 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419ed0, 1, 0x04, 0x00003234 },
{ 0x419f74, 1, 0x04, 0x00015555 },
{ 0x419f80, 4, 0x04, 0x00000000 },
{}
};
@ -145,7 +131,12 @@ nv108_graph_pack_mmio[] = {
{ nvd9_graph_init_gpm_0 },
{ nvf0_graph_init_gpc_unk_1 },
{ nvc0_graph_init_gcc_0 },
{ nv108_graph_init_tpc_0 },
{ nve4_graph_init_tpccs_0 },
{ nv108_graph_init_tex_0 },
{ nve4_graph_init_pe_0 },
{ nv108_graph_init_l1c_0 },
{ nvc0_graph_init_mpc_0 },
{ nvf0_graph_init_sm_0 },
{ nvd7_graph_init_ppc_0 },
{ nve4_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },

52
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View File

@ -274,27 +274,62 @@ nvc0_graph_init_gcc_0[] = {
{}
};
static const struct nvc0_graph_init
nvc0_graph_init_tpc_0[] = {
const struct nvc0_graph_init
nvc0_graph_init_tpccs_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
const struct nvc0_graph_init
nvc0_graph_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvc0_graph_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
{ 0x419850, 4, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvc0_graph_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00008bf4 },
{ 0x419cbc, 1, 0x04, 0x28137606 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvc0_graph_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvc0_graph_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvc0_graph_init_mpc_0[] = {
{ 0x419c0c, 1, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvc0_graph_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@ -330,7 +365,7 @@ nvc0_graph_init_fe_1[] = {
};
const struct nvc0_graph_init
nvc0_graph_init_tpc_1[] = {
nvc0_graph_init_pe_1[] = {
{ 0x419880, 1, 0x04, 0x00000002 },
{}
};
@ -353,10 +388,17 @@ nvc0_graph_pack_mmio[] = {
{ nvc0_graph_init_gpm_0 },
{ nvc0_graph_init_gpc_unk_1 },
{ nvc0_graph_init_gcc_0 },
{ nvc0_graph_init_tpc_0 },
{ nvc0_graph_init_tpccs_0 },
{ nvc0_graph_init_tex_0 },
{ nvc0_graph_init_pe_0 },
{ nvc0_graph_init_l1c_0 },
{ nvc0_graph_init_wwdx_0 },
{ nvc0_graph_init_tpccs_1 },
{ nvc0_graph_init_mpc_0 },
{ nvc0_graph_init_sm_0 },
{ nvc0_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },
{ nvc0_graph_init_tpc_1 },
{ nvc0_graph_init_pe_1 },
{}
};

16
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
View File

@ -181,11 +181,20 @@ extern const struct nvc0_graph_init nvc0_graph_init_zcull_0[];
extern const struct nvc0_graph_init nvc0_graph_init_gpm_0[];
extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_1[];
extern const struct nvc0_graph_init nvc0_graph_init_gcc_0[];
extern const struct nvc0_graph_init nvc0_graph_init_tpccs_0[];
extern const struct nvc0_graph_init nvc0_graph_init_tex_0[];
extern const struct nvc0_graph_init nvc0_graph_init_pe_0[];
extern const struct nvc0_graph_init nvc0_graph_init_l1c_0[];
extern const struct nvc0_graph_init nvc0_graph_init_wwdx_0[];
extern const struct nvc0_graph_init nvc0_graph_init_tpccs_1[];
extern const struct nvc0_graph_init nvc0_graph_init_mpc_0[];
extern const struct nvc0_graph_init nvc0_graph_init_be_0[];
extern const struct nvc0_graph_init nvc0_graph_init_fe_1[];
extern const struct nvc0_graph_init nvc0_graph_init_tpc_1[];
extern const struct nvc0_graph_init nvc0_graph_init_pe_1[];
extern const struct nvc0_graph_init nvc4_graph_init_ds_0[];
extern const struct nvc0_graph_init nvc4_graph_init_tex_0[];
extern const struct nvc0_graph_init nvc4_graph_init_sm_0[];
extern const struct nvc0_graph_init nvc1_graph_init_gpc_unk_0[];
extern const struct nvc0_graph_init nvc1_graph_init_setup_1[];
@ -195,17 +204,22 @@ extern const struct nvc0_graph_init nvd9_graph_init_ds_0[];
extern const struct nvc0_graph_init nvd9_graph_init_prop_0[];
extern const struct nvc0_graph_init nvd9_graph_init_gpm_0[];
extern const struct nvc0_graph_init nvd9_graph_init_gpc_unk_1[];
extern const struct nvc0_graph_init nvd9_graph_init_tex_0[];
extern const struct nvc0_graph_init nvd9_graph_init_sm_0[];
extern const struct nvc0_graph_init nvd9_graph_init_fe_1[];
extern const struct nvc0_graph_init nvd7_graph_init_ppc_0[];
extern const struct nvc0_graph_init nve4_graph_init_main_0[];
extern const struct nvc0_graph_init nve4_graph_init_tpccs_0[];
extern const struct nvc0_graph_init nve4_graph_init_pe_0[];
extern const struct nvc0_graph_init nve4_graph_init_be_0[];
extern const struct nvc0_graph_init nvf0_graph_init_fe_0[];
extern const struct nvc0_graph_init nvf0_graph_init_sked_0[];
extern const struct nvc0_graph_init nvf0_graph_init_cwd_0[];
extern const struct nvc0_graph_init nvf0_graph_init_gpc_unk_1[];
extern const struct nvc0_graph_init nvf0_graph_init_sm_0[];
#endif

41
drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
View File

@ -70,13 +70,7 @@ nvc1_graph_init_gpc_unk_1[] = {
};
static const struct nvc0_graph_init
nvc1_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
nvc1_graph_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x419814, 1, 0x04, 0x00000004 },
@ -84,30 +78,6 @@ nvc1_graph_init_tpc_0[] = {
{ 0x41984c, 1, 0x04, 0x00005bc5 },
{ 0x419850, 4, 0x04, 0x00000000 },
{ 0x419880, 1, 0x04, 0x00000002 },
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00008bf4 },
{ 0x419cbc, 1, 0x04, 0x28137606 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{ 0x419d2c, 1, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00001100 },
{ 0x419eac, 1, 0x04, 0x11100702 },
{ 0x419eb0, 1, 0x04, 0x00000003 },
{ 0x419eb4, 4, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x0e063818 },
{ 0x419ecc, 1, 0x04, 0x0e060e06 },
{ 0x419ed0, 1, 0x04, 0x00003818 },
{ 0x419ed4, 1, 0x04, 0x011104f1 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419f2c, 1, 0x04, 0x00000000 },
{}
};
@ -129,7 +99,14 @@ nvc1_graph_pack_mmio[] = {
{ nvc0_graph_init_gpm_0 },
{ nvc1_graph_init_gpc_unk_1 },
{ nvc0_graph_init_gcc_0 },
{ nvc1_graph_init_tpc_0 },
{ nvc0_graph_init_tpccs_0 },
{ nvc4_graph_init_tex_0 },
{ nvc1_graph_init_pe_0 },
{ nvc0_graph_init_l1c_0 },
{ nvc0_graph_init_wwdx_0 },
{ nvc0_graph_init_tpccs_1 },
{ nvc0_graph_init_mpc_0 },
{ nvc4_graph_init_sm_0 },
{ nvc0_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },
{}

35
drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c
View File

@ -38,29 +38,27 @@ nvc4_graph_init_ds_0[] = {
{}
};
static const struct nvc0_graph_init
nvc4_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
const struct nvc0_graph_init
nvc4_graph_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvc4_graph_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
{ 0x419850, 4, 0x04, 0x00000000 },
{ 0x419880, 1, 0x04, 0x00000002 },
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00008bf4 },
{ 0x419cbc, 1, 0x04, 0x28137606 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{ 0x419d2c, 1, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvc4_graph_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@ -96,7 +94,14 @@ nvc4_graph_pack_mmio[] = {
{ nvc0_graph_init_gpm_0 },
{ nvc0_graph_init_gpc_unk_1 },
{ nvc0_graph_init_gcc_0 },
{ nvc4_graph_init_tpc_0 },
{ nvc0_graph_init_tpccs_0 },
{ nvc4_graph_init_tex_0 },
{ nvc4_graph_init_pe_0 },
{ nvc0_graph_init_l1c_0 },
{ nvc0_graph_init_wwdx_0 },
{ nvc0_graph_init_tpccs_1 },
{ nvc0_graph_init_mpc_0 },
{ nvc4_graph_init_sm_0 },
{ nvc0_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },
{}

32
drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
View File

@ -45,26 +45,7 @@ nvc8_graph_sclass[] = {
******************************************************************************/
static const struct nvc0_graph_init
nvc8_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
{ 0x419850, 4, 0x04, 0x00000000 },
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00008bf4 },
{ 0x419cbc, 1, 0x04, 0x28137606 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{ 0x419d2c, 1, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
nvc8_graph_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@ -99,10 +80,17 @@ nvc8_graph_pack_mmio[] = {
{ nvc0_graph_init_gpm_0 },
{ nvc0_graph_init_gpc_unk_1 },
{ nvc0_graph_init_gcc_0 },
{ nvc8_graph_init_tpc_0 },
{ nvc0_graph_init_tpccs_0 },
{ nvc0_graph_init_tex_0 },
{ nvc0_graph_init_pe_0 },
{ nvc0_graph_init_l1c_0 },
{ nvc0_graph_init_wwdx_0 },
{ nvc0_graph_init_tpccs_1 },
{ nvc0_graph_init_mpc_0 },
{ nvc8_graph_init_sm_0 },
{ nvc0_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },
{ nvc0_graph_init_tpc_1 },
{ nvc0_graph_init_pe_1 },
{}
};

37
drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
View File

@ -30,39 +30,11 @@
******************************************************************************/
static const struct nvc0_graph_init
nvd7_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
nvd7_graph_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc8 },
{ 0x419850, 3, 0x04, 0x00000000 },
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00008bf4 },
{ 0x419cbc, 1, 0x04, 0x28137606 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x02001100 },
{ 0x419eac, 1, 0x04, 0x11100702 },
{ 0x419eb0, 1, 0x04, 0x00000003 },
{ 0x419eb4, 4, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x0e063818 },
{ 0x419ecc, 1, 0x04, 0x0e060e06 },
{ 0x419ed0, 1, 0x04, 0x00003818 },
{ 0x419ed4, 1, 0x04, 0x011104f1 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419f2c, 1, 0x04, 0x00000000 },
{}
};
@ -99,7 +71,12 @@ nvd7_graph_pack_mmio[] = {
{ nvd9_graph_init_gpm_0 },
{ nvd9_graph_init_gpc_unk_1 },
{ nvc0_graph_init_gcc_0 },
{ nvd7_graph_init_tpc_0 },
{ nvc0_graph_init_tpccs_0 },
{ nvd9_graph_init_tex_0 },
{ nvd7_graph_init_pe_0 },
{ nvc0_graph_init_l1c_0 },
{ nvc0_graph_init_mpc_0 },
{ nvd9_graph_init_sm_0 },
{ nvd7_graph_init_ppc_0 },
{ nvc0_graph_init_be_0 },
{ nvd9_graph_init_fe_1 },

42
drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
View File

@ -75,15 +75,18 @@ nvd9_graph_init_gpc_unk_1[] = {
{}
};
static const struct nvc0_graph_init
nvd9_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
const struct nvc0_graph_init
nvd9_graph_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvd9_graph_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x419814, 1, 0x04, 0x00000004 },
@ -91,18 +94,26 @@ nvd9_graph_init_tpc_0[] = {
{ 0x41984c, 1, 0x04, 0x0000a918 },
{ 0x419850, 4, 0x04, 0x00000000 },
{ 0x419880, 1, 0x04, 0x00000002 },
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00008bf4 },
{ 0x419cbc, 1, 0x04, 0x28137606 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvd9_graph_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{ 0x419bf8, 2, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvd9_graph_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{ 0x419d48, 2, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvd9_graph_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@ -146,7 +157,14 @@ nvd9_graph_pack_mmio[] = {
{ nvd9_graph_init_gpm_0 },
{ nvd9_graph_init_gpc_unk_1 },
{ nvc0_graph_init_gcc_0 },
{ nvd9_graph_init_tpc_0 },
{ nvc0_graph_init_tpccs_0 },
{ nvd9_graph_init_tex_0 },
{ nvd9_graph_init_pe_0 },
{ nvc0_graph_init_l1c_0 },
{ nvd9_graph_init_wwdx_0 },
{ nvd9_graph_init_tpccs_1 },
{ nvc0_graph_init_mpc_0 },
{ nvd9_graph_init_sm_0 },
{ nvc0_graph_init_be_0 },
{ nvd9_graph_init_fe_1 },
{}

32
drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
View File

@ -93,19 +93,24 @@ nve4_graph_init_gpc_unk_1[] = {
{}
};
static const struct nvc0_graph_init
nve4_graph_init_tpc_0[] = {
const struct nvc0_graph_init
nve4_graph_init_tpccs_0[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nve4_graph_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x419850, 1, 0x04, 0x00000004 },
{ 0x419854, 2, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nve4_graph_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@ -115,7 +120,11 @@ nve4_graph_init_tpc_0[] = {
{ 0x419cbc, 1, 0x04, 0x28137646 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x00020232 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nve4_graph_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
@ -162,7 +171,12 @@ nve4_graph_pack_mmio[] = {
{ nvd9_graph_init_gpm_0 },
{ nve4_graph_init_gpc_unk_1 },
{ nvc0_graph_init_gcc_0 },
{ nve4_graph_init_tpc_0 },
{ nve4_graph_init_tpccs_0 },
{ nvd9_graph_init_tex_0 },
{ nve4_graph_init_pe_0 },
{ nve4_graph_init_l1c_0 },
{ nvc0_graph_init_mpc_0 },
{ nve4_graph_init_sm_0 },
{ nvd7_graph_init_ppc_0 },
{ nve4_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },

26
drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
View File

@ -89,9 +89,7 @@ nvf0_graph_init_gpc_unk_1[] = {
};
static const struct nvc0_graph_init
nvf0_graph_init_tpc_0[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
nvf0_graph_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@ -99,10 +97,11 @@ nvf0_graph_init_tpc_0[] = {
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
{ 0x419aa8, 2, 0x04, 0x00000000 },
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x419850, 1, 0x04, 0x00000004 },
{ 0x419854, 2, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_init
nvf0_graph_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@ -113,7 +112,11 @@ nvf0_graph_init_tpc_0[] = {
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x00020230 },
{ 0x419ccc, 2, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_init
nvf0_graph_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
@ -149,7 +152,12 @@ nvf0_graph_pack_mmio[] = {
{ nvd9_graph_init_gpm_0 },
{ nvf0_graph_init_gpc_unk_1 },
{ nvc0_graph_init_gcc_0 },
{ nvf0_graph_init_tpc_0 },
{ nve4_graph_init_tpccs_0 },
{ nvf0_graph_init_tex_0 },
{ nve4_graph_init_pe_0 },
{ nvf0_graph_init_l1c_0 },
{ nvc0_graph_init_mpc_0 },
{ nvf0_graph_init_sm_0 },
{ nvd7_graph_init_ppc_0 },
{ nve4_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },