microblaze_mmu_v2: Update exception handling - MMU exception
Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek
parent
ca54502bd5
commit
7db29dde73
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@ -53,6 +53,12 @@
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* - Illegal instruction opcode
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* - Divide-by-zero
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*
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* - Privileged instruction exception (MMU)
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* - Data storage exception (MMU)
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* - Instruction storage exception (MMU)
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* - Data TLB miss exception (MMU)
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* - Instruction TLB miss exception (MMU)
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*
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* Note we disable interrupts during exception handling, otherwise we will
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* possibly get multiple re-entrancy if interrupt handles themselves cause
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* exceptions. JW
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@ -71,9 +77,24 @@
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#include <asm/asm-offsets.h>
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/* Helpful Macros */
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#ifndef CONFIG_MMU
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#define EX_HANDLER_STACK_SIZ (4*19)
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#endif
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#define NUM_TO_REG(num) r ## num
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#ifdef CONFIG_MMU
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/* FIXME you can't change first load of MSR because there is
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* hardcoded jump bri 4 */
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#define RESTORE_STATE \
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lwi r3, r1, PT_R3; \
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lwi r4, r1, PT_R4; \
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lwi r5, r1, PT_R5; \
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lwi r6, r1, PT_R6; \
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lwi r11, r1, PT_R11; \
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lwi r31, r1, PT_R31; \
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lwi r1, r0, TOPHYS(r0_ram + 0);
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#endif /* CONFIG_MMU */
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#define LWREG_NOP \
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bri ex_handler_unhandled; \
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nop;
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@ -106,6 +127,54 @@
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or r3, r0, NUM_TO_REG (regnum); \
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bri ex_sw_tail;
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#ifdef CONFIG_MMU
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#define R3_TO_LWREG_VM_V(regnum) \
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brid ex_lw_end_vm; \
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swi r3, r7, 4 * regnum;
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#define R3_TO_LWREG_VM(regnum) \
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brid ex_lw_end_vm; \
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or NUM_TO_REG (regnum), r0, r3;
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#define SWREG_TO_R3_VM_V(regnum) \
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brid ex_sw_tail_vm; \
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lwi r3, r7, 4 * regnum;
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#define SWREG_TO_R3_VM(regnum) \
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brid ex_sw_tail_vm; \
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or r3, r0, NUM_TO_REG (regnum);
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/* Shift right instruction depending on available configuration */
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#if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
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#define BSRLI(rD, rA, imm) \
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bsrli rD, rA, imm
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#elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0
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#define BSRLI(rD, rA, imm) \
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ori rD, r0, (1 << imm); \
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idivu rD, rD, rA
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#else
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#define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
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/* Only the used shift constants defined here - add more if needed */
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#define BSRLI2(rD, rA) \
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srl rD, rA; /* << 1 */ \
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srl rD, rD; /* << 2 */
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#define BSRLI10(rD, rA) \
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srl rD, rA; /* << 1 */ \
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srl rD, rD; /* << 2 */ \
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srl rD, rD; /* << 3 */ \
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srl rD, rD; /* << 4 */ \
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srl rD, rD; /* << 5 */ \
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srl rD, rD; /* << 6 */ \
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srl rD, rD; /* << 7 */ \
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srl rD, rD; /* << 8 */ \
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srl rD, rD; /* << 9 */ \
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srl rD, rD /* << 10 */
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#define BSRLI20(rD, rA) \
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BSRLI10(rD, rA); \
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BSRLI10(rD, rD)
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#endif
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#endif /* CONFIG_MMU */
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.extern other_exception_handler /* Defined in exception.c */
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/*
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@ -163,34 +232,119 @@
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/* wrappers to restore state before coming to entry.S */
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#ifdef CONFIG_MMU
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.section .rodata
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.align 4
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_MB_HW_ExceptionVectorTable:
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/* 0 - Undefined */
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.long TOPHYS(ex_handler_unhandled)
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/* 1 - Unaligned data access exception */
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.long TOPHYS(handle_unaligned_ex)
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/* 2 - Illegal op-code exception */
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.long TOPHYS(full_exception_trapw)
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/* 3 - Instruction bus error exception */
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.long TOPHYS(full_exception_trapw)
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/* 4 - Data bus error exception */
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.long TOPHYS(full_exception_trapw)
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/* 5 - Divide by zero exception */
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.long TOPHYS(full_exception_trapw)
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/* 6 - Floating point unit exception */
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.long TOPHYS(full_exception_trapw)
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/* 7 - Privileged instruction exception */
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.long TOPHYS(full_exception_trapw)
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/* 8 - 15 - Undefined */
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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/* 16 - Data storage exception */
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.long TOPHYS(handle_data_storage_exception)
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/* 17 - Instruction storage exception */
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.long TOPHYS(handle_instruction_storage_exception)
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/* 18 - Data TLB miss exception */
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.long TOPHYS(handle_data_tlb_miss_exception)
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/* 19 - Instruction TLB miss exception */
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.long TOPHYS(handle_instruction_tlb_miss_exception)
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/* 20 - 31 - Undefined */
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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.long TOPHYS(ex_handler_unhandled)
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#endif
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.global _hw_exception_handler
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.section .text
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.align 4
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.ent _hw_exception_handler
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_hw_exception_handler:
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#ifndef CONFIG_MMU
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addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
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#else
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swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */
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/* Save date to kernel memory. Here is the problem
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* when you came from user space */
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ori r1, r0, TOPHYS(r0_ram + 28);
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#endif
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swi r3, r1, PT_R3
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swi r4, r1, PT_R4
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swi r5, r1, PT_R5
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swi r6, r1, PT_R6
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mfs r5, rmsr;
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nop
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swi r5, r1, 0;
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mfs r4, rbtr /* Save BTR before jumping to handler */
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nop
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#ifdef CONFIG_MMU
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swi r11, r1, PT_R11
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swi r31, r1, PT_R31
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lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
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#endif
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mfs r3, resr
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nop
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mfs r4, rear;
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nop
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#ifndef CONFIG_MMU
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andi r5, r3, 0x1000; /* Check ESR[DS] */
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beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
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mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
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nop
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not_in_delay_slot:
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swi r17, r1, PT_R17
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#endif
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andi r5, r3, 0x1F; /* Extract ESR[EXC] */
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#ifdef CONFIG_MMU
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/* Calculate exception vector offset = r5 << 2 */
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addk r6, r5, r5; /* << 1 */
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addk r6, r6, r6; /* << 2 */
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/* counting which exception happen */
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lwi r5, r0, 0x200 + TOPHYS(r0_ram)
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addi r5, r5, 1
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swi r5, r0, 0x200 + TOPHYS(r0_ram)
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lwi r5, r6, 0x200 + TOPHYS(r0_ram)
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addi r5, r5, 1
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swi r5, r6, 0x200 + TOPHYS(r0_ram)
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/* end */
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/* Load the HW Exception vector */
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lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
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bra r6
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full_exception_trapw:
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RESTORE_STATE
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bri full_exception_trap
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#else
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/* Exceptions enabled here. This will allow nested exceptions */
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mfs r6, rmsr;
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nop
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@ -254,6 +408,7 @@ handle_other_ex: /* Handle Other exceptions here */
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lwi r18, r1, PT_R18
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bri ex_handler_done; /* Complete exception handling */
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#endif
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/* 0x01 - Unaligned data access exception
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* This occurs when a word access is not aligned on a word boundary,
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@ -265,11 +420,28 @@ handle_other_ex: /* Handle Other exceptions here */
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handle_unaligned_ex:
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/* Working registers already saved: R3, R4, R5, R6
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* R3 = ESR
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* R4 = BTR
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* R4 = EAR
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*/
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mfs r4, rear;
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#ifdef CONFIG_MMU
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andi r6, r3, 0x1000 /* Check ESR[DS] */
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beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
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mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
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nop
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_no_delayslot:
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#endif
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#ifdef CONFIG_MMU
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/* Check if unaligned address is last on a 4k page */
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andi r5, r4, 0xffc
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xori r5, r5, 0xffc
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bnei r5, _unaligned_ex2
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_unaligned_ex1:
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RESTORE_STATE;
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/* Another page must be accessed or physical address not in page table */
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bri unaligned_data_trap
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_unaligned_ex2:
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#endif
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andi r6, r3, 0x3E0; /* Mask and extract the register operand */
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srl r6, r6; /* r6 >> 5 */
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srl r6, r6;
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@ -278,6 +450,45 @@ handle_unaligned_ex:
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srl r6, r6;
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/* Store the register operand in a temporary location */
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sbi r6, r0, TOPHYS(ex_reg_op);
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#ifdef CONFIG_MMU
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/* Get physical address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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ori r5, r0, CONFIG_KERNEL_START
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cmpu r5, r4, r5
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bgti r5, _unaligned_ex3
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ori r5, r0, swapper_pg_dir
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bri _unaligned_ex4
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/* Get the PGD for the current thread. */
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_unaligned_ex3: /* user thread */
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addi r5 ,CURRENT_TASK, TOPHYS(0); /* get current task address */
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lwi r5, r5, TASK_THREAD + PGDIR
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_unaligned_ex4:
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tophys(r5,r5)
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BSRLI(r6,r4,20) /* Create L1 (pgdir/pmd) address */
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andi r6, r6, 0xffc
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/* Assume pgdir aligned on 4K boundary, no need for "andi r5,r5,0xfffff003" */
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or r5, r5, r6
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lwi r6, r5, 0 /* Get L1 entry */
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andi r5, r6, 0xfffff000 /* Extract L2 (pte) base address. */
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beqi r5, _unaligned_ex1 /* Bail if no table */
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tophys(r5,r5)
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BSRLI(r6,r4,10) /* Compute PTE address */
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andi r6, r6, 0xffc
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andi r5, r5, 0xfffff003
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or r5, r5, r6
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lwi r5, r5, 0 /* Get Linux PTE */
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andi r6, r5, _PAGE_PRESENT
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beqi r6, _unaligned_ex1 /* Bail if no page */
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andi r5, r5, 0xfffff000 /* Extract RPN */
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andi r4, r4, 0x00000fff /* Extract offset */
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or r4, r4, r5 /* Create physical address */
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#endif /* CONFIG_MMU */
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andi r6, r3, 0x400; /* Extract ESR[S] */
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bnei r6, ex_sw;
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@ -355,6 +566,7 @@ ex_shw:
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ex_sw_end: /* Exception handling of store word, ends. */
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ex_handler_done:
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#ifndef CONFIG_MMU
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lwi r5, r1, 0 /* RMSR */
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mts rmsr, r5
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nop
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@ -366,13 +578,455 @@ ex_handler_done:
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rted r17, 0
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addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
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#else
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RESTORE_STATE;
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rted r17, 0
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nop
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#endif
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#ifdef CONFIG_MMU
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/* Exception vector entry code. This code runs with address translation
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* turned off (i.e. using physical addresses). */
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/* Exception vectors. */
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/* 0x10 - Data Storage Exception
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* This happens for just a few reasons. U0 set (but we don't do that),
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* or zone protection fault (user violation, write to protected page).
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* If this is just an update of modified status, we do that quickly
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* and exit. Otherwise, we call heavyweight functions to do the work.
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*/
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handle_data_storage_exception:
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/* Working registers already saved: R3, R4, R5, R6
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* R3 = ESR
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*/
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mfs r11, rpid
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nop
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bri 4
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mfs r3, rear /* Get faulting address */
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nop
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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ori r4, r0, CONFIG_KERNEL_START
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cmpu r4, r3, r4
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bgti r4, ex3
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/* First, check if it was a zone fault (which means a user
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* tried to access a kernel or read-protected page - always
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* a SEGV). All other faults here must be stores, so no
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* need to check ESR_S as well. */
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mfs r4, resr
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nop
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andi r4, r4, 0x800 /* ESR_Z - zone protection */
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bnei r4, ex2
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ori r4, r0, swapper_pg_dir
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mts rpid, r0 /* TLB will have 0 TID */
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nop
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bri ex4
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/* Get the PGD for the current thread. */
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ex3:
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/* First, check if it was a zone fault (which means a user
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* tried to access a kernel or read-protected page - always
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* a SEGV). All other faults here must be stores, so no
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* need to check ESR_S as well. */
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mfs r4, resr
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nop
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andi r4, r4, 0x800 /* ESR_Z */
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bnei r4, ex2
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/* get current task address */
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addi r4 ,CURRENT_TASK, TOPHYS(0);
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lwi r4, r4, TASK_THREAD+PGDIR
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ex4:
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tophys(r4,r4)
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BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
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andi r5, r5, 0xffc
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/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
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or r4, r4, r5
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lwi r4, r4, 0 /* Get L1 entry */
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andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
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beqi r5, ex2 /* Bail if no table */
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tophys(r5,r5)
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BSRLI(r6,r3,10) /* Compute PTE address */
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andi r6, r6, 0xffc
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andi r5, r5, 0xfffff003
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or r5, r5, r6
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lwi r4, r5, 0 /* Get Linux PTE */
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andi r6, r4, _PAGE_RW /* Is it writeable? */
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beqi r6, ex2 /* Bail if not */
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/* Update 'changed' */
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ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
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swi r4, r5, 0 /* Update Linux page table */
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/* Most of the Linux PTE is ready to load into the TLB LO.
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* We set ZSEL, where only the LS-bit determines user access.
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* We set execute, because we don't have the granularity to
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* properly set this at the page level (Linux problem).
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* If shared is set, we cause a zero PID->TID load.
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* Many of these bits are software only. Bits we don't set
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* here we (properly should) assume have the appropriate value.
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*/
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andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
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ori r4, r4, _PAGE_HWEXEC /* make it executable */
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/* find the TLB index that caused the fault. It has to be here*/
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mts rtlbsx, r3
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nop
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mfs r5, rtlbx /* DEBUG: TBD */
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nop
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mts rtlblo, r4 /* Load TLB LO */
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nop
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/* Will sync shadow TLBs */
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/* Done...restore registers and get out of here. */
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mts rpid, r11
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nop
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bri 4
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RESTORE_STATE;
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rted r17, 0
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nop
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ex2:
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/* The bailout. Restore registers to pre-exception conditions
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* and call the heavyweights to help us out. */
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mts rpid, r11
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nop
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bri 4
|
||||
RESTORE_STATE;
|
||||
bri page_fault_data_trap
|
||||
|
||||
|
||||
/* 0x11 - Instruction Storage Exception
|
||||
* This is caused by a fetch from non-execute or guarded pages. */
|
||||
handle_instruction_storage_exception:
|
||||
/* Working registers already saved: R3, R4, R5, R6
|
||||
* R3 = ESR
|
||||
*/
|
||||
|
||||
mfs r3, rear /* Get faulting address */
|
||||
nop
|
||||
RESTORE_STATE;
|
||||
bri page_fault_instr_trap
|
||||
|
||||
/* 0x12 - Data TLB Miss Exception
|
||||
* As the name implies, translation is not in the MMU, so search the
|
||||
* page tables and fix it. The only purpose of this function is to
|
||||
* load TLB entries from the page table if they exist.
|
||||
*/
|
||||
handle_data_tlb_miss_exception:
|
||||
/* Working registers already saved: R3, R4, R5, R6
|
||||
* R3 = ESR
|
||||
*/
|
||||
mfs r11, rpid
|
||||
nop
|
||||
bri 4
|
||||
mfs r3, rear /* Get faulting address */
|
||||
nop
|
||||
|
||||
/* If we are faulting a kernel address, we have to use the
|
||||
* kernel page tables. */
|
||||
ori r4, r0, CONFIG_KERNEL_START
|
||||
cmpu r4, r3, r4
|
||||
bgti r4, ex5
|
||||
ori r4, r0, swapper_pg_dir
|
||||
mts rpid, r0 /* TLB will have 0 TID */
|
||||
nop
|
||||
bri ex6
|
||||
|
||||
/* Get the PGD for the current thread. */
|
||||
ex5:
|
||||
/* get current task address */
|
||||
addi r4 ,CURRENT_TASK, TOPHYS(0);
|
||||
lwi r4, r4, TASK_THREAD+PGDIR
|
||||
ex6:
|
||||
tophys(r4,r4)
|
||||
BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
|
||||
andi r5, r5, 0xffc
|
||||
/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
|
||||
or r4, r4, r5
|
||||
lwi r4, r4, 0 /* Get L1 entry */
|
||||
andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
|
||||
beqi r5, ex7 /* Bail if no table */
|
||||
|
||||
tophys(r5,r5)
|
||||
BSRLI(r6,r3,10) /* Compute PTE address */
|
||||
andi r6, r6, 0xffc
|
||||
andi r5, r5, 0xfffff003
|
||||
or r5, r5, r6
|
||||
lwi r4, r5, 0 /* Get Linux PTE */
|
||||
|
||||
andi r6, r4, _PAGE_PRESENT
|
||||
beqi r6, ex7
|
||||
|
||||
ori r4, r4, _PAGE_ACCESSED
|
||||
swi r4, r5, 0
|
||||
|
||||
/* Most of the Linux PTE is ready to load into the TLB LO.
|
||||
* We set ZSEL, where only the LS-bit determines user access.
|
||||
* We set execute, because we don't have the granularity to
|
||||
* properly set this at the page level (Linux problem).
|
||||
* If shared is set, we cause a zero PID->TID load.
|
||||
* Many of these bits are software only. Bits we don't set
|
||||
* here we (properly should) assume have the appropriate value.
|
||||
*/
|
||||
andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
|
||||
|
||||
bri finish_tlb_load
|
||||
ex7:
|
||||
/* The bailout. Restore registers to pre-exception conditions
|
||||
* and call the heavyweights to help us out.
|
||||
*/
|
||||
mts rpid, r11
|
||||
nop
|
||||
bri 4
|
||||
RESTORE_STATE;
|
||||
bri page_fault_data_trap
|
||||
|
||||
/* 0x13 - Instruction TLB Miss Exception
|
||||
* Nearly the same as above, except we get our information from
|
||||
* different registers and bailout to a different point.
|
||||
*/
|
||||
handle_instruction_tlb_miss_exception:
|
||||
/* Working registers already saved: R3, R4, R5, R6
|
||||
* R3 = ESR
|
||||
*/
|
||||
mfs r11, rpid
|
||||
nop
|
||||
bri 4
|
||||
mfs r3, rear /* Get faulting address */
|
||||
nop
|
||||
|
||||
/* If we are faulting a kernel address, we have to use the
|
||||
* kernel page tables.
|
||||
*/
|
||||
ori r4, r0, CONFIG_KERNEL_START
|
||||
cmpu r4, r3, r4
|
||||
bgti r4, ex8
|
||||
ori r4, r0, swapper_pg_dir
|
||||
mts rpid, r0 /* TLB will have 0 TID */
|
||||
nop
|
||||
bri ex9
|
||||
|
||||
/* Get the PGD for the current thread. */
|
||||
ex8:
|
||||
/* get current task address */
|
||||
addi r4 ,CURRENT_TASK, TOPHYS(0);
|
||||
lwi r4, r4, TASK_THREAD+PGDIR
|
||||
ex9:
|
||||
tophys(r4,r4)
|
||||
BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
|
||||
andi r5, r5, 0xffc
|
||||
/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
|
||||
or r4, r4, r5
|
||||
lwi r4, r4, 0 /* Get L1 entry */
|
||||
andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
|
||||
beqi r5, ex10 /* Bail if no table */
|
||||
|
||||
tophys(r5,r5)
|
||||
BSRLI(r6,r3,10) /* Compute PTE address */
|
||||
andi r6, r6, 0xffc
|
||||
andi r5, r5, 0xfffff003
|
||||
or r5, r5, r6
|
||||
lwi r4, r5, 0 /* Get Linux PTE */
|
||||
|
||||
andi r6, r4, _PAGE_PRESENT
|
||||
beqi r6, ex7
|
||||
|
||||
ori r4, r4, _PAGE_ACCESSED
|
||||
swi r4, r5, 0
|
||||
|
||||
/* Most of the Linux PTE is ready to load into the TLB LO.
|
||||
* We set ZSEL, where only the LS-bit determines user access.
|
||||
* We set execute, because we don't have the granularity to
|
||||
* properly set this at the page level (Linux problem).
|
||||
* If shared is set, we cause a zero PID->TID load.
|
||||
* Many of these bits are software only. Bits we don't set
|
||||
* here we (properly should) assume have the appropriate value.
|
||||
*/
|
||||
andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
|
||||
|
||||
bri finish_tlb_load
|
||||
ex10:
|
||||
/* The bailout. Restore registers to pre-exception conditions
|
||||
* and call the heavyweights to help us out.
|
||||
*/
|
||||
mts rpid, r11
|
||||
nop
|
||||
bri 4
|
||||
RESTORE_STATE;
|
||||
bri page_fault_instr_trap
|
||||
|
||||
/* Both the instruction and data TLB miss get to this point to load the TLB.
|
||||
* r3 - EA of fault
|
||||
* r4 - TLB LO (info from Linux PTE)
|
||||
* r5, r6 - available to use
|
||||
* PID - loaded with proper value when we get here
|
||||
* Upon exit, we reload everything and RFI.
|
||||
* A common place to load the TLB.
|
||||
*/
|
||||
tlb_index:
|
||||
.long 1 /* MS: storing last used tlb index */
|
||||
finish_tlb_load:
|
||||
/* MS: load the last used TLB index. */
|
||||
lwi r5, r0, TOPHYS(tlb_index)
|
||||
addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
|
||||
|
||||
/* MS: FIXME this is potential fault, because this is mask not count */
|
||||
andi r5, r5, (MICROBLAZE_TLB_SIZE-1)
|
||||
ori r6, r0, 1
|
||||
cmp r31, r5, r6
|
||||
blti r31, sem
|
||||
addik r5, r6, 1
|
||||
sem:
|
||||
/* MS: save back current TLB index */
|
||||
swi r5, r0, TOPHYS(tlb_index)
|
||||
|
||||
ori r4, r4, _PAGE_HWEXEC /* make it executable */
|
||||
mts rtlbx, r5 /* MS: save current TLB */
|
||||
nop
|
||||
mts rtlblo, r4 /* MS: save to TLB LO */
|
||||
nop
|
||||
|
||||
/* Create EPN. This is the faulting address plus a static
|
||||
* set of bits. These are size, valid, E, U0, and ensure
|
||||
* bits 20 and 21 are zero.
|
||||
*/
|
||||
andi r3, r3, 0xfffff000
|
||||
ori r3, r3, 0x0c0
|
||||
mts rtlbhi, r3 /* Load TLB HI */
|
||||
nop
|
||||
|
||||
/* Done...restore registers and get out of here. */
|
||||
ex12:
|
||||
mts rpid, r11
|
||||
nop
|
||||
bri 4
|
||||
RESTORE_STATE;
|
||||
rted r17, 0
|
||||
nop
|
||||
|
||||
/* extern void giveup_fpu(struct task_struct *prev)
|
||||
*
|
||||
* The MicroBlaze processor may have an FPU, so this should not just
|
||||
* return: TBD.
|
||||
*/
|
||||
.globl giveup_fpu;
|
||||
.align 4;
|
||||
giveup_fpu:
|
||||
bralid r15,0 /* TBD */
|
||||
nop
|
||||
|
||||
/* At present, this routine just hangs. - extern void abort(void) */
|
||||
.globl abort;
|
||||
.align 4;
|
||||
abort:
|
||||
br r0
|
||||
|
||||
.globl set_context;
|
||||
.align 4;
|
||||
set_context:
|
||||
mts rpid, r5 /* Shadow TLBs are automatically */
|
||||
nop
|
||||
bri 4 /* flushed by changing PID */
|
||||
rtsd r15,8
|
||||
nop
|
||||
|
||||
#endif
|
||||
.end _hw_exception_handler
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
/* Unaligned data access exception last on a 4k page for MMU.
|
||||
* When this is called, we are in virtual mode with exceptions enabled
|
||||
* and registers 1-13,15,17,18 saved.
|
||||
*
|
||||
* R3 = ESR
|
||||
* R4 = EAR
|
||||
* R7 = pointer to saved registers (struct pt_regs *regs)
|
||||
*
|
||||
* This handler perform the access, and returns via ret_from_exc.
|
||||
*/
|
||||
.global _unaligned_data_exception
|
||||
.ent _unaligned_data_exception
|
||||
_unaligned_data_exception:
|
||||
andi r8, r3, 0x3E0; /* Mask and extract the register operand */
|
||||
BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */
|
||||
andi r6, r3, 0x400; /* Extract ESR[S] */
|
||||
bneid r6, ex_sw_vm;
|
||||
andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
|
||||
ex_lw_vm:
|
||||
beqid r6, ex_lhw_vm;
|
||||
lbui r5, r4, 0; /* Exception address in r4 - delay slot */
|
||||
/* Load a word, byte-by-byte from destination address and save it in tmp space*/
|
||||
la r6, r0, ex_tmp_data_loc_0;
|
||||
sbi r5, r6, 0;
|
||||
lbui r5, r4, 1;
|
||||
sbi r5, r6, 1;
|
||||
lbui r5, r4, 2;
|
||||
sbi r5, r6, 2;
|
||||
lbui r5, r4, 3;
|
||||
sbi r5, r6, 3;
|
||||
brid ex_lw_tail_vm;
|
||||
/* Get the destination register value into r3 - delay slot */
|
||||
lwi r3, r6, 0;
|
||||
ex_lhw_vm:
|
||||
/* Load a half-word, byte-by-byte from destination address and
|
||||
* save it in tmp space */
|
||||
la r6, r0, ex_tmp_data_loc_0;
|
||||
sbi r5, r6, 0;
|
||||
lbui r5, r4, 1;
|
||||
sbi r5, r6, 1;
|
||||
lhui r3, r6, 0; /* Get the destination register value into r3 */
|
||||
ex_lw_tail_vm:
|
||||
/* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
|
||||
addik r5, r8, lw_table_vm;
|
||||
bra r5;
|
||||
ex_lw_end_vm: /* Exception handling of load word, ends */
|
||||
brai ret_from_exc;
|
||||
ex_sw_vm:
|
||||
/* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
|
||||
addik r5, r8, sw_table_vm;
|
||||
bra r5;
|
||||
ex_sw_tail_vm:
|
||||
la r5, r0, ex_tmp_data_loc_0;
|
||||
beqid r6, ex_shw_vm;
|
||||
swi r3, r5, 0; /* Get the word - delay slot */
|
||||
/* Store the word, byte-by-byte into destination address */
|
||||
lbui r3, r5, 0;
|
||||
sbi r3, r4, 0;
|
||||
lbui r3, r5, 1;
|
||||
sbi r3, r4, 1;
|
||||
lbui r3, r5, 2;
|
||||
sbi r3, r4, 2;
|
||||
lbui r3, r5, 3;
|
||||
brid ret_from_exc;
|
||||
sbi r3, r4, 3; /* Delay slot */
|
||||
ex_shw_vm:
|
||||
/* Store the lower half-word, byte-by-byte into destination address */
|
||||
lbui r3, r5, 2;
|
||||
sbi r3, r4, 0;
|
||||
lbui r3, r5, 3;
|
||||
brid ret_from_exc;
|
||||
sbi r3, r4, 1; /* Delay slot */
|
||||
ex_sw_end_vm: /* Exception handling of store word, ends. */
|
||||
.end _unaligned_data_exception
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
ex_handler_unhandled:
|
||||
/* FIXME add handle function for unhandled exception - dump register */
|
||||
bri 0
|
||||
|
||||
/*
|
||||
* hw_exception_handler Jump Table
|
||||
* - Contains code snippets for each register that caused the unalign exception
|
||||
* - Hence exception handler is NOT self-modifying
|
||||
* - Separate table for load exceptions and store exceptions.
|
||||
* - Each table is of size: (8 * 32) = 256 bytes
|
||||
*/
|
||||
|
||||
.section .text
|
||||
.align 4
|
||||
lw_table:
|
||||
|
|
@ -407,7 +1061,11 @@ lw_r27: R3_TO_LWREG (27);
|
|||
lw_r28: R3_TO_LWREG (28);
|
||||
lw_r29: R3_TO_LWREG (29);
|
||||
lw_r30: R3_TO_LWREG (30);
|
||||
#ifdef CONFIG_MMU
|
||||
lw_r31: R3_TO_LWREG_V (31);
|
||||
#else
|
||||
lw_r31: R3_TO_LWREG (31);
|
||||
#endif
|
||||
|
||||
sw_table:
|
||||
sw_r0: SWREG_TO_R3 (0);
|
||||
|
|
@ -441,7 +1099,81 @@ sw_r27: SWREG_TO_R3 (27);
|
|||
sw_r28: SWREG_TO_R3 (28);
|
||||
sw_r29: SWREG_TO_R3 (29);
|
||||
sw_r30: SWREG_TO_R3 (30);
|
||||
#ifdef CONFIG_MMU
|
||||
sw_r31: SWREG_TO_R3_V (31);
|
||||
#else
|
||||
sw_r31: SWREG_TO_R3 (31);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
lw_table_vm:
|
||||
lw_r0_vm: R3_TO_LWREG_VM (0);
|
||||
lw_r1_vm: R3_TO_LWREG_VM_V (1);
|
||||
lw_r2_vm: R3_TO_LWREG_VM_V (2);
|
||||
lw_r3_vm: R3_TO_LWREG_VM_V (3);
|
||||
lw_r4_vm: R3_TO_LWREG_VM_V (4);
|
||||
lw_r5_vm: R3_TO_LWREG_VM_V (5);
|
||||
lw_r6_vm: R3_TO_LWREG_VM_V (6);
|
||||
lw_r7_vm: R3_TO_LWREG_VM_V (7);
|
||||
lw_r8_vm: R3_TO_LWREG_VM_V (8);
|
||||
lw_r9_vm: R3_TO_LWREG_VM_V (9);
|
||||
lw_r10_vm: R3_TO_LWREG_VM_V (10);
|
||||
lw_r11_vm: R3_TO_LWREG_VM_V (11);
|
||||
lw_r12_vm: R3_TO_LWREG_VM_V (12);
|
||||
lw_r13_vm: R3_TO_LWREG_VM_V (13);
|
||||
lw_r14_vm: R3_TO_LWREG_VM (14);
|
||||
lw_r15_vm: R3_TO_LWREG_VM_V (15);
|
||||
lw_r16_vm: R3_TO_LWREG_VM (16);
|
||||
lw_r17_vm: R3_TO_LWREG_VM_V (17);
|
||||
lw_r18_vm: R3_TO_LWREG_VM_V (18);
|
||||
lw_r19_vm: R3_TO_LWREG_VM (19);
|
||||
lw_r20_vm: R3_TO_LWREG_VM (20);
|
||||
lw_r21_vm: R3_TO_LWREG_VM (21);
|
||||
lw_r22_vm: R3_TO_LWREG_VM (22);
|
||||
lw_r23_vm: R3_TO_LWREG_VM (23);
|
||||
lw_r24_vm: R3_TO_LWREG_VM (24);
|
||||
lw_r25_vm: R3_TO_LWREG_VM (25);
|
||||
lw_r26_vm: R3_TO_LWREG_VM (26);
|
||||
lw_r27_vm: R3_TO_LWREG_VM (27);
|
||||
lw_r28_vm: R3_TO_LWREG_VM (28);
|
||||
lw_r29_vm: R3_TO_LWREG_VM (29);
|
||||
lw_r30_vm: R3_TO_LWREG_VM (30);
|
||||
lw_r31_vm: R3_TO_LWREG_VM_V (31);
|
||||
|
||||
sw_table_vm:
|
||||
sw_r0_vm: SWREG_TO_R3_VM (0);
|
||||
sw_r1_vm: SWREG_TO_R3_VM_V (1);
|
||||
sw_r2_vm: SWREG_TO_R3_VM_V (2);
|
||||
sw_r3_vm: SWREG_TO_R3_VM_V (3);
|
||||
sw_r4_vm: SWREG_TO_R3_VM_V (4);
|
||||
sw_r5_vm: SWREG_TO_R3_VM_V (5);
|
||||
sw_r6_vm: SWREG_TO_R3_VM_V (6);
|
||||
sw_r7_vm: SWREG_TO_R3_VM_V (7);
|
||||
sw_r8_vm: SWREG_TO_R3_VM_V (8);
|
||||
sw_r9_vm: SWREG_TO_R3_VM_V (9);
|
||||
sw_r10_vm: SWREG_TO_R3_VM_V (10);
|
||||
sw_r11_vm: SWREG_TO_R3_VM_V (11);
|
||||
sw_r12_vm: SWREG_TO_R3_VM_V (12);
|
||||
sw_r13_vm: SWREG_TO_R3_VM_V (13);
|
||||
sw_r14_vm: SWREG_TO_R3_VM (14);
|
||||
sw_r15_vm: SWREG_TO_R3_VM_V (15);
|
||||
sw_r16_vm: SWREG_TO_R3_VM (16);
|
||||
sw_r17_vm: SWREG_TO_R3_VM_V (17);
|
||||
sw_r18_vm: SWREG_TO_R3_VM_V (18);
|
||||
sw_r19_vm: SWREG_TO_R3_VM (19);
|
||||
sw_r20_vm: SWREG_TO_R3_VM (20);
|
||||
sw_r21_vm: SWREG_TO_R3_VM (21);
|
||||
sw_r22_vm: SWREG_TO_R3_VM (22);
|
||||
sw_r23_vm: SWREG_TO_R3_VM (23);
|
||||
sw_r24_vm: SWREG_TO_R3_VM (24);
|
||||
sw_r25_vm: SWREG_TO_R3_VM (25);
|
||||
sw_r26_vm: SWREG_TO_R3_VM (26);
|
||||
sw_r27_vm: SWREG_TO_R3_VM (27);
|
||||
sw_r28_vm: SWREG_TO_R3_VM (28);
|
||||
sw_r29_vm: SWREG_TO_R3_VM (29);
|
||||
sw_r30_vm: SWREG_TO_R3_VM (30);
|
||||
sw_r31_vm: SWREG_TO_R3_VM_V (31);
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
/* Temporary data structures used in the handler */
|
||||
.section .data
|
||||
|
|
|
|||
Loading…
Reference in New Issue