PM / devfreq: move definitions for exynos4_bus into drivers/devfreq
We don't need to keep the definitions for exynos4_bus into mach-exynos/ so this moves them into drviers/devfreq with adding header file. Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Kukjin Kim
parent
728599439f
commit
7d8f159188
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@ -18,12 +18,6 @@
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#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
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#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
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#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
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#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
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#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
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#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
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#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
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@ -41,24 +35,7 @@
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#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
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#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
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#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
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#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
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#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
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#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
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#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
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#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
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#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
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#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
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#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
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#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
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#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
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#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
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#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
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#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
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#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
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#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
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@ -74,81 +51,10 @@
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#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
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#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
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#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
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#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
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#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
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#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
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#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
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#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
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#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
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#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
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#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
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#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
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#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
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#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
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#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
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#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
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#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
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#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
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#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
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#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
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#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
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#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
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#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
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#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
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#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
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#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
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#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
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#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
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#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
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#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
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#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
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#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
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#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
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/* Only for EXYNOS4210 */
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#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
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/* Only for EXYNOS4212 */
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#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
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#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
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#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
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#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
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/* For EXYNOS5250 */
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#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
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@ -30,10 +30,10 @@
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extern unsigned int exynos_result_of_asv;
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#endif
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#include <mach/regs-clock.h>
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#include <plat/map-s5p.h>
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#include "exynos4_bus.h"
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#define MAX_SAFEVOLT 1200000 /* 1.2V */
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enum exynos4_busf_type {
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@ -0,0 +1,110 @@
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* EXYNOS4 BUS header
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DEVFREQ_EXYNOS4_BUS_H
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#define __DEVFREQ_EXYNOS4_BUS_H __FILE__
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#include <mach/map.h>
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#define EXYNOS4_CLKDIV_LEFTBUS (S5P_VA_CMU + 0x04500)
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#define EXYNOS4_CLKDIV_STAT_LEFTBUS (S5P_VA_CMU + 0x04600)
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#define EXYNOS4_CLKDIV_RIGHTBUS (S5P_VA_CMU + 0x08500)
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#define EXYNOS4_CLKDIV_STAT_RIGHTBUS (S5P_VA_CMU + 0x08600)
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#define EXYNOS4_CLKDIV_TOP (S5P_VA_CMU + 0x0C510)
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#define EXYNOS4_CLKDIV_CAM (S5P_VA_CMU + 0x0C520)
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#define EXYNOS4_CLKDIV_MFC (S5P_VA_CMU + 0x0C528)
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#define EXYNOS4_CLKDIV_STAT_TOP (S5P_VA_CMU + 0x0C610)
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#define EXYNOS4_CLKDIV_STAT_MFC (S5P_VA_CMU + 0x0C628)
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#define EXYNOS4210_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x0C930)
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#define EXYNOS4212_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x04930)
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#define EXYNOS4_CLKDIV_DMC0 (S5P_VA_CMU + 0x10500)
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#define EXYNOS4_CLKDIV_DMC1 (S5P_VA_CMU + 0x10504)
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#define EXYNOS4_CLKDIV_STAT_DMC0 (S5P_VA_CMU + 0x10600)
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#define EXYNOS4_CLKDIV_STAT_DMC1 (S5P_VA_CMU + 0x10604)
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#define EXYNOS4_DMC_PAUSE_CTRL (S5P_VA_CMU + 0x11094)
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#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
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#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
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#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
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#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
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#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
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#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
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#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
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#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
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#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
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#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
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#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
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#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
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#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
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#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
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#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
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#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
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#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
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#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
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#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
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#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
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#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
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#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
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#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
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#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
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#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
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#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
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#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
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#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
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#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
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#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
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#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
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#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
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#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
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#define EXYNOS4_CLKDIV_CAM1 (S5P_VA_CMU + 0x0C568)
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#define EXYNOS4_CLKDIV_STAT_CAM1 (S5P_VA_CMU + 0x0C668)
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#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
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#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
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#endif /* __DEVFREQ_EXYNOS4_BUS_H */
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