alpha: kill off alpha_do_IRQ
Good riddance... Nuke a pile of redundant handlers that the generic code takes care of as well. Tested-by: Michael Cree <mcree@orcon.net.nz> Signed-off-by: Kyle McMartin <kyle@redhat.com> Signed-off-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
parent
a891b393dd
commit
7d209c8110
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@ -88,7 +88,4 @@ static __inline__ int irq_canonicalize(int irq)
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struct pt_regs;
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struct pt_regs;
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extern void (*perf_irq)(unsigned long, struct pt_regs *);
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extern void (*perf_irq)(unsigned long, struct pt_regs *);
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struct irq_desc;
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extern void alpha_do_IRQ(unsigned int irq, struct irq_desc *desc);
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#endif /* _ALPHA_IRQ_H */
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#endif /* _ALPHA_IRQ_H */
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@ -162,7 +162,7 @@ handle_irq(int irq)
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irq_enter();
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irq_enter();
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/*
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/*
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* __do_IRQ() must be called with IPL_MAX. Note that we do not
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* handle_irq() must be called with IPL_MAX. Note that we do not
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* explicitly enable interrupts afterwards - some MILO PALcode
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* explicitly enable interrupts afterwards - some MILO PALcode
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* (namely LX164 one) seems to have severe problems with RTI
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* (namely LX164 one) seems to have severe problems with RTI
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* at IPL 0.
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* at IPL 0.
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@ -172,7 +172,3 @@ handle_irq(int irq)
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irq_exit();
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irq_exit();
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}
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}
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void alpha_do_IRQ(unsigned int irq, struct irq_desc *desc)
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{
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__do_IRQ(irq);
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}
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@ -219,25 +219,12 @@ process_mcheck_info(unsigned long vector, unsigned long la_ptr,
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* processed by PALcode, and comes in via entInt vector 1.
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* processed by PALcode, and comes in via entInt vector 1.
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*/
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*/
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static void rtc_enable_disable(unsigned int irq) { }
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static unsigned int rtc_startup(unsigned int irq) { return 0; }
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struct irqaction timer_irqaction = {
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struct irqaction timer_irqaction = {
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.handler = timer_interrupt,
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED,
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.flags = IRQF_DISABLED,
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.name = "timer",
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.name = "timer",
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};
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};
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static struct irq_chip rtc_irq_type = {
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.name = "RTC",
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.startup = rtc_startup,
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.shutdown = rtc_enable_disable,
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.enable = rtc_enable_disable,
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.disable = rtc_enable_disable,
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.ack = rtc_enable_disable,
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.end = rtc_enable_disable,
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};
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void __init
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void __init
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init_rtc_irq(void)
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init_rtc_irq(void)
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{
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{
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@ -245,7 +232,8 @@ init_rtc_irq(void)
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if (desc) {
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if (desc) {
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desc->status |= IRQ_DISABLED;
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desc->status |= IRQ_DISABLED;
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set_irq_chip(RTC_IRQ, &rtc_irq_type);
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set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
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handle_simple_irq, "RTC");
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setup_irq(RTC_IRQ, &timer_irqaction);
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setup_irq(RTC_IRQ, &timer_irqaction);
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}
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}
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}
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}
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@ -69,29 +69,11 @@ i8259a_mask_and_ack_irq(unsigned int irq)
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spin_unlock(&i8259_irq_lock);
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spin_unlock(&i8259_irq_lock);
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}
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}
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unsigned int
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i8259a_startup_irq(unsigned int irq)
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{
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i8259a_enable_irq(irq);
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return 0; /* never anything pending */
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}
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void
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i8259a_end_irq(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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if (desc || !(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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i8259a_enable_irq(irq);
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}
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struct irq_chip i8259a_irq_type = {
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struct irq_chip i8259a_irq_type = {
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.name = "XT-PIC",
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.name = "XT-PIC",
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.startup = i8259a_startup_irq,
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.unmask = i8259a_enable_irq,
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.shutdown = i8259a_disable_irq,
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.mask = i8259a_disable_irq,
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.enable = i8259a_enable_irq,
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.mask_ack = i8259a_mask_and_ack_irq,
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.disable = i8259a_disable_irq,
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.ack = i8259a_mask_and_ack_irq,
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.end = i8259a_end_irq,
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};
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};
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void __init
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void __init
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@ -108,7 +90,7 @@ init_i8259a_irqs(void)
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outb(0xff, 0xA1); /* mask all of 8259A-2 */
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outb(0xff, 0xA1); /* mask all of 8259A-2 */
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for (i = 0; i < 16; i++) {
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for (i = 0; i < 16; i++) {
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set_irq_chip_and_handler(i, &i8259a_irq_type, alpha_do_IRQ);
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set_irq_chip_and_handler(i, &i8259a_irq_type, handle_level_irq);
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}
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}
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setup_irq(2, &cascade);
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setup_irq(2, &cascade);
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@ -40,21 +40,6 @@ pyxis_disable_irq(unsigned int irq)
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pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
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pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
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}
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}
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static unsigned int
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pyxis_startup_irq(unsigned int irq)
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{
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pyxis_enable_irq(irq);
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return 0;
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}
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static void
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pyxis_end_irq(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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if (desc || !(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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pyxis_enable_irq(irq);
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}
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static void
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static void
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pyxis_mask_and_ack_irq(unsigned int irq)
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pyxis_mask_and_ack_irq(unsigned int irq)
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{
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{
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@ -73,12 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq)
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static struct irq_chip pyxis_irq_type = {
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static struct irq_chip pyxis_irq_type = {
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.name = "PYXIS",
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.name = "PYXIS",
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.startup = pyxis_startup_irq,
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.mask_ack = pyxis_mask_and_ack_irq,
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.shutdown = pyxis_disable_irq,
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.mask = pyxis_disable_irq,
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.enable = pyxis_enable_irq,
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.unmask = pyxis_enable_irq,
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.disable = pyxis_disable_irq,
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.ack = pyxis_mask_and_ack_irq,
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.end = pyxis_end_irq,
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};
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};
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void
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void
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@ -120,7 +102,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
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for (i = 16; i < 48; ++i) {
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for (i = 16; i < 48; ++i) {
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if ((ignore_mask >> i) & 1)
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if ((ignore_mask >> i) & 1)
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continue;
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continue;
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set_irq_chip_and_handler(i, &pyxis_irq_type, alpha_do_IRQ);
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set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
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irq_to_desc(i)->status |= IRQ_LEVEL;
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irq_to_desc(i)->status |= IRQ_LEVEL;
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}
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}
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@ -33,29 +33,12 @@ srm_disable_irq(unsigned int irq)
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spin_unlock(&srm_irq_lock);
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spin_unlock(&srm_irq_lock);
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}
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}
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static unsigned int
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srm_startup_irq(unsigned int irq)
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{
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srm_enable_irq(irq);
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return 0;
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}
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static void
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srm_end_irq(unsigned int irq)
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{
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if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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srm_enable_irq(irq);
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}
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/* Handle interrupts from the SRM, assuming no additional weirdness. */
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/* Handle interrupts from the SRM, assuming no additional weirdness. */
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static struct irq_chip srm_irq_type = {
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static struct irq_chip srm_irq_type = {
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.name = "SRM",
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.name = "SRM",
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.startup = srm_startup_irq,
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.unmask = srm_enable_irq,
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.shutdown = srm_disable_irq,
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.mask = srm_disable_irq,
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.enable = srm_enable_irq,
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.mask_ack = srm_disable_irq,
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.disable = srm_disable_irq,
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.ack = srm_disable_irq,
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.end = srm_end_irq,
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};
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};
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void __init
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void __init
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@ -68,7 +51,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
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for (i = 16; i < max; ++i) {
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for (i = 16; i < max; ++i) {
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if (i < 64 && ((ignore_mask >> i) & 1))
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if (i < 64 && ((ignore_mask >> i) & 1))
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continue;
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continue;
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set_irq_chip_and_handler(i, &srm_irq_type, alpha_do_IRQ);
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set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
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irq_to_desc(i)->status |= IRQ_LEVEL;
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irq_to_desc(i)->status |= IRQ_LEVEL;
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}
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}
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}
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}
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@ -65,13 +65,6 @@ alcor_mask_and_ack_irq(unsigned int irq)
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*(vuip)GRU_INT_CLEAR = 0; mb();
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*(vuip)GRU_INT_CLEAR = 0; mb();
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}
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}
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static unsigned int
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alcor_startup_irq(unsigned int irq)
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{
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alcor_enable_irq(irq);
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return 0;
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}
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static void
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static void
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alcor_isa_mask_and_ack_irq(unsigned int irq)
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alcor_isa_mask_and_ack_irq(unsigned int irq)
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{
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{
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*(vuip)GRU_INT_CLEAR = 0; mb();
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*(vuip)GRU_INT_CLEAR = 0; mb();
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}
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}
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static void
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alcor_end_irq(unsigned int irq)
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{
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if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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alcor_enable_irq(irq);
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}
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static struct irq_chip alcor_irq_type = {
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static struct irq_chip alcor_irq_type = {
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.name = "ALCOR",
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.name = "ALCOR",
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.startup = alcor_startup_irq,
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.unmask = alcor_enable_irq,
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.shutdown = alcor_disable_irq,
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.mask = alcor_disable_irq,
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.enable = alcor_enable_irq,
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.mask_ack = alcor_mask_and_ack_irq,
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.disable = alcor_disable_irq,
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.ack = alcor_mask_and_ack_irq,
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.end = alcor_end_irq,
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};
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};
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static void
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static void
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on while IRQ probing. */
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on while IRQ probing. */
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if (i >= 16+20 && i <= 16+30)
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if (i >= 16+20 && i <= 16+30)
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continue;
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continue;
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set_irq_chip_and_handler(i, &alcor_irq_type, alpha_do_IRQ);
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set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
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irq_to_desc(i)->status |= IRQ_LEVEL;
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irq_to_desc(i)->status |= IRQ_LEVEL;
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}
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}
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i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
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i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
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@ -57,28 +57,11 @@ cabriolet_disable_irq(unsigned int irq)
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cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
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cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
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}
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}
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static unsigned int
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cabriolet_startup_irq(unsigned int irq)
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{
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cabriolet_enable_irq(irq);
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return 0; /* never anything pending */
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}
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static void
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cabriolet_end_irq(unsigned int irq)
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{
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if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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cabriolet_enable_irq(irq);
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}
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static struct irq_chip cabriolet_irq_type = {
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static struct irq_chip cabriolet_irq_type = {
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.name = "CABRIOLET",
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.name = "CABRIOLET",
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.startup = cabriolet_startup_irq,
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.unmask = cabriolet_enable_irq,
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.shutdown = cabriolet_disable_irq,
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.mask = cabriolet_disable_irq,
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.enable = cabriolet_enable_irq,
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.mask_ack = cabriolet_disable_irq,
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.disable = cabriolet_disable_irq,
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.ack = cabriolet_disable_irq,
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.end = cabriolet_end_irq,
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};
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};
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static void
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static void
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@ -123,7 +106,7 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
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for (i = 16; i < 35; ++i) {
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for (i = 16; i < 35; ++i) {
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set_irq_chip_and_handler(i, &cabriolet_irq_type,
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set_irq_chip_and_handler(i, &cabriolet_irq_type,
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alpha_do_IRQ);
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handle_level_irq);
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irq_to_desc(i)->status |= IRQ_LEVEL;
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irq_to_desc(i)->status |= IRQ_LEVEL;
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}
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}
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}
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}
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@ -115,20 +115,6 @@ dp264_disable_irq(unsigned int irq)
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spin_unlock(&dp264_irq_lock);
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spin_unlock(&dp264_irq_lock);
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}
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}
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static unsigned int
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dp264_startup_irq(unsigned int irq)
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{
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dp264_enable_irq(irq);
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return 0; /* never anything pending */
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}
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static void
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dp264_end_irq(unsigned int irq)
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{
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if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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dp264_enable_irq(irq);
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}
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static void
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static void
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clipper_enable_irq(unsigned int irq)
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clipper_enable_irq(unsigned int irq)
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{
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{
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@ -147,20 +133,6 @@ clipper_disable_irq(unsigned int irq)
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spin_unlock(&dp264_irq_lock);
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spin_unlock(&dp264_irq_lock);
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}
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}
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static unsigned int
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clipper_startup_irq(unsigned int irq)
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{
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clipper_enable_irq(irq);
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return 0; /* never anything pending */
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}
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static void
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clipper_end_irq(unsigned int irq)
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{
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if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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clipper_enable_irq(irq);
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}
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static void
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static void
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cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
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cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
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{
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{
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@ -200,23 +172,17 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
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static struct irq_chip dp264_irq_type = {
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static struct irq_chip dp264_irq_type = {
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.name = "DP264",
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.name = "DP264",
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.startup = dp264_startup_irq,
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.unmask = dp264_enable_irq,
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.shutdown = dp264_disable_irq,
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.mask = dp264_disable_irq,
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.enable = dp264_enable_irq,
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.mask_ack = dp264_disable_irq,
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.disable = dp264_disable_irq,
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|
||||||
.ack = dp264_disable_irq,
|
|
||||||
.end = dp264_end_irq,
|
|
||||||
.set_affinity = dp264_set_affinity,
|
.set_affinity = dp264_set_affinity,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct irq_chip clipper_irq_type = {
|
static struct irq_chip clipper_irq_type = {
|
||||||
.name = "CLIPPER",
|
.name = "CLIPPER",
|
||||||
.startup = clipper_startup_irq,
|
.unmask = clipper_enable_irq,
|
||||||
.shutdown = clipper_disable_irq,
|
.mask = clipper_disable_irq,
|
||||||
.enable = clipper_enable_irq,
|
.mask_ack = clipper_disable_irq,
|
||||||
.disable = clipper_disable_irq,
|
|
||||||
.ack = clipper_disable_irq,
|
|
||||||
.end = clipper_end_irq,
|
|
||||||
.set_affinity = clipper_set_affinity,
|
.set_affinity = clipper_set_affinity,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -303,7 +269,7 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
|
||||||
long i;
|
long i;
|
||||||
for (i = imin; i <= imax; ++i) {
|
for (i = imin; i <= imax; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, ops, alpha_do_IRQ);
|
set_irq_chip_and_handler(i, ops, handle_level_irq);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -55,28 +55,11 @@ eb64p_disable_irq(unsigned int irq)
|
||||||
eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
|
eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
eb64p_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
eb64p_enable_irq(irq);
|
|
||||||
return 0; /* never anything pending */
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
eb64p_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
eb64p_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct irq_chip eb64p_irq_type = {
|
static struct irq_chip eb64p_irq_type = {
|
||||||
.name = "EB64P",
|
.name = "EB64P",
|
||||||
.startup = eb64p_startup_irq,
|
.unmask = eb64p_enable_irq,
|
||||||
.shutdown = eb64p_disable_irq,
|
.mask = eb64p_disable_irq,
|
||||||
.enable = eb64p_enable_irq,
|
.mask_ack = eb64p_disable_irq,
|
||||||
.disable = eb64p_disable_irq,
|
|
||||||
.ack = eb64p_disable_irq,
|
|
||||||
.end = eb64p_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -136,7 +119,7 @@ eb64p_init_irq(void)
|
||||||
|
|
||||||
for (i = 16; i < 32; ++i) {
|
for (i = 16; i < 32; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, &eb64p_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
common_init_isa_dma();
|
common_init_isa_dma();
|
||||||
|
|
|
@ -66,28 +66,11 @@ eiger_disable_irq(unsigned int irq)
|
||||||
eiger_update_irq_hw(irq, mask);
|
eiger_update_irq_hw(irq, mask);
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
eiger_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
eiger_enable_irq(irq);
|
|
||||||
return 0; /* never anything pending */
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
eiger_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
eiger_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct irq_chip eiger_irq_type = {
|
static struct irq_chip eiger_irq_type = {
|
||||||
.name = "EIGER",
|
.name = "EIGER",
|
||||||
.startup = eiger_startup_irq,
|
.unmask = eiger_enable_irq,
|
||||||
.shutdown = eiger_disable_irq,
|
.mask = eiger_disable_irq,
|
||||||
.enable = eiger_enable_irq,
|
.mask_ack = eiger_disable_irq,
|
||||||
.disable = eiger_disable_irq,
|
|
||||||
.ack = eiger_disable_irq,
|
|
||||||
.end = eiger_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -154,7 +137,7 @@ eiger_init_irq(void)
|
||||||
|
|
||||||
for (i = 16; i < 128; ++i) {
|
for (i = 16; i < 128; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, &eiger_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -62,24 +62,6 @@
|
||||||
* world.
|
* world.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
jensen_local_startup(unsigned int irq)
|
|
||||||
{
|
|
||||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
|
||||||
if (irq == 7)
|
|
||||||
i8259a_startup_irq(1);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
jensen_local_shutdown(unsigned int irq)
|
|
||||||
{
|
|
||||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
|
||||||
if (irq == 7)
|
|
||||||
i8259a_disable_irq(1);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
static void
|
||||||
jensen_local_enable(unsigned int irq)
|
jensen_local_enable(unsigned int irq)
|
||||||
{
|
{
|
||||||
|
@ -97,29 +79,18 @@ jensen_local_disable(unsigned int irq)
|
||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void
|
||||||
jensen_local_ack(unsigned int irq)
|
jensen_local_mask_ack(unsigned int irq)
|
||||||
{
|
{
|
||||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
/* the parport is really hw IRQ 1, silly Jensen. */
|
||||||
if (irq == 7)
|
if (irq == 7)
|
||||||
i8259a_mask_and_ack_irq(1);
|
i8259a_mask_and_ack_irq(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void
|
|
||||||
jensen_local_end(unsigned int irq)
|
|
||||||
{
|
|
||||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
|
||||||
if (irq == 7)
|
|
||||||
i8259a_end_irq(1);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct irq_chip jensen_local_irq_type = {
|
static struct irq_chip jensen_local_irq_type = {
|
||||||
.name = "LOCAL",
|
.name = "LOCAL",
|
||||||
.startup = jensen_local_startup,
|
.unmask = jensen_local_enable,
|
||||||
.shutdown = jensen_local_shutdown,
|
.mask = jensen_local_disable,
|
||||||
.enable = jensen_local_enable,
|
.mask_ack = jensen_local_mask_ack,
|
||||||
.disable = jensen_local_disable,
|
|
||||||
.ack = jensen_local_ack,
|
|
||||||
.end = jensen_local_end,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -200,11 +171,11 @@ jensen_init_irq(void)
|
||||||
{
|
{
|
||||||
init_i8259a_irqs();
|
init_i8259a_irqs();
|
||||||
|
|
||||||
set_irq_chip_and_handler(1, &jensen_local_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq);
|
||||||
set_irq_chip_and_handler(4, &jensen_local_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq);
|
||||||
set_irq_chip_and_handler(3, &jensen_local_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq);
|
||||||
set_irq_chip_and_handler(7, &jensen_local_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq);
|
||||||
set_irq_chip_and_handler(9, &jensen_local_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq);
|
||||||
|
|
||||||
common_init_isa_dma();
|
common_init_isa_dma();
|
||||||
}
|
}
|
||||||
|
|
|
@ -143,20 +143,6 @@ io7_disable_irq(unsigned int irq)
|
||||||
spin_unlock(&io7->irq_lock);
|
spin_unlock(&io7->irq_lock);
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
io7_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
io7_enable_irq(irq);
|
|
||||||
return 0; /* never anything pending */
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
io7_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
io7_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
static void
|
||||||
marvel_irq_noop(unsigned int irq)
|
marvel_irq_noop(unsigned int irq)
|
||||||
{
|
{
|
||||||
|
@ -171,32 +157,22 @@ marvel_irq_noop_return(unsigned int irq)
|
||||||
|
|
||||||
static struct irq_chip marvel_legacy_irq_type = {
|
static struct irq_chip marvel_legacy_irq_type = {
|
||||||
.name = "LEGACY",
|
.name = "LEGACY",
|
||||||
.startup = marvel_irq_noop_return,
|
.mask = marvel_irq_noop,
|
||||||
.shutdown = marvel_irq_noop,
|
.unmask = marvel_irq_noop,
|
||||||
.enable = marvel_irq_noop,
|
|
||||||
.disable = marvel_irq_noop,
|
|
||||||
.ack = marvel_irq_noop,
|
|
||||||
.end = marvel_irq_noop,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct irq_chip io7_lsi_irq_type = {
|
static struct irq_chip io7_lsi_irq_type = {
|
||||||
.name = "LSI",
|
.name = "LSI",
|
||||||
.startup = io7_startup_irq,
|
.unmask = io7_enable_irq,
|
||||||
.shutdown = io7_disable_irq,
|
.mask = io7_disable_irq,
|
||||||
.enable = io7_enable_irq,
|
.mask_ack = io7_disable_irq,
|
||||||
.disable = io7_disable_irq,
|
|
||||||
.ack = io7_disable_irq,
|
|
||||||
.end = io7_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct irq_chip io7_msi_irq_type = {
|
static struct irq_chip io7_msi_irq_type = {
|
||||||
.name = "MSI",
|
.name = "MSI",
|
||||||
.startup = io7_startup_irq,
|
.unmask = io7_enable_irq,
|
||||||
.shutdown = io7_disable_irq,
|
.mask = io7_disable_irq,
|
||||||
.enable = io7_enable_irq,
|
|
||||||
.disable = io7_disable_irq,
|
|
||||||
.ack = marvel_irq_noop,
|
.ack = marvel_irq_noop,
|
||||||
.end = io7_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -305,7 +281,7 @@ init_io7_irqs(struct io7 *io7,
|
||||||
/* Set up the lsi irqs. */
|
/* Set up the lsi irqs. */
|
||||||
for (i = 0; i < 128; ++i) {
|
for (i = 0; i < 128; ++i) {
|
||||||
irq_to_desc(base + i)->status |= IRQ_LEVEL;
|
irq_to_desc(base + i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(base + i, lsi_ops, alpha_do_IRQ);
|
set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Disable the implemented irqs in hardware. */
|
/* Disable the implemented irqs in hardware. */
|
||||||
|
@ -319,7 +295,7 @@ init_io7_irqs(struct io7 *io7,
|
||||||
/* Set up the msi irqs. */
|
/* Set up the msi irqs. */
|
||||||
for (i = 128; i < (128 + 512); ++i) {
|
for (i = 128; i < (128 + 512); ++i) {
|
||||||
irq_to_desc(base + i)->status |= IRQ_LEVEL;
|
irq_to_desc(base + i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(base + i, msi_ops, alpha_do_IRQ);
|
set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < 16; ++i)
|
for (i = 0; i < 16; ++i)
|
||||||
|
@ -337,7 +313,7 @@ marvel_init_irq(void)
|
||||||
/* Reserve the legacy irqs. */
|
/* Reserve the legacy irqs. */
|
||||||
for (i = 0; i < 16; ++i) {
|
for (i = 0; i < 16; ++i) {
|
||||||
set_irq_chip_and_handler(i, &marvel_legacy_irq_type,
|
set_irq_chip_and_handler(i, &marvel_legacy_irq_type,
|
||||||
alpha_do_IRQ);
|
handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Init the io7 irqs. */
|
/* Init the io7 irqs. */
|
||||||
|
|
|
@ -54,28 +54,11 @@ mikasa_disable_irq(unsigned int irq)
|
||||||
mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
|
mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
mikasa_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
mikasa_enable_irq(irq);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
mikasa_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
mikasa_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct irq_chip mikasa_irq_type = {
|
static struct irq_chip mikasa_irq_type = {
|
||||||
.name = "MIKASA",
|
.name = "MIKASA",
|
||||||
.startup = mikasa_startup_irq,
|
.unmask = mikasa_enable_irq,
|
||||||
.shutdown = mikasa_disable_irq,
|
.mask = mikasa_disable_irq,
|
||||||
.enable = mikasa_enable_irq,
|
.mask_ack = mikasa_disable_irq,
|
||||||
.disable = mikasa_disable_irq,
|
|
||||||
.ack = mikasa_disable_irq,
|
|
||||||
.end = mikasa_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -116,7 +99,7 @@ mikasa_init_irq(void)
|
||||||
|
|
||||||
for (i = 16; i < 32; ++i) {
|
for (i = 16; i < 32; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, &mikasa_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
init_i8259a_irqs();
|
init_i8259a_irqs();
|
||||||
|
|
|
@ -59,28 +59,11 @@ noritake_disable_irq(unsigned int irq)
|
||||||
noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
|
noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
noritake_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
noritake_enable_irq(irq);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
noritake_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
noritake_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct irq_chip noritake_irq_type = {
|
static struct irq_chip noritake_irq_type = {
|
||||||
.name = "NORITAKE",
|
.name = "NORITAKE",
|
||||||
.startup = noritake_startup_irq,
|
.unmask = noritake_enable_irq,
|
||||||
.shutdown = noritake_disable_irq,
|
.mask = noritake_disable_irq,
|
||||||
.enable = noritake_enable_irq,
|
.mask_ack = noritake_disable_irq,
|
||||||
.disable = noritake_disable_irq,
|
|
||||||
.ack = noritake_disable_irq,
|
|
||||||
.end = noritake_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -145,7 +128,7 @@ noritake_init_irq(void)
|
||||||
|
|
||||||
for (i = 16; i < 48; ++i) {
|
for (i = 16; i < 48; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, &noritake_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
init_i8259a_irqs();
|
init_i8259a_irqs();
|
||||||
|
|
|
@ -121,28 +121,11 @@ rawhide_mask_and_ack_irq(unsigned int irq)
|
||||||
spin_unlock(&rawhide_irq_lock);
|
spin_unlock(&rawhide_irq_lock);
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
rawhide_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
rawhide_enable_irq(irq);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
rawhide_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
rawhide_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct irq_chip rawhide_irq_type = {
|
static struct irq_chip rawhide_irq_type = {
|
||||||
.name = "RAWHIDE",
|
.name = "RAWHIDE",
|
||||||
.startup = rawhide_startup_irq,
|
.unmask = rawhide_enable_irq,
|
||||||
.shutdown = rawhide_disable_irq,
|
.mask = rawhide_disable_irq,
|
||||||
.enable = rawhide_enable_irq,
|
.mask_ack = rawhide_mask_and_ack_irq,
|
||||||
.disable = rawhide_disable_irq,
|
|
||||||
.ack = rawhide_mask_and_ack_irq,
|
|
||||||
.end = rawhide_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -195,7 +178,7 @@ rawhide_init_irq(void)
|
||||||
|
|
||||||
for (i = 16; i < 128; ++i) {
|
for (i = 16; i < 128; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, &rawhide_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
init_i8259a_irqs();
|
init_i8259a_irqs();
|
||||||
|
|
|
@ -58,28 +58,11 @@ rx164_disable_irq(unsigned int irq)
|
||||||
rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
|
rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
rx164_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
rx164_enable_irq(irq);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
rx164_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
rx164_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct irq_chip rx164_irq_type = {
|
static struct irq_chip rx164_irq_type = {
|
||||||
.name = "RX164",
|
.name = "RX164",
|
||||||
.startup = rx164_startup_irq,
|
.unmask = rx164_enable_irq,
|
||||||
.shutdown = rx164_disable_irq,
|
.mask = rx164_disable_irq,
|
||||||
.enable = rx164_enable_irq,
|
.mask_ack = rx164_disable_irq,
|
||||||
.disable = rx164_disable_irq,
|
|
||||||
.ack = rx164_disable_irq,
|
|
||||||
.end = rx164_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -117,7 +100,7 @@ rx164_init_irq(void)
|
||||||
rx164_update_irq_hw(0);
|
rx164_update_irq_hw(0);
|
||||||
for (i = 16; i < 40; ++i) {
|
for (i = 16; i < 40; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, &rx164_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
init_i8259a_irqs();
|
init_i8259a_irqs();
|
||||||
|
|
|
@ -474,20 +474,6 @@ sable_lynx_disable_irq(unsigned int irq)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
sable_lynx_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
sable_lynx_enable_irq(irq);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
sable_lynx_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
sable_lynx_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
static void
|
||||||
sable_lynx_mask_and_ack_irq(unsigned int irq)
|
sable_lynx_mask_and_ack_irq(unsigned int irq)
|
||||||
{
|
{
|
||||||
|
@ -503,12 +489,9 @@ sable_lynx_mask_and_ack_irq(unsigned int irq)
|
||||||
|
|
||||||
static struct irq_chip sable_lynx_irq_type = {
|
static struct irq_chip sable_lynx_irq_type = {
|
||||||
.name = "SABLE/LYNX",
|
.name = "SABLE/LYNX",
|
||||||
.startup = sable_lynx_startup_irq,
|
.unmask = sable_lynx_enable_irq,
|
||||||
.shutdown = sable_lynx_disable_irq,
|
.mask = sable_lynx_disable_irq,
|
||||||
.enable = sable_lynx_enable_irq,
|
.mask_ack = sable_lynx_mask_and_ack_irq,
|
||||||
.disable = sable_lynx_disable_irq,
|
|
||||||
.ack = sable_lynx_mask_and_ack_irq,
|
|
||||||
.end = sable_lynx_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -537,7 +520,7 @@ sable_lynx_init_irq(int nr_of_irqs)
|
||||||
for (i = 0; i < nr_of_irqs; ++i) {
|
for (i = 0; i < nr_of_irqs; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, &sable_lynx_irq_type,
|
set_irq_chip_and_handler(i, &sable_lynx_irq_type,
|
||||||
alpha_do_IRQ);
|
handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
common_init_isa_dma();
|
common_init_isa_dma();
|
||||||
|
|
|
@ -60,28 +60,11 @@ takara_disable_irq(unsigned int irq)
|
||||||
takara_update_irq_hw(irq, mask);
|
takara_update_irq_hw(irq, mask);
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
takara_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
takara_enable_irq(irq);
|
|
||||||
return 0; /* never anything pending */
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
takara_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
takara_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct irq_chip takara_irq_type = {
|
static struct irq_chip takara_irq_type = {
|
||||||
.name = "TAKARA",
|
.name = "TAKARA",
|
||||||
.startup = takara_startup_irq,
|
.unmask = takara_enable_irq,
|
||||||
.shutdown = takara_disable_irq,
|
.mask = takara_disable_irq,
|
||||||
.enable = takara_enable_irq,
|
.mask_ack = takara_disable_irq,
|
||||||
.disable = takara_disable_irq,
|
|
||||||
.ack = takara_disable_irq,
|
|
||||||
.end = takara_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
@ -154,7 +137,7 @@ takara_init_irq(void)
|
||||||
|
|
||||||
for (i = 16; i < 128; ++i) {
|
for (i = 16; i < 128; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, &takara_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
common_init_isa_dma();
|
common_init_isa_dma();
|
||||||
|
|
|
@ -129,20 +129,6 @@ titan_disable_irq(unsigned int irq)
|
||||||
spin_unlock(&titan_irq_lock);
|
spin_unlock(&titan_irq_lock);
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
titan_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
titan_enable_irq(irq);
|
|
||||||
return 0; /* never anything pending */
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
titan_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
titan_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
static void
|
||||||
titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
|
titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
|
||||||
{
|
{
|
||||||
|
@ -190,19 +176,16 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
|
||||||
long i;
|
long i;
|
||||||
for (i = imin; i <= imax; ++i) {
|
for (i = imin; i <= imax; ++i) {
|
||||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i, ops, alpha_do_IRQ);
|
set_irq_chip_and_handler(i, ops, handle_level_irq);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_chip titan_irq_type = {
|
static struct irq_chip titan_irq_type = {
|
||||||
.name = "TITAN",
|
.name = "TITAN",
|
||||||
.startup = titan_startup_irq,
|
.unmask = titan_enable_irq,
|
||||||
.shutdown = titan_disable_irq,
|
.mask = titan_disable_irq,
|
||||||
.enable = titan_enable_irq,
|
.mask_ack = titan_disable_irq,
|
||||||
.disable = titan_disable_irq,
|
.set_affinity = titan_set_irq_affinity,
|
||||||
.ack = titan_disable_irq,
|
|
||||||
.end = titan_end_irq,
|
|
||||||
.set_affinity = titan_set_irq_affinity,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static irqreturn_t
|
static irqreturn_t
|
||||||
|
|
|
@ -139,32 +139,11 @@ wildfire_mask_and_ack_irq(unsigned int irq)
|
||||||
spin_unlock(&wildfire_irq_lock);
|
spin_unlock(&wildfire_irq_lock);
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int
|
|
||||||
wildfire_startup_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
wildfire_enable_irq(irq);
|
|
||||||
return 0; /* never anything pending */
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
wildfire_end_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
#if 0
|
|
||||||
if (!irq_has_action(irq))
|
|
||||||
printk("got irq %d\n", irq);
|
|
||||||
#endif
|
|
||||||
if (!(irq_to_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
||||||
wildfire_enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct irq_chip wildfire_irq_type = {
|
static struct irq_chip wildfire_irq_type = {
|
||||||
.name = "WILDFIRE",
|
.name = "WILDFIRE",
|
||||||
.startup = wildfire_startup_irq,
|
.unmask = wildfire_enable_irq,
|
||||||
.shutdown = wildfire_disable_irq,
|
.mask = wildfire_disable_irq,
|
||||||
.enable = wildfire_enable_irq,
|
.mask_ack = wildfire_mask_and_ack_irq,
|
||||||
.disable = wildfire_disable_irq,
|
|
||||||
.ack = wildfire_mask_and_ack_irq,
|
|
||||||
.end = wildfire_end_irq,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static void __init
|
static void __init
|
||||||
|
@ -200,15 +179,16 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
|
||||||
continue;
|
continue;
|
||||||
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
|
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
||||||
alpha_do_IRQ);
|
handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL;
|
irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type, alpha_do_IRQ);
|
set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
|
||||||
|
handle_level_irq);
|
||||||
for (i = 40; i < 64; ++i) {
|
for (i = 40; i < 64; ++i) {
|
||||||
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
|
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
|
||||||
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
||||||
alpha_do_IRQ);
|
handle_level_irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
setup_irq(32+irq_bias, &isa_enable);
|
setup_irq(32+irq_bias, &isa_enable);
|
||||||
|
|
Loading…
Reference in New Issue