drm/i915: remove dev_priv->pc8.enabled
It was just being used on debugfs and on a WARN inside hsw_set_power_well. But now that we PC8 is part of runtime PM and we get/put runtime PM when we get/put any power domain, we shouldn't need the WARN anymore. v2: - Rebase. v3: - Rebase. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -2016,7 +2016,6 @@ static int i915_pc8_status(struct seq_file *m, void *unused)
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seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
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seq_printf(m, "IRQs disabled: %s\n",
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yesno(dev_priv->pc8.irqs_disabled));
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seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
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mutex_unlock(&dev_priv->pc8.lock);
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return 0;
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@ -1391,8 +1391,6 @@ struct ilk_wm_values {
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*/
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struct i915_package_c8 {
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bool irqs_disabled;
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/* Only true after the delayed work task actually enables it. */
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bool enabled;
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struct mutex lock;
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struct {
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@ -7033,8 +7033,6 @@ void __hsw_do_enable_pc8(struct drm_i915_private *dev_priv)
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DRM_DEBUG_KMS("Enabling package C8+\n");
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dev_priv->pc8.enabled = true;
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if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
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val = I915_READ(SOUTH_DSPCLK_GATE_D);
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val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
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@ -7070,7 +7068,6 @@ void __hsw_do_disable_pc8(struct drm_i915_private *dev_priv)
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mutex_lock(&dev_priv->rps.hw_lock);
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gen6_update_ring_freq(dev);
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mutex_unlock(&dev_priv->rps.hw_lock);
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dev_priv->pc8.enabled = false;
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}
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static void haswell_modeset_global_resources(struct drm_device *dev)
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@ -5345,8 +5345,6 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
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bool is_enabled, enable_requested;
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uint32_t tmp;
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WARN_ON(dev_priv->pc8.enabled);
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tmp = I915_READ(HSW_PWR_WELL_DRIVER);
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is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
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enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
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@ -6161,7 +6159,6 @@ void intel_pm_setup(struct drm_device *dev)
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mutex_init(&dev_priv->pc8.lock);
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dev_priv->pc8.irqs_disabled = false;
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dev_priv->pc8.enabled = false;
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INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
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intel_gen6_powersave_work);
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}
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