arm64: dts: renesas: r8a77995: sort subnodes of the soc node
Sort subnodes of the soc node. - The primary key is the bus address. - The secondary key is the IP block. - The tertiary key is the node name. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Yoshihiro Kaneko
Simon Horman
parent
21559e2b04
commit
7c55747fbe
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@ -76,23 +76,6 @@
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x20000>,
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<0x0 0xf1040000 0 0x20000>,
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<0x0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 408>;
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};
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a77995-wdt",
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"renesas,rcar-gen3-wdt";
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@ -103,207 +86,6 @@
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status = "disabled";
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};
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ipmmu_vi0: mmu@febd0000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xfebd0000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 14>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_vp0: mmu@fe990000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xfe990000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 16>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_vc0: mmu@fe6b0000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xfe6b0000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 12>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_pv0: mmu@fd800000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xfd800000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 6>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_hc: mmu@e6570000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xe6570000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 2>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_rt: mmu@ffc80000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xffc80000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 10>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_mp: mmu@ec670000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xec670000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 4>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_ds0: mmu@e6740000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xe6740000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 0>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_ds1: mmu@e7740000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xe7740000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 1>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_mm: mmu@e67b0000 {
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compatible = "renesas,ipmmu-r8a77995";
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reg = <0 0xe67b0000 0 0x1000>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77995-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77995-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a77995";
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reg = <0 0xe6060000 0 0x508>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77995-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 407>;
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a77995",
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"renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x10000>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7";
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clocks = <&cpg CPG_MOD 219>;
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clock-names = "fck";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 219>;
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#dma-cells = <1>;
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dma-channels = <8>;
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};
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dmac1: dma-controller@e7300000 {
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compatible = "renesas,dmac-r8a77995",
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"renesas,rcar-dmac";
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reg = <0 0xe7300000 0 0x10000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7";
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clocks = <&cpg CPG_MOD 218>;
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clock-names = "fck";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 218>;
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#dma-cells = <1>;
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dma-channels = <8>;
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};
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dmac2: dma-controller@e7310000 {
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compatible = "renesas,dmac-r8a77995",
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"renesas,rcar-dmac";
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reg = <0 0xe7310000 0 0x10000>;
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interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7";
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clocks = <&cpg CPG_MOD 217>;
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clock-names = "fck";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 217>;
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#dma-cells = <1>;
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dma-channels = <8>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio",
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@ -416,124 +198,46 @@
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resets = <&cpg 906>;
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};
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can0: can@e6c30000 {
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compatible = "renesas,can-r8a77995",
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"renesas,rcar-gen3-can";
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reg = <0 0xe6c30000 0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 916>,
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<&cpg CPG_CORE R8A77995_CLK_CANFD>,
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<&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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status = "disabled";
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a77995";
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reg = <0 0xe6060000 0 0x508>;
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};
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can1: can@e6c38000 {
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compatible = "renesas,can-r8a77995",
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"renesas,rcar-gen3-can";
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reg = <0 0xe6c38000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 915>,
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<&cpg CPG_CORE R8A77995_CLK_CANFD>,
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<&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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status = "disabled";
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77995-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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canfd: can@e66c0000 {
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compatible = "renesas,r8a77995-canfd",
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"renesas,rcar-gen3-canfd";
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reg = <0 0xe66c0000 0 0x8000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 914>,
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<&cpg CPG_CORE R8A77995_CLK_CANFD>,
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<&can_clk>;
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clock-names = "fck", "canfd", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 914>;
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status = "disabled";
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channel0 {
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status = "disabled";
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};
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channel1 {
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status = "disabled";
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77995-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a77995",
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"renesas,etheravb-rcar-gen3";
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reg = <0 0xe6800000 0 0x800>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15",
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"ch16", "ch17", "ch18", "ch19",
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"ch20", "ch21", "ch22", "ch23",
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"ch24";
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 812>;
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phy-mode = "rgmii";
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iommus = <&ipmmu_ds0 16>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77995-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a77995",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>,
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<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x13>, <&dmac1 0x12>,
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<&dmac2 0x13>, <&dmac2 0x12>;
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dma-names = "tx", "rx", "tx", "rx";
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 310>;
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status = "disabled";
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resets = <&cpg 407>;
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};
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i2c0: i2c@e6500000 {
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@ -603,6 +307,262 @@
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status = "disabled";
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};
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canfd: can@e66c0000 {
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compatible = "renesas,r8a77995-canfd",
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"renesas,rcar-gen3-canfd";
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reg = <0 0xe66c0000 0 0x8000>;
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||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "fck", "canfd", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
status = "disabled";
|
||||
|
||||
channel0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7300000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7310000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_vp0: mmu@fe990000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe990000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a77995",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can0: can@e6c30000 {
|
||||
compatible = "renesas,can-r8a77995",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c30000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6c38000 {
|
||||
compatible = "renesas,can-r8a77995",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c38000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@e6e30000 {
|
||||
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e30000 0 0x8>;
|
||||
|
|
@ -643,15 +603,32 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a77995",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
max-frequency = <200000000>;
|
||||
scif2: serial@e6e88000 {
|
||||
compatible = "renesas,scif-r8a77995",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6e88000 0 64>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 310>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
|
||||
<&dmac2 0x13>, <&dmac2 0x12>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -668,18 +645,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy0: usb-phy@ee080200 {
|
||||
compatible = "renesas,usb2-phy-r8a77995",
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
|
|
@ -692,6 +657,35 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a77995",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xf1010000 0 0x1000>,
|
||||
<0x0 0xf1020000 0 0x20000>,
|
||||
<0x0 0xf1040000 0 0x20000>,
|
||||
<0x0 0xf1060000 0 0x20000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
vspbs: vsp@fe960000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe960000 0 0x8000>;
|
||||
|
|
@ -702,15 +696,6 @@
|
|||
renesas,fcp = <&fcpvb0>;
|
||||
};
|
||||
|
||||
fcpvb0: fcp@fe96f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfe96f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 607>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 607>;
|
||||
iommus = <&ipmmu_vp0 5>;
|
||||
};
|
||||
|
||||
vspd0: vsp@fea20000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea20000 0 0x8000>;
|
||||
|
|
@ -721,15 +706,6 @@
|
|||
renesas,fcp = <&fcpvd0>;
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea27000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea27000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
iommus = <&ipmmu_vi0 8>;
|
||||
};
|
||||
|
||||
vspd1: vsp@fea28000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea28000 0 0x8000>;
|
||||
|
|
@ -740,6 +716,24 @@
|
|||
renesas,fcp = <&fcpvd1>;
|
||||
};
|
||||
|
||||
fcpvb0: fcp@fe96f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfe96f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 607>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 607>;
|
||||
iommus = <&ipmmu_vp0 5>;
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea27000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea27000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
iommus = <&ipmmu_vi0 8>;
|
||||
};
|
||||
|
||||
fcpvd1: fcp@fea2f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea2f000 0 0x200>;
|
||||
|
|
@ -783,6 +777,11 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
Loading…
Reference in New Issue