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MIPS: Generic: Support GIC in EIC mode 

The GIC supports running in External Interrupt Controller (EIC) mode,
and will signal this via cpu_has_veic if enabled in hardware. Currently
the generic kernel will panic if cpu_has_veic is set - but the GIC can
legitimately set this flag if either configured to boot in EIC mode, or
if the GIC driver enables this mode. Make the kernel not panic in this
case, and instead just check if the GIC is present. If so, use it's CPU
local interrupt routing functions. If an EIC is present, but it is not
the GIC, then the kernel does not know how to get the VIRQ for the CPU
local interrupts and should panic. Support for alternative EICs being
present is needed here for the generic kernel to support them.

Suggested-by: Paul Burton <paul.burton@mips.com>
Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18191/
Signed-off-by: James Hogan <jhogan@kernel.org>
This commit is contained in:
Matt Redfearn 2018-01-05 10:31:07 +00:00 committed by James Hogan
parent 0ef1559a20
commit 7bf8b16d1b
No known key found for this signature in database
GPG Key ID: 6C0B6993DE38767A
1 changed files with 9 additions and 9 deletions
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18
arch/mips/generic/irq.c
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@ -22,10 +22,10 @@ int get_c0_fdc_int(void)
{ {
int mips_cpu_fdc_irq; int mips_cpu_fdc_irq;
if (cpu_has_veic) if (mips_gic_present())
panic("Unimplemented!");
else if (mips_gic_present())
mips_cpu_fdc_irq = gic_get_c0_fdc_int(); mips_cpu_fdc_irq = gic_get_c0_fdc_int();
else if (cpu_has_veic)
panic("Unimplemented!");
else if (cp0_fdc_irq >= 0) else if (cp0_fdc_irq >= 0)
mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq; mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
else else
@ -38,10 +38,10 @@ int get_c0_perfcount_int(void)
{ {
int mips_cpu_perf_irq; int mips_cpu_perf_irq;
if (cpu_has_veic) if (mips_gic_present())
panic("Unimplemented!");
else if (mips_gic_present())
mips_cpu_perf_irq = gic_get_c0_perfcount_int(); mips_cpu_perf_irq = gic_get_c0_perfcount_int();
else if (cpu_has_veic)
panic("Unimplemented!");
else if (cp0_perfcount_irq >= 0) else if (cp0_perfcount_irq >= 0)
mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
else else
@ -54,10 +54,10 @@ unsigned int get_c0_compare_int(void)
{ {
int mips_cpu_timer_irq; int mips_cpu_timer_irq;
if (cpu_has_veic) if (mips_gic_present())
panic("Unimplemented!");
else if (mips_gic_present())
mips_cpu_timer_irq = gic_get_c0_compare_int(); mips_cpu_timer_irq = gic_get_c0_compare_int();
else if (cpu_has_veic)
panic("Unimplemented!");
else else
mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;