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clk: tegra: Add fields for override bits 

PLLM can have override bits in the PMC. Describe those in the PLL parameters.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Peter De Schrijver 2013-06-06 13:47:28 +03:00 committed by Mike Turquette
parent 29b09447b6
commit 7b781c72c9
1 changed files with 8 additions and 0 deletions
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8
drivers/clk/tegra/clk.h
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@ -136,6 +136,9 @@ struct pdiv_map {
* @divm_width: width of the input divider bit field
* @divp_shift: shift to the post divider bit field
* @divp_width: width of the post divider bit field
* @override_divn_shift: shift to the feedback divider bitfield in override reg
* @override_divm_shift: shift to the input divider bitfield in override reg
* @override_divp_shift: shift to the post divider bitfield in override reg
*/
struct div_nmp {
u8 divn_shift;
@ -144,6 +147,9 @@ struct div_nmp {
u8 divm_width;
u8 divp_shift;
u8 divp_width;
u8 override_divn_shift;
u8 override_divm_shift;
u8 override_divp_shift;
};
/**
@ -180,6 +186,8 @@ struct tegra_clk_pll_params {
u32 aux_reg;
u32 dyn_ramp_reg;
u32 ext_misc_reg[3];
u32 pmc_divnm_reg;
u32 pmc_divp_reg;
int stepa_shift;
int stepb_shift;
int lock_delay;