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qed: Utilize FW 8.20.0.0 

This pushes qed [and as result, all qed* drivers] into using 8.20.0.0
firmware. The changes are mostly contained in qed with minor changes
to qedi due to some HSI changes.

Content-wise, the firmware contains fixes to various issues exposed
since the release of the previous firmware, including:
 - Corrects iSCSI fast retransmit when data digest is enabled.
 - Stop draining packets when receiving several consecutive PFCs.
 - Prevent possible assertion when consecutively opening/closing
   many connections.
 - Prevent possible assertion due to too long BDQ fetch time.

In addition, the new firmware would allow us to later add iWARP support
in qed and qedr.

Changes from previous version
-----------------------------
 - V2: Fix warning in qed_debug.c

Signed-off-by: Chad Dupuis <Chad.Dupuis@cavium.com>
Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com>
Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: Manish Rangankar <Manish.Rangankar@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Mintz, Yuval 2017-05-18 19:41:04 +03:00 committed by David S. Miller
parent b17b8a20c5
commit 7b6859fbdc
20 changed files with 4800 additions and 3027 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/qlogic/qed/qed.h
View File

@ -54,7 +54,7 @@ extern const struct qed_common_ops qed_common_ops_pass;
#define QED_MAJOR_VERSION 8
#define QED_MINOR_VERSION 10
#define QED_REVISION_VERSION 10
#define QED_REVISION_VERSION 11
#define QED_ENGINEERING_VERSION 21
#define QED_VERSION \

11
drivers/net/ethernet/qlogic/qed/qed_dcbx.c
View File

@ -944,17 +944,18 @@ void qed_dcbx_set_pf_update_params(struct qed_dcbx_results *p_src,
p_dest->pf_id = p_src->pf_id;
update_flag = p_src->arr[DCBX_PROTOCOL_FCOE].update;
p_dest->update_fcoe_dcb_data_flag = update_flag;
p_dest->update_fcoe_dcb_data_mode = update_flag;
update_flag = p_src->arr[DCBX_PROTOCOL_ROCE].update;
p_dest->update_roce_dcb_data_flag = update_flag;
p_dest->update_roce_dcb_data_mode = update_flag;
update_flag = p_src->arr[DCBX_PROTOCOL_ROCE_V2].update;
p_dest->update_roce_dcb_data_flag = update_flag;
p_dest->update_rroce_dcb_data_mode = update_flag;
update_flag = p_src->arr[DCBX_PROTOCOL_ISCSI].update;
p_dest->update_iscsi_dcb_data_flag = update_flag;
p_dest->update_iscsi_dcb_data_mode = update_flag;
update_flag = p_src->arr[DCBX_PROTOCOL_ETH].update;
p_dest->update_eth_dcb_data_flag = update_flag;
p_dest->update_eth_dcb_data_mode = update_flag;
p_dcb_data = &p_dest->fcoe_dcb_data;
qed_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_FCOE);

3464
drivers/net/ethernet/qlogic/qed/qed_debug.c
View File

File diff suppressed because it is too large Load Diff

3
drivers/net/ethernet/qlogic/qed/qed_debug.h
View File

@ -20,6 +20,9 @@ enum qed_dbg_features {
DBG_FEATURE_NUM
};
/* Forward Declaration */
struct qed_dev;
int qed_dbg_grc(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes);
int qed_dbg_grc_size(struct qed_dev *cdev);
int qed_dbg_idle_chk(struct qed_dev *cdev, void *buffer,

3529
drivers/net/ethernet/qlogic/qed/qed_hsi.h
View File

File diff suppressed because it is too large Load Diff

263
drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
View File

@ -40,31 +40,17 @@
#include "qed_init_ops.h"
#include "qed_reg_addr.h"
enum cminterface {
MCM_SEC,
MCM_PRI,
UCM_SEC,
UCM_PRI,
TCM_SEC,
TCM_PRI,
YCM_SEC,
YCM_PRI,
XCM_SEC,
XCM_PRI,
NUM_OF_CM_INTERFACES
};
/* general constants */
/* General constants */
#define QM_PQ_MEM_4KB(pq_size) (pq_size ? DIV_ROUND_UP((pq_size + 1) * \
QM_PQ_ELEMENT_SIZE, \
0x1000) : 0)
#define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, \
0x100) - 1 : 0)
#define QM_INVALID_PQ_ID 0xffff
/* feature enable */
/* Feature enable */
#define QM_BYPASS_EN 1
#define QM_BYTE_CRD_EN 1
/* other PQ constants */
/* Other PQ constants */
#define QM_OTHER_PQS_PER_PF 4
/* WFQ constants */
#define QM_WFQ_UPPER_BOUND 62500000
@ -106,20 +92,21 @@ enum cminterface {
#define BTB_PURE_LB_FACTOR 10
#define BTB_PURE_LB_RATIO 7
/* QM stop command constants */
#define QM_STOP_PQ_MASK_WIDTH 32
#define QM_STOP_CMD_ADDR 0x2
#define QM_STOP_CMD_STRUCT_SIZE 2
#define QM_STOP_PQ_MASK_WIDTH 32
#define QM_STOP_CMD_ADDR 2
#define QM_STOP_CMD_STRUCT_SIZE 2
#define QM_STOP_CMD_PAUSE_MASK_OFFSET 0
#define QM_STOP_CMD_PAUSE_MASK_SHIFT 0
#define QM_STOP_CMD_PAUSE_MASK_MASK -1
#define QM_STOP_CMD_GROUP_ID_OFFSET 1
#define QM_STOP_CMD_GROUP_ID_SHIFT 16
#define QM_STOP_CMD_GROUP_ID_MASK 15
#define QM_STOP_CMD_PQ_TYPE_OFFSET 1
#define QM_STOP_CMD_PQ_TYPE_SHIFT 24
#define QM_STOP_CMD_PQ_TYPE_MASK 1
#define QM_STOP_CMD_MAX_POLL_COUNT 100
#define QM_STOP_CMD_POLL_PERIOD_US 500
#define QM_STOP_CMD_PAUSE_MASK_MASK -1
#define QM_STOP_CMD_GROUP_ID_OFFSET 1
#define QM_STOP_CMD_GROUP_ID_SHIFT 16
#define QM_STOP_CMD_GROUP_ID_MASK 15
#define QM_STOP_CMD_PQ_TYPE_OFFSET 1
#define QM_STOP_CMD_PQ_TYPE_SHIFT 24
#define QM_STOP_CMD_PQ_TYPE_MASK 1
#define QM_STOP_CMD_MAX_POLL_COUNT 100
#define QM_STOP_CMD_POLL_PERIOD_US 500
/* QM command macros */
#define QM_CMD_STRUCT_SIZE(cmd) cmd ## \
_STRUCT_SIZE
@ -146,16 +133,17 @@ static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
{
STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
if (pf_rl_en) {
/* enable RLs for all VOQs */
/* Enable RLs for all VOQs */
STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET,
(1 << MAX_NUM_VOQS) - 1);
/* write RL period */
/* Write RL period */
STORE_RT_REG(p_hwfn,
QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
STORE_RT_REG(p_hwfn,
QM_REG_RLPFPERIODTIMER_RT_OFFSET,
QM_RL_PERIOD_CLK_25M);
/* set credit threshold for QM bypass flow */
/* Set credit threshold for QM bypass flow */
if (QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET,
@ -167,7 +155,8 @@ static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
static void qed_enable_pf_wfq(struct qed_hwfn *p_hwfn, bool pf_wfq_en)
{
STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0);
/* set credit threshold for QM bypass flow */
/* Set credit threshold for QM bypass flow */
if (pf_wfq_en && QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET,
@ -180,14 +169,15 @@ static void qed_enable_vport_rl(struct qed_hwfn *p_hwfn, bool vport_rl_en)
STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET,
vport_rl_en ? 1 : 0);
if (vport_rl_en) {
/* write RL period (use timer 0 only) */
/* Write RL period (use timer 0 only) */
STORE_RT_REG(p_hwfn,
QM_REG_RLGLBLPERIOD_0_RT_OFFSET,
QM_RL_PERIOD_CLK_25M);
STORE_RT_REG(p_hwfn,
QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET,
QM_RL_PERIOD_CLK_25M);
/* set credit threshold for QM bypass flow */
/* Set credit threshold for QM bypass flow */
if (QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET,
@ -200,7 +190,8 @@ static void qed_enable_vport_wfq(struct qed_hwfn *p_hwfn, bool vport_wfq_en)
{
STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET,
vport_wfq_en ? 1 : 0);
/* set credit threshold for QM bypass flow */
/* Set credit threshold for QM bypass flow */
if (vport_wfq_en && QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET,
@ -208,7 +199,7 @@ static void qed_enable_vport_wfq(struct qed_hwfn *p_hwfn, bool vport_wfq_en)
}
/* Prepare runtime init values to allocate PBF command queue lines for
* the specified VOQ
* the specified VOQ.
*/
static void qed_cmdq_lines_voq_rt_init(struct qed_hwfn *p_hwfn,
u8 voq, u16 cmdq_lines)
@ -232,7 +223,7 @@ static void qed_cmdq_lines_rt_init(
{
u8 tc, voq, port_id, num_tcs_in_port;
/* clear PBF lines for all VOQs */
/* Clear PBF lines for all VOQs */
for (voq = 0; voq < MAX_NUM_VOQS; voq++)
STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0);
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
@ -285,7 +276,7 @@ static void qed_btb_blocks_rt_init(
if (!port_params[port_id].active)
continue;
/* subtract headroom blocks */
/* Subtract headroom blocks */
usable_blocks = port_params[port_id].num_btb_blocks -
BTB_HEADROOM_BLOCKS;
@ -305,7 +296,7 @@ static void qed_btb_blocks_rt_init(
phys_blocks = (usable_blocks - pure_lb_blocks) /
num_tcs_in_port;
/* init physical TCs */
/* Init physical TCs */
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
if (((port_params[port_id].active_phys_tcs >>
tc) & 0x1) != 1)
@ -317,7 +308,7 @@ static void qed_btb_blocks_rt_init(
phys_blocks);
}
/* init pure LB TC */
/* Init pure LB TC */
temp = LB_VOQ(port_id);
STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(temp),
pure_lb_blocks);
@ -338,24 +329,24 @@ static void qed_tx_pq_map_rt_init(
QM_PF_QUEUE_GROUP_SIZE;
u16 i, pq_id, pq_group;
/* a bit per Tx PQ indicating if the PQ is associated with a VF */
/* A bit per Tx PQ indicating if the PQ is associated with a VF */
u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE;
u32 pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids);
u32 vport_pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_vf_cids);
u32 mem_addr_4kb = base_mem_addr_4kb;
/* set mapping from PQ group to PF */
/* Set mapping from PQ group to PF */
for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++)
STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group,
(u32)(p_params->pf_id));
/* set PQ sizes */
/* Set PQ sizes */
STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET,
QM_PQ_SIZE_256B(p_params->num_pf_cids));
STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET,
QM_PQ_SIZE_256B(p_params->num_vf_cids));
/* go over all Tx PQs */
/* Go over all Tx PQs */
for (i = 0, pq_id = p_params->start_pq; i < num_pqs; i++, pq_id++) {
u8 voq = VOQ(p_params->port_id, p_params->pq_params[i].tc_id,
p_params->max_phys_tcs_per_port);
@ -366,17 +357,18 @@ static void qed_tx_pq_map_rt_init(
(p_params->pq_params[i].vport_id <
MAX_QM_GLOBAL_RLS);
/* update first Tx PQ of VPORT/TC */
/* Update first Tx PQ of VPORT/TC */
u8 vport_id_in_pf = p_params->pq_params[i].vport_id -
p_params->start_vport;
u16 *pq_ids = &vport_params[vport_id_in_pf].first_tx_pq_id[0];
u16 first_tx_pq_id = pq_ids[p_params->pq_params[i].tc_id];
if (first_tx_pq_id == QM_INVALID_PQ_ID) {
/* create new VP PQ */
/* Create new VP PQ */
pq_ids[p_params->pq_params[i].tc_id] = pq_id;
first_tx_pq_id = pq_id;
/* map VP PQ to VOQ and PF */
/* Map VP PQ to VOQ and PF */
STORE_RT_REG(p_hwfn,
QM_REG_WFQVPMAP_RT_OFFSET +
first_tx_pq_id,
@ -388,7 +380,7 @@ static void qed_tx_pq_map_rt_init(
if (p_params->pq_params[i].rl_valid && !rl_valid)
DP_NOTICE(p_hwfn,
"Invalid VPORT ID for rate limiter configuration");
/* fill PQ map entry */
/* Fill PQ map entry */
memset(&tx_pq_map, 0, sizeof(tx_pq_map));
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1);
SET_FIELD(tx_pq_map.reg,
@ -400,18 +392,16 @@ static void qed_tx_pq_map_rt_init(
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP,
p_params->pq_params[i].wrr_group);
/* write PQ map entry to CAM */
/* Write PQ map entry to CAM */
STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id,
*((u32 *)&tx_pq_map));
/* set base address */
/* Set base address */
STORE_RT_REG(p_hwfn,
QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id,
mem_addr_4kb);
/* check if VF PQ */
/* If VF PQ, add indication to PQ VF mask */
if (is_vf_pq) {
/* if PQ is associated with a VF, add indication
* to PQ VF mask
*/
tx_pq_vf_mask[pq_id /
QM_PF_QUEUE_GROUP_SIZE] |=
BIT((pq_id % QM_PF_QUEUE_GROUP_SIZE));
@ -421,16 +411,12 @@ static void qed_tx_pq_map_rt_init(
}
}
/* store Tx PQ VF mask to size select register */
for (i = 0; i < num_tx_pq_vf_masks; i++) {
if (tx_pq_vf_mask[i]) {
u32 addr;
addr = QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i;
STORE_RT_REG(p_hwfn, addr,
/* Store Tx PQ VF mask to size select register */
for (i = 0; i < num_tx_pq_vf_masks; i++)
if (tx_pq_vf_mask[i])
STORE_RT_REG(p_hwfn,
QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i,
tx_pq_vf_mask[i]);
}
}
}
/* Prepare Other PQ mapping runtime init values for the specified PF */
@ -440,23 +426,25 @@ static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn,
u32 num_pf_cids,
u32 num_tids, u32 base_mem_addr_4kb)
{
u16 i, pq_id;
u32 pq_size, pq_mem_4kb, mem_addr_4kb;
u16 i, pq_id, pq_group;
/* a single other PQ group is used in each PF,
* where PQ group i is used in PF i.
*/
u16 pq_group = pf_id;
u32 pq_size = num_pf_cids + num_tids;
u32 pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
u32 mem_addr_4kb = base_mem_addr_4kb;
pq_group = pf_id;
pq_size = num_pf_cids + num_tids;
pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
mem_addr_4kb = base_mem_addr_4kb;
/* map PQ group to PF */
/* Map PQ group to PF */
STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group,
(u32)(pf_id));
/* set PQ sizes */
/* Set PQ sizes */
STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET,
QM_PQ_SIZE_256B(pq_size));
/* set base address */
/* Set base address */
for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE;
i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
STORE_RT_REG(p_hwfn,
@ -485,7 +473,7 @@ static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn,
inc_val = QM_WFQ_INC_VAL(p_params->pf_wfq);
if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration");
DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
return -1;
}
@ -514,7 +502,7 @@ static int qed_pf_rl_rt_init(struct qed_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
u32 inc_val = QM_RL_INC_VAL(pf_rl);
if (inc_val > QM_RL_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration");
DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
return -1;
}
STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id,
@ -535,7 +523,7 @@ static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn,
u32 inc_val;
u8 tc, i;
/* go over all PF VPORTs */
/* Go over all PF VPORTs */
for (i = 0; i < num_vports; i++) {
if (!vport_params[i].vport_wfq)
@ -544,7 +532,7 @@ static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn,
inc_val = QM_WFQ_INC_VAL(vport_params[i].vport_wfq);
if (inc_val > QM_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn,
"Invalid VPORT WFQ weight configuration");
"Invalid VPORT WFQ weight configuration\n");
return -1;
}
@ -578,17 +566,17 @@ static int qed_vport_rl_rt_init(struct qed_hwfn *p_hwfn,
if (start_vport + num_vports >= MAX_QM_GLOBAL_RLS) {
DP_NOTICE(p_hwfn,
"Invalid VPORT ID for rate limiter configuration");
"Invalid VPORT ID for rate limiter configuration\n");
return -1;
}
/* go over all PF VPORTs */
/* Go over all PF VPORTs */
for (i = 0, vport_id = start_vport; i < num_vports; i++, vport_id++) {
u32 inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl);
if (inc_val > QM_RL_MAX_INC_VAL) {
DP_NOTICE(p_hwfn,
"Invalid VPORT rate-limit configuration");
"Invalid VPORT rate-limit configuration\n");
return -1;
}
@ -617,7 +605,7 @@ static bool qed_poll_on_qm_cmd_ready(struct qed_hwfn *p_hwfn,
reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
}
/* check if timeout while waiting for SDM command ready */
/* Check if timeout while waiting for SDM command ready */
if (i == QM_STOP_CMD_MAX_POLL_COUNT) {
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"Timeout when waiting for QM SDM command ready signal\n");
@ -701,16 +689,16 @@ int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
QM_OTHER_PQS_PER_PF;
u8 tc, i;
/* clear first Tx PQ ID array for each VPORT */
/* Clear first Tx PQ ID array for each VPORT */
for (i = 0; i < p_params->num_vports; i++)
for (tc = 0; tc < NUM_OF_TCS; tc++)
vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID;
/* map Other PQs (if any) */
/* Map Other PQs (if any) */
qed_other_pq_map_rt_init(p_hwfn, p_params->port_id, p_params->pf_id,
p_params->num_pf_cids, p_params->num_tids, 0);
/* map Tx PQs */
/* Map Tx PQs */
qed_tx_pq_map_rt_init(p_hwfn, p_ptt, p_params, other_mem_size_4kb);
if (p_params->pf_wfq)
@ -736,7 +724,7 @@ int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
u32 inc_val = QM_WFQ_INC_VAL(pf_wfq);
if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration");
DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
return -1;
}
@ -750,7 +738,7 @@ int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
u32 inc_val = QM_RL_INC_VAL(pf_rl);
if (inc_val > QM_RL_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration");
DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
return -1;
}
@ -766,17 +754,18 @@ int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq)
{
u32 inc_val = QM_WFQ_INC_VAL(vport_wfq);
u16 vport_pq_id;
u32 inc_val;
u8 tc;
inc_val = QM_WFQ_INC_VAL(vport_wfq);
if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid VPORT WFQ weight configuration");
DP_NOTICE(p_hwfn, "Invalid VPORT WFQ weight configuration\n");
return -1;
}
for (tc = 0; tc < NUM_OF_TCS; tc++) {
u16 vport_pq_id = first_tx_pq_id[tc];
vport_pq_id = first_tx_pq_id[tc];
if (vport_pq_id != QM_INVALID_PQ_ID)
qed_wr(p_hwfn, p_ptt,
QM_REG_WFQVPWEIGHT + vport_pq_id * 4,
@ -793,12 +782,12 @@ int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
if (vport_id >= MAX_QM_GLOBAL_RLS) {
DP_NOTICE(p_hwfn,
"Invalid VPORT ID for rate limiter configuration");
"Invalid VPORT ID for rate limiter configuration\n");
return -1;
}
if (inc_val > QM_RL_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid VPORT rate-limit configuration");
DP_NOTICE(p_hwfn, "Invalid VPORT rate-limit configuration\n");
return -1;
}
@ -818,15 +807,15 @@ bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
u32 cmd_arr[QM_CMD_STRUCT_SIZE(QM_STOP_CMD)] = { 0 };
u32 pq_mask = 0, last_pq = start_pq + num_pqs - 1, pq_id;
/* set command's PQ type */
/* Set command's PQ type */
QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PQ_TYPE, is_tx_pq ? 0 : 1);
for (pq_id = start_pq; pq_id <= last_pq; pq_id++) {
/* set PQ bit in mask (stop command only) */
/* Set PQ bit in mask (stop command only) */
if (!is_release_cmd)
pq_mask |= (1 << (pq_id % QM_STOP_PQ_MASK_WIDTH));
/* if last PQ or end of PQ mask, write command */
/* If last PQ or end of PQ mask, write command */
if ((pq_id == last_pq) ||
(pq_id % QM_STOP_PQ_MASK_WIDTH ==
(QM_STOP_PQ_MASK_WIDTH - 1))) {
@ -962,8 +951,10 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
ip_geneve_enable ? 1 : 0);
}
#define T_ETH_PACKET_ACTION_GFT_EVENTID 23
#define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272
#define T_ETH_PACKET_MATCH_RFS_EVENTID 25
#define PARSER_ETH_CONN_CM_HDR (0x0)
#define PARSER_ETH_CONN_CM_HDR 0
#define CAM_LINE_SIZE sizeof(u32)
#define RAM_LINE_SIZE sizeof(u64)
#define REG_SIZE sizeof(u32)
@ -971,40 +962,26 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
void qed_set_rfs_mode_disable(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u16 pf_id)
{
union gft_cam_line_union camline;
struct gft_ram_line ramline;
u32 *p_ramline, i;
p_ramline = (u32 *)&ramline;
u32 hw_addr = PRS_REG_GFT_PROFILE_MASK_RAM +
pf_id * RAM_LINE_SIZE;
/*stop using gft logic */
qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0);
qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, 0x0);
memset(&camline, 0, sizeof(union gft_cam_line_union));
qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
camline.cam_line_mapped.camline);
memset(&ramline, 0, sizeof(ramline));
for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++) {
u32 hw_addr = PRS_REG_GFT_PROFILE_MASK_RAM;
hw_addr += (RAM_LINE_SIZE * pf_id + i * REG_SIZE);
qed_wr(p_hwfn, p_ptt, hw_addr, *(p_ramline + i));
}
qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 0);
qed_wr(p_hwfn, p_ptt, hw_addr, 0);
qed_wr(p_hwfn, p_ptt, hw_addr + 4, 0);
}
void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u16 pf_id, bool tcp, bool udp,
bool ipv4, bool ipv6)
{
u32 rfs_cm_hdr_event_id, *p_ramline;
union gft_cam_line_union camline;
struct gft_ram_line ramline;
int i;
u32 rfs_cm_hdr_event_id;
rfs_cm_hdr_event_id = qed_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
p_ramline = (u32 *)&ramline;
if (!ipv6 && !ipv4)
DP_NOTICE(p_hwfn,
@ -1024,18 +1001,20 @@ void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
qed_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0);
camline.cam_line_mapped.camline = 0;
/* cam line is now valid!! */
/* Cam line is now valid!! */
SET_FIELD(camline.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_VALID, 1);
/* filters are per PF!! */
SET_FIELD(camline.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_PF_ID_MASK, 1);
GFT_CAM_LINE_MAPPED_PF_ID_MASK,
GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK);
SET_FIELD(camline.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
if (!(tcp && udp)) {
SET_FIELD(camline.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK, 1);
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK);
if (tcp)
SET_FIELD(camline.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
@ -1059,34 +1038,38 @@ void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
GFT_PROFILE_IPV6);
}
/* write characteristics to cam */
/* Write characteristics to cam */
qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
camline.cam_line_mapped.camline);
camline.cam_line_mapped.camline = qed_rd(p_hwfn, p_ptt,
PRS_REG_GFT_CAM +
CAM_LINE_SIZE * pf_id);
/* write line to RAM - compare to filter 4 tuple */
ramline.low32bits = 0;
ramline.high32bits = 0;
SET_FIELD(ramline.high32bits, GFT_RAM_LINE_DST_IP, 1);
SET_FIELD(ramline.high32bits, GFT_RAM_LINE_SRC_IP, 1);
SET_FIELD(ramline.low32bits, GFT_RAM_LINE_SRC_PORT, 1);
SET_FIELD(ramline.low32bits, GFT_RAM_LINE_DST_PORT, 1);
/* Write line to RAM - compare to filter 4 tuple */
ramline.lo = 0;
ramline.hi = 0;
SET_FIELD(ramline.hi, GFT_RAM_LINE_DST_IP, 1);
SET_FIELD(ramline.hi, GFT_RAM_LINE_SRC_IP, 1);
SET_FIELD(ramline.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
SET_FIELD(ramline.lo, GFT_RAM_LINE_ETHERTYPE, 1);
SET_FIELD(ramline.lo, GFT_RAM_LINE_SRC_PORT, 1);
SET_FIELD(ramline.lo, GFT_RAM_LINE_DST_PORT, 1);
/* each iteration write to reg */
for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
qed_wr(p_hwfn, p_ptt,
PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id +
i * REG_SIZE, *(p_ramline + i));
/* Each iteration write to reg */
qed_wr(p_hwfn, p_ptt,
PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
ramline.lo);
qed_wr(p_hwfn, p_ptt,
PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id + 4,
ramline.hi);
/* set default profile so that no filter match will happen */
ramline.low32bits = 0xffff;
ramline.high32bits = 0xffff;
for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
qed_wr(p_hwfn, p_ptt,
PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
PRS_GFT_CAM_LINES_NO_MATCH + i * REG_SIZE,
*(p_ramline + i));
/* Set default profile so that no filter match will happen */
qed_wr(p_hwfn, p_ptt,
PRS_REG_GFT_PROFILE_MASK_RAM +
RAM_LINE_SIZE * PRS_GFT_CAM_LINES_NO_MATCH,
ramline.lo);
qed_wr(p_hwfn, p_ptt,
PRS_REG_GFT_PROFILE_MASK_RAM +
RAM_LINE_SIZE * PRS_GFT_CAM_LINES_NO_MATCH + 4,
ramline.hi);
}

3
drivers/net/ethernet/qlogic/qed/qed_iscsi.c
View File

@ -375,7 +375,6 @@ static int qed_sp_iscsi_conn_offload(struct qed_hwfn *p_hwfn,
p_tcp->ss_thresh = cpu_to_le32(p_conn->ss_thresh);
p_tcp->srtt = cpu_to_le16(p_conn->srtt);
p_tcp->rtt_var = cpu_to_le16(p_conn->rtt_var);
p_tcp->ts_time = cpu_to_le32(p_conn->ts_time);
p_tcp->ts_recent = cpu_to_le32(p_conn->ts_recent);
p_tcp->ts_recent_age = cpu_to_le32(p_conn->ts_recent_age);
p_tcp->total_rt = cpu_to_le32(p_conn->total_rt);
@ -400,8 +399,6 @@ static int qed_sp_iscsi_conn_offload(struct qed_hwfn *p_hwfn,
p_tcp->mss = cpu_to_le16(p_conn->mss);
p_tcp->snd_wnd_scale = p_conn->snd_wnd_scale;
p_tcp->rcv_wnd_scale = p_conn->rcv_wnd_scale;
dval = p_conn->ts_ticks_per_second;
p_tcp->ts_ticks_per_second = cpu_to_le32(dval);
wval = p_conn->da_timeout_value;
p_tcp->da_timeout_value = cpu_to_le16(wval);
p_tcp->ack_frequency = p_conn->ack_frequency;

186
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
View File

@ -592,15 +592,15 @@
#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
#define QM_REG_WFQVPWEIGHT 0x2fa000UL
#define PGLCS_REG_DBG_SELECT \
#define PGLCS_REG_DBG_SELECT_K2 \
0x001d14UL
#define PGLCS_REG_DBG_DWORD_ENABLE \
#define PGLCS_REG_DBG_DWORD_ENABLE_K2 \
0x001d18UL
#define PGLCS_REG_DBG_SHIFT \
#define PGLCS_REG_DBG_SHIFT_K2 \
0x001d1cUL
#define PGLCS_REG_DBG_FORCE_VALID \
#define PGLCS_REG_DBG_FORCE_VALID_K2 \
0x001d20UL
#define PGLCS_REG_DBG_FORCE_FRAME \
#define PGLCS_REG_DBG_FORCE_FRAME_K2 \
0x001d24UL
#define MISC_REG_RESET_PL_PDA_VMAIN_1 \
0x008070UL
@ -612,7 +612,7 @@
0x009050UL
#define MISCS_REG_RESET_PL_HV \
0x009060UL
#define MISCS_REG_RESET_PL_HV_2 \
#define MISCS_REG_RESET_PL_HV_2_K2 \
0x009150UL
#define DMAE_REG_DBG_SELECT \
0x00c510UL
@ -644,15 +644,15 @@
0x0500b0UL
#define GRC_REG_DBG_FORCE_FRAME \
0x0500b4UL
#define UMAC_REG_DBG_SELECT \
#define UMAC_REG_DBG_SELECT_K2 \
0x051094UL
#define UMAC_REG_DBG_DWORD_ENABLE \
#define UMAC_REG_DBG_DWORD_ENABLE_K2 \
0x051098UL
#define UMAC_REG_DBG_SHIFT \
#define UMAC_REG_DBG_SHIFT_K2 \
0x05109cUL
#define UMAC_REG_DBG_FORCE_VALID \
#define UMAC_REG_DBG_FORCE_VALID_K2 \
0x0510a0UL
#define UMAC_REG_DBG_FORCE_FRAME \
#define UMAC_REG_DBG_FORCE_FRAME_K2 \
0x0510a4UL
#define MCP2_REG_DBG_SELECT \
0x052400UL
@ -924,15 +924,15 @@
0x4c160cUL
#define XYLD_REG_DBG_FORCE_FRAME \
0x4c1610UL
#define YULD_REG_DBG_SELECT \
#define YULD_REG_DBG_SELECT_BB_K2 \
0x4c9600UL
#define YULD_REG_DBG_DWORD_ENABLE \
#define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \
0x4c9604UL
#define YULD_REG_DBG_SHIFT \
#define YULD_REG_DBG_SHIFT_BB_K2 \
0x4c9608UL
#define YULD_REG_DBG_FORCE_VALID \
#define YULD_REG_DBG_FORCE_VALID_BB_K2 \
0x4c960cUL
#define YULD_REG_DBG_FORCE_FRAME \
#define YULD_REG_DBG_FORCE_FRAME_BB_K2 \
0x4c9610UL
#define TMLD_REG_DBG_SELECT \
0x4d1600UL
@ -994,35 +994,35 @@
0x580710UL
#define CDU_REG_DBG_FORCE_FRAME \
0x580714UL
#define WOL_REG_DBG_SELECT \
#define WOL_REG_DBG_SELECT_K2 \
0x600140UL
#define WOL_REG_DBG_DWORD_ENABLE \
#define WOL_REG_DBG_DWORD_ENABLE_K2 \
0x600144UL
#define WOL_REG_DBG_SHIFT \
#define WOL_REG_DBG_SHIFT_K2 \
0x600148UL
#define WOL_REG_DBG_FORCE_VALID \
#define WOL_REG_DBG_FORCE_VALID_K2 \
0x60014cUL
#define WOL_REG_DBG_FORCE_FRAME \
#define WOL_REG_DBG_FORCE_FRAME_K2 \
0x600150UL
#define BMBN_REG_DBG_SELECT \
#define BMBN_REG_DBG_SELECT_K2 \
0x610140UL
#define BMBN_REG_DBG_DWORD_ENABLE \
#define BMBN_REG_DBG_DWORD_ENABLE_K2 \
0x610144UL
#define BMBN_REG_DBG_SHIFT \
#define BMBN_REG_DBG_SHIFT_K2 \
0x610148UL
#define BMBN_REG_DBG_FORCE_VALID \
#define BMBN_REG_DBG_FORCE_VALID_K2 \
0x61014cUL
#define BMBN_REG_DBG_FORCE_FRAME \
#define BMBN_REG_DBG_FORCE_FRAME_K2 \
0x610150UL
#define NWM_REG_DBG_SELECT \
#define NWM_REG_DBG_SELECT_K2 \
0x8000ecUL
#define NWM_REG_DBG_DWORD_ENABLE \
#define NWM_REG_DBG_DWORD_ENABLE_K2 \
0x8000f0UL
#define NWM_REG_DBG_SHIFT \
#define NWM_REG_DBG_SHIFT_K2 \
0x8000f4UL
#define NWM_REG_DBG_FORCE_VALID \
#define NWM_REG_DBG_FORCE_VALID_K2 \
0x8000f8UL
#define NWM_REG_DBG_FORCE_FRAME \
#define NWM_REG_DBG_FORCE_FRAME_K2\
0x8000fcUL
#define PBF_REG_DBG_SELECT \
0xd80060UL
@ -1244,35 +1244,35 @@
0x1901534UL
#define USEM_REG_DBG_FORCE_FRAME \
0x1901538UL
#define NWS_REG_DBG_SELECT \
#define NWS_REG_DBG_SELECT_K2 \
0x700128UL
#define NWS_REG_DBG_DWORD_ENABLE \
#define NWS_REG_DBG_DWORD_ENABLE_K2 \
0x70012cUL
#define NWS_REG_DBG_SHIFT \
#define NWS_REG_DBG_SHIFT_K2 \
0x700130UL
#define NWS_REG_DBG_FORCE_VALID \
#define NWS_REG_DBG_FORCE_VALID_K2 \
0x700134UL
#define NWS_REG_DBG_FORCE_FRAME \
#define NWS_REG_DBG_FORCE_FRAME_K2 \
0x700138UL
#define MS_REG_DBG_SELECT \
#define MS_REG_DBG_SELECT_K2 \
0x6a0228UL
#define MS_REG_DBG_DWORD_ENABLE \
#define MS_REG_DBG_DWORD_ENABLE_K2 \
0x6a022cUL
#define MS_REG_DBG_SHIFT \
#define MS_REG_DBG_SHIFT_K2 \
0x6a0230UL
#define MS_REG_DBG_FORCE_VALID \
#define MS_REG_DBG_FORCE_VALID_K2 \
0x6a0234UL
#define MS_REG_DBG_FORCE_FRAME \
#define MS_REG_DBG_FORCE_FRAME_K2 \
0x6a0238UL
#define PCIE_REG_DBG_COMMON_SELECT \
#define PCIE_REG_DBG_COMMON_SELECT_K2 \
0x054398UL
#define PCIE_REG_DBG_COMMON_DWORD_ENABLE \
#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2 \
0x05439cUL
#define PCIE_REG_DBG_COMMON_SHIFT \
#define PCIE_REG_DBG_COMMON_SHIFT_K2 \
0x0543a0UL
#define PCIE_REG_DBG_COMMON_FORCE_VALID \
#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2 \
0x0543a4UL
#define PCIE_REG_DBG_COMMON_FORCE_FRAME \
#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2 \
0x0543a8UL
#define MISC_REG_RESET_PL_UA \
0x008050UL
@ -1328,85 +1328,85 @@
0x128170cUL
#define UCM_REG_SM_TASK_CTX \
0x1281710UL
#define XSEM_REG_SLOW_DBG_EMPTY \
#define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
0x1401140UL
#define XSEM_REG_SYNC_DBG_EMPTY \
0x1401160UL
#define XSEM_REG_SLOW_DBG_ACTIVE \
#define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
0x1401400UL
#define XSEM_REG_SLOW_DBG_MODE \
#define XSEM_REG_SLOW_DBG_MODE_BB_K2 \
0x1401404UL
#define XSEM_REG_DBG_FRAME_MODE \
#define XSEM_REG_DBG_FRAME_MODE_BB_K2 \
0x1401408UL
#define XSEM_REG_DBG_MODE1_CFG \
#define XSEM_REG_DBG_MODE1_CFG_BB_K2 \
0x1401420UL
#define XSEM_REG_FAST_MEMORY \
0x1440000UL
#define YSEM_REG_SYNC_DBG_EMPTY \
0x1501160UL
#define YSEM_REG_SLOW_DBG_ACTIVE \
#define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
0x1501400UL
#define YSEM_REG_SLOW_DBG_MODE \
#define YSEM_REG_SLOW_DBG_MODE_BB_K2 \
0x1501404UL
#define YSEM_REG_DBG_FRAME_MODE \
#define YSEM_REG_DBG_FRAME_MODE_BB_K2 \
0x1501408UL
#define YSEM_REG_DBG_MODE1_CFG \
#define YSEM_REG_DBG_MODE1_CFG_BB_K2 \
0x1501420UL
#define YSEM_REG_FAST_MEMORY \
0x1540000UL
#define PSEM_REG_SLOW_DBG_EMPTY \
#define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
0x1601140UL
#define PSEM_REG_SYNC_DBG_EMPTY \
0x1601160UL
#define PSEM_REG_SLOW_DBG_ACTIVE \
#define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
0x1601400UL
#define PSEM_REG_SLOW_DBG_MODE \
#define PSEM_REG_SLOW_DBG_MODE_BB_K2 \
0x1601404UL
#define PSEM_REG_DBG_FRAME_MODE \
#define PSEM_REG_DBG_FRAME_MODE_BB_K2 \
0x1601408UL
#define PSEM_REG_DBG_MODE1_CFG \
#define PSEM_REG_DBG_MODE1_CFG_BB_K2 \
0x1601420UL
#define PSEM_REG_FAST_MEMORY \
0x1640000UL
#define TSEM_REG_SLOW_DBG_EMPTY \
#define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
0x1701140UL
#define TSEM_REG_SYNC_DBG_EMPTY \
0x1701160UL
#define TSEM_REG_SLOW_DBG_ACTIVE \
#define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
0x1701400UL
#define TSEM_REG_SLOW_DBG_MODE \
#define TSEM_REG_SLOW_DBG_MODE_BB_K2 \
0x1701404UL
#define TSEM_REG_DBG_FRAME_MODE \
#define TSEM_REG_DBG_FRAME_MODE_BB_K2 \
0x1701408UL
#define TSEM_REG_DBG_MODE1_CFG \
#define TSEM_REG_DBG_MODE1_CFG_BB_K2 \
0x1701420UL
#define TSEM_REG_FAST_MEMORY \
0x1740000UL
#define MSEM_REG_SLOW_DBG_EMPTY \
#define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
0x1801140UL
#define MSEM_REG_SYNC_DBG_EMPTY \
0x1801160UL
#define MSEM_REG_SLOW_DBG_ACTIVE \
#define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
0x1801400UL
#define MSEM_REG_SLOW_DBG_MODE \
#define MSEM_REG_SLOW_DBG_MODE_BB_K2 \
0x1801404UL
#define MSEM_REG_DBG_FRAME_MODE \
#define MSEM_REG_DBG_FRAME_MODE_BB_K2 \
0x1801408UL
#define MSEM_REG_DBG_MODE1_CFG \
#define MSEM_REG_DBG_MODE1_CFG_BB_K2 \
0x1801420UL
#define MSEM_REG_FAST_MEMORY \
0x1840000UL
#define USEM_REG_SLOW_DBG_EMPTY \
#define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \
0x1901140UL
#define USEM_REG_SYNC_DBG_EMPTY \
0x1901160UL
#define USEM_REG_SLOW_DBG_ACTIVE \
#define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
0x1901400UL
#define USEM_REG_SLOW_DBG_MODE \
#define USEM_REG_SLOW_DBG_MODE_BB_K2 \
0x1901404UL
#define USEM_REG_DBG_FRAME_MODE \
#define USEM_REG_DBG_FRAME_MODE_BB_K2 \
0x1901408UL
#define USEM_REG_DBG_MODE1_CFG \
#define USEM_REG_DBG_MODE1_CFG_BB_K2 \
0x1901420UL
#define USEM_REG_FAST_MEMORY \
0x1940000UL
@ -1430,7 +1430,7 @@
0x340800UL
#define BRB_REG_BIG_RAM_DATA \
0x341500UL
#define SEM_FAST_REG_STALL_0 \
#define SEM_FAST_REG_STALL_0_BB_K2 \
0x000488UL
#define SEM_FAST_REG_STALLED \
0x000494UL
@ -1480,37 +1480,37 @@
4
#define MISC_REG_BLOCK_256B_EN \
0x008c14UL
#define NWS_REG_NWS_CMU \
#define NWS_REG_NWS_CMU_K2 \
0x720000UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 \
0x000680UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 \
0x000684UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 \
0x0006c0UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 \
0x0006c4UL
#define MS_REG_MS_CMU \
#define MS_REG_MS_CMU_K2 \
0x6a4000UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 \
0x000208UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \
0x000210UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 \
0x00020cUL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 \
0x000210UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 \
0x000214UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 \
0x000208UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 \
0x00020cUL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 \
0x000210UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 \
0x000214UL
#define PHY_PCIE_REG_PHY0 \
#define PHY_PCIE_REG_PHY0_K2 \
0x620000UL
#define PHY_PCIE_REG_PHY1 \
#define PHY_PCIE_REG_PHY1_K2 \
0x624000UL
#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
#define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL

4
drivers/net/ethernet/qlogic/qed/qed_roce.c
View File

@ -2431,10 +2431,6 @@ qed_rdma_register_tid(void *rdma_cxt,
RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG,
params->page_size_log - 12);
SET_FIELD(p_ramrod->flags,
RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID,
p_hwfn->p_rdma_info->last_tid);
SET_FIELD(p_ramrod->flags,
RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ,
params->remote_read);

23
drivers/net/ethernet/qlogic/qed/qed_sp_commands.c
View File

@ -185,22 +185,20 @@ static void qed_set_tunn_ports(struct qed_tunnel_info *p_tun,
}
static void
__qed_set_ramrod_tunnel_param(u8 *p_tunn_cls, u8 *p_enable_tx_clas,
__qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
struct qed_tunn_update_type *tun_type)
{
*p_tunn_cls = tun_type->tun_cls;
if (tun_type->b_mode_enabled)
*p_enable_tx_clas = 1;
}
static void
qed_set_ramrod_tunnel_param(u8 *p_tunn_cls, u8 *p_enable_tx_clas,
qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
struct qed_tunn_update_type *tun_type,
u8 *p_update_port, __le16 *p_port,
u8 *p_update_port,
__le16 *p_port,
struct qed_tunn_update_udp_port *p_udp_port)
{
__qed_set_ramrod_tunnel_param(p_tunn_cls, p_enable_tx_clas, tun_type);
__qed_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
if (p_udp_port->b_update_port) {
*p_update_port = 1;
*p_port = cpu_to_le16(p_udp_port->port);
@ -219,33 +217,27 @@ qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
qed_set_tunn_ports(p_tun, p_src);
qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
&p_tunn_cfg->tx_enable_vxlan,
&p_tun->vxlan,
&p_tunn_cfg->set_vxlan_udp_port_flg,
&p_tunn_cfg->vxlan_udp_port,
&p_tun->vxlan_port);
qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
&p_tunn_cfg->tx_enable_l2geneve,
&p_tun->l2_geneve,
&p_tunn_cfg->set_geneve_udp_port_flg,
&p_tunn_cfg->geneve_udp_port,
&p_tun->geneve_port);
__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
&p_tunn_cfg->tx_enable_ipgeneve,
&p_tun->ip_geneve);
__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
&p_tunn_cfg->tx_enable_l2gre,
&p_tun->l2_gre);
__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
&p_tunn_cfg->tx_enable_ipgre,
&p_tun->ip_gre);
p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
p_tunn_cfg->update_tx_pf_clss = p_tun->b_update_tx_cls;
}
static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
@ -289,29 +281,24 @@ qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
qed_set_tunn_ports(p_tun, p_src);
qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
&p_tunn_cfg->tx_enable_vxlan,
&p_tun->vxlan,
&p_tunn_cfg->set_vxlan_udp_port_flg,
&p_tunn_cfg->vxlan_udp_port,
&p_tun->vxlan_port);
qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
&p_tunn_cfg->tx_enable_l2geneve,
&p_tun->l2_geneve,
&p_tunn_cfg->set_geneve_udp_port_flg,
&p_tunn_cfg->geneve_udp_port,
&p_tun->geneve_port);
__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
&p_tunn_cfg->tx_enable_ipgeneve,
&p_tun->ip_geneve);
__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
&p_tunn_cfg->tx_enable_l2gre,
&p_tun->l2_gre);
__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
&p_tunn_cfg->tx_enable_ipgre,
&p_tun->ip_gre);
}

20
drivers/scsi/qedi/qedi_fw.c
View File

@ -2099,14 +2099,16 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
/* Update header info */
SET_FIELD(cmd_pdu_header.flags_attr, ISCSI_CMD_HDR_ATTR,
ISCSI_ATTR_SIMPLE);
if (sc->sc_data_direction == DMA_TO_DEVICE) {
SET_FIELD(cmd_pdu_header.flags_attr,
ISCSI_CMD_HDR_WRITE, 1);
task_type = ISCSI_TASK_TYPE_INITIATOR_WRITE;
} else {
SET_FIELD(cmd_pdu_header.flags_attr,
ISCSI_CMD_HDR_READ, 1);
task_type = ISCSI_TASK_TYPE_INITIATOR_READ;
if (hdr->cdb[0] != TEST_UNIT_READY) {
if (sc->sc_data_direction == DMA_TO_DEVICE) {
SET_FIELD(cmd_pdu_header.flags_attr,
ISCSI_CMD_HDR_WRITE, 1);
task_type = ISCSI_TASK_TYPE_INITIATOR_WRITE;
} else {
SET_FIELD(cmd_pdu_header.flags_attr,
ISCSI_CMD_HDR_READ, 1);
task_type = ISCSI_TASK_TYPE_INITIATOR_READ;
}
}
cmd_pdu_header.lun.lo = be32_to_cpu(scsi_lun[0]);
@ -2117,7 +2119,7 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
cmd_pdu_header.expected_transfer_length = cpu_to_be32(hdr->data_length);
cmd_pdu_header.hdr_second_dword = ntoh24(hdr->dlength);
cmd_pdu_header.cmd_sn = be32_to_cpu(hdr->cmdsn);
cmd_pdu_header.opcode = hdr->opcode;
cmd_pdu_header.hdr_first_byte = hdr->opcode;
qedi_cpy_scsi_cdb(sc, (u32 *)cmd_pdu_header.cdb);
/* Fill tx AHS and rx buffer */

3
drivers/scsi/qedi/qedi_fw_api.c
View File

@ -578,7 +578,8 @@ int init_initiator_rw_iscsi_task(struct iscsi_task_params *task_params,
(struct iscsi_common_hdr *)cmd_header,
tx_sgl_params, cmd_params,
dif_task_params);
else if (GET_FIELD(cmd_header->flags_attr, ISCSI_CMD_HDR_READ))
else if (GET_FIELD(cmd_header->flags_attr, ISCSI_CMD_HDR_READ) ||
(task_params->rx_io_size == 0 && task_params->tx_io_size == 0))
return init_rw_iscsi_task(task_params,
ISCSI_TASK_TYPE_INITIATOR_READ,
conn_params,

3
drivers/scsi/qedi/qedi_iscsi.c
View File

@ -1461,9 +1461,6 @@ static const struct {
{ ISCSI_CONN_ERROR_OUT_OF_SGES_ERROR,
"out of sge error"
},
{ ISCSI_CONN_ERROR_TCP_SEG_PROC_IP_OPTIONS_ERROR,
"tcp seg ip options error"
},
{ ISCSI_CONN_ERROR_TCP_IP_FRAGMENT_ERROR,
"tcp ip fragment error"
},

209
include/linux/qed/common_hsi.h
View File

@ -96,12 +96,12 @@
#define CORE_SPQE_PAGE_SIZE_BYTES 4096
#define MAX_NUM_LL2_RX_QUEUES 32
#define MAX_NUM_LL2_TX_STATS_COUNTERS 32
#define MAX_NUM_LL2_RX_QUEUES 48
#define MAX_NUM_LL2_TX_STATS_COUNTERS 48
#define FW_MAJOR_VERSION 8
#define FW_MINOR_VERSION 15
#define FW_REVISION_VERSION 3
#define FW_MINOR_VERSION 20
#define FW_REVISION_VERSION 0
#define FW_ENGINEERING_VERSION 0
/***********************/
@ -181,6 +181,14 @@
#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1)
#define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2)
#define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3)
#define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4)
#define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5)
/*****************/
/* DQ CONSTANTS */
/*****************/
@ -457,7 +465,6 @@
#define PXP_BAR_DQ 1
/* PTT and GTT */
#define PXP_NUM_PF_WINDOWS 12
#define PXP_PER_PF_ENTRY_SIZE 8
#define PXP_NUM_GLOBAL_WINDOWS 243
#define PXP_GLOBAL_ENTRY_SIZE 4
@ -482,6 +489,7 @@
#define PXP_PF_ME_OPAQUE_ADDR 0x1f8
#define PXP_PF_ME_CONCRETE_ADDR 0x1fc
#define PXP_NUM_PF_WINDOWS 12
#define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS
#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
@ -618,16 +626,21 @@
/*****************/
/* PRM CONSTANTS */
/*****************/
#define PRM_DMA_PAD_BYTES_NUM 2
/******************/
/* SDMs CONSTANTS */
/******************/
#define SDM_OP_GEN_TRIG_NONE 0
#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
#define SDM_OP_GEN_TRIG_AGG_INT 2
#define SDM_OP_GEN_TRIG_LOADER 4
#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
#define SDM_OP_GEN_TRIG_RELEASE_THREAD 7
#define PRM_DMA_PAD_BYTES_NUM 2
/*****************/
/* SDMs CONSTANTS */
/*****************/
#define SDM_OP_GEN_TRIG_NONE 0
#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
#define SDM_OP_GEN_TRIG_AGG_INT 2
#define SDM_OP_GEN_TRIG_LOADER 4
#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
#define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9
/********************/
/* Completion types */
/********************/
#define SDM_COMP_TYPE_NONE 0
#define SDM_COMP_TYPE_WAKE_THREAD 1
@ -638,10 +651,11 @@
#define SDM_COMP_TYPE_INDICATE_ERROR 6
#define SDM_COMP_TYPE_RELEASE_THREAD 7
#define SDM_COMP_TYPE_RAM 8
#define SDM_COMP_TYPE_INC_ORDER_CNT 9
/******************/
/* PBF CONSTANTS */
/******************/
/*****************/
/* PBF Constants */
/*****************/
/* Number of PBF command queue lines. Each line is 32B. */
#define PBF_MAX_CMD_LINES 3328
@ -861,7 +875,7 @@ enum db_dest {
/* Enum of doorbell DPM types */
enum db_dpm_type {
DPM_LEGACY,
DPM_ROCE,
DPM_RDMA,
DPM_L2_INLINE,
DPM_L2_BD,
MAX_DB_DPM_TYPE
@ -884,8 +898,8 @@ struct db_l2_dpm_data {
#define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
#define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
#define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28
#define DB_L2_DPM_DATA_RESERVED1_MASK 0x1
#define DB_L2_DPM_DATA_RESERVED1_SHIFT 31
#define DB_L2_DPM_DATA_GFS_SRC_EN_MASK 0x1
#define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT 31
};
/* Structure for SGE in a DPM doorbell of type DPM_L2_BD */
@ -931,31 +945,33 @@ struct db_pwm_addr {
};
/* Parameters to RoCE firmware, passed in EDPM doorbell */
struct db_roce_dpm_params {
struct db_rdma_dpm_params {
__le32 params;
#define DB_ROCE_DPM_PARAMS_SIZE_MASK 0x3F
#define DB_ROCE_DPM_PARAMS_SIZE_SHIFT 0
#define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK 0x3
#define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT 6
#define DB_ROCE_DPM_PARAMS_OPCODE_MASK 0xFF
#define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT 8
#define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
#define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT 16
#define DB_ROCE_DPM_PARAMS_RESERVED0_MASK 0x1
#define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT 27
#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
#define DB_ROCE_DPM_PARAMS_S_FLG_MASK 0x1
#define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT 29
#define DB_ROCE_DPM_PARAMS_RESERVED1_MASK 0x3
#define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT 30
#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1
#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30
#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
};
/* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */
struct db_roce_dpm_data {
struct db_rdma_dpm_data {
__le16 icid;
__le16 prod_val;
struct db_roce_dpm_params params;
struct db_rdma_dpm_params params;
};
/* Igu interrupt command */
@ -1026,6 +1042,42 @@ struct parsing_and_err_flags {
#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
};
struct parsing_err_flags {
__le16 flags;
#define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
#define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0
#define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1
#define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1
#define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1
#define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2
#define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1
#define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3
#define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1
#define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4
#define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1
#define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5
#define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1
#define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6
#define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1
#define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7
#define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1
#define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8
#define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1
#define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9
#define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1
#define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10
#define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1
#define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11
#define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1
#define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12
#define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1
#define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13
#define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1
#define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14
#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1
#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15
};
struct pb_context {
__le32 crc[4];
};
@ -1288,39 +1340,56 @@ struct tdif_task_context {
struct timers_context {
__le32 logical_client_0;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
#define TIMERS_CONTEXT_VALIDLC0_SHIFT 28
#define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
#define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
#define TIMERS_CONTEXT_RESERVED0_MASK 0x3
#define TIMERS_CONTEXT_RESERVED0_SHIFT 30
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
#define TIMERS_CONTEXT_RESERVED0_MASK 0x1
#define TIMERS_CONTEXT_RESERVED0_SHIFT 27
#define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
#define TIMERS_CONTEXT_VALIDLC0_SHIFT 28
#define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
#define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
#define TIMERS_CONTEXT_RESERVED1_MASK 0x3
#define TIMERS_CONTEXT_RESERVED1_SHIFT 30
__le32 logical_client_1;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
#define TIMERS_CONTEXT_VALIDLC1_SHIFT 28
#define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
#define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
#define TIMERS_CONTEXT_RESERVED1_MASK 0x3
#define TIMERS_CONTEXT_RESERVED1_SHIFT 30
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
#define TIMERS_CONTEXT_RESERVED2_MASK 0x1
#define TIMERS_CONTEXT_RESERVED2_SHIFT 27
#define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
#define TIMERS_CONTEXT_VALIDLC1_SHIFT 28
#define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
#define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
#define TIMERS_CONTEXT_RESERVED3_MASK 0x3
#define TIMERS_CONTEXT_RESERVED3_SHIFT 30
__le32 logical_client_2;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
#define TIMERS_CONTEXT_VALIDLC2_SHIFT 28
#define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
#define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29
#define TIMERS_CONTEXT_RESERVED2_MASK 0x3
#define TIMERS_CONTEXT_RESERVED2_SHIFT 30
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
#define TIMERS_CONTEXT_RESERVED4_MASK 0x1
#define TIMERS_CONTEXT_RESERVED4_SHIFT 27
#define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
#define TIMERS_CONTEXT_VALIDLC2_SHIFT 28
#define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
#define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29
#define TIMERS_CONTEXT_RESERVED5_MASK 0x3
#define TIMERS_CONTEXT_RESERVED5_SHIFT 30
__le32 host_expiration_fields;
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28
#define TIMERS_CONTEXT_RESERVED3_MASK 0x7
#define TIMERS_CONTEXT_RESERVED3_SHIFT 29
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
#define TIMERS_CONTEXT_RESERVED6_MASK 0x1
#define TIMERS_CONTEXT_RESERVED6_SHIFT 27
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28
#define TIMERS_CONTEXT_RESERVED7_MASK 0x7
#define TIMERS_CONTEXT_RESERVED7_SHIFT 29
};
enum tunnel_next_protocol {
e_unknown = 0,
e_l2 = 1,
e_ipv4 = 2,
e_ipv6 = 3,
MAX_TUNNEL_NEXT_PROTOCOL
};
#endif /* __COMMON_HSI__ */
#endif

3
include/linux/qed/eth_common.h
View File

@ -75,7 +75,8 @@
(ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
/* Maximum number of buffers, used for RX packet placement */
#define ETH_RX_MAX_BUFF_PER_PKT 5
#define ETH_RX_MAX_BUFF_PER_PKT 5
#define ETH_RX_BD_THRESHOLD 12
/* num of MAC/VLAN filters */
#define ETH_NUM_MAC_FILTERS 512

1
include/linux/qed/fcoe_common.h
View File

@ -13,7 +13,6 @@
/*********************/
#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
#define FCOE_MAX_SIZE_FCP_DATA_SUPER (8600)
struct fcoe_abts_pkt {
__le32 abts_rsp_fc_payload_lo;

91
include/linux/qed/iscsi_common.h
View File

@ -75,25 +75,13 @@
#define ISCSI_TARGET_MODE 1
/* iSCSI request op codes */
#define ISCSI_OPCODE_NOP_OUT_NO_IMM (0)
#define ISCSI_OPCODE_NOP_OUT ( \
ISCSI_OPCODE_NOP_OUT_NO_IMM | 0x40)
#define ISCSI_OPCODE_SCSI_CMD_NO_IMM (1)
#define ISCSI_OPCODE_SCSI_CMD ( \
ISCSI_OPCODE_SCSI_CMD_NO_IMM | 0x40)
#define ISCSI_OPCODE_TMF_REQUEST_NO_IMM (2)
#define ISCSI_OPCODE_TMF_REQUEST ( \
ISCSI_OPCODE_TMF_REQUEST_NO_IMM | 0x40)
#define ISCSI_OPCODE_LOGIN_REQUEST_NO_IMM (3)
#define ISCSI_OPCODE_LOGIN_REQUEST ( \
ISCSI_OPCODE_LOGIN_REQUEST_NO_IMM | 0x40)
#define ISCSI_OPCODE_TEXT_REQUEST_NO_IMM (4)
#define ISCSI_OPCODE_TEXT_REQUEST ( \
ISCSI_OPCODE_TEXT_REQUEST_NO_IMM | 0x40)
#define ISCSI_OPCODE_DATA_OUT (5)
#define ISCSI_OPCODE_LOGOUT_REQUEST_NO_IMM (6)
#define ISCSI_OPCODE_LOGOUT_REQUEST ( \
ISCSI_OPCODE_LOGOUT_REQUEST_NO_IMM | 0x40)
#define ISCSI_OPCODE_NOP_OUT (0)
#define ISCSI_OPCODE_SCSI_CMD (1)
#define ISCSI_OPCODE_TMF_REQUEST (2)
#define ISCSI_OPCODE_LOGIN_REQUEST (3)
#define ISCSI_OPCODE_TEXT_REQUEST (4)
#define ISCSI_OPCODE_DATA_OUT (5)
#define ISCSI_OPCODE_LOGOUT_REQUEST (6)
/* iSCSI response/messages op codes */
#define ISCSI_OPCODE_NOP_IN (0x20)
@ -172,17 +160,23 @@ struct iscsi_async_msg_hdr {
struct iscsi_cmd_hdr {
__le16 reserved1;
u8 flags_attr;
#define ISCSI_CMD_HDR_ATTR_MASK 0x7
#define ISCSI_CMD_HDR_ATTR_SHIFT 0
#define ISCSI_CMD_HDR_RSRV_MASK 0x3
#define ISCSI_CMD_HDR_RSRV_SHIFT 3
#define ISCSI_CMD_HDR_WRITE_MASK 0x1
#define ISCSI_CMD_HDR_WRITE_SHIFT 5
#define ISCSI_CMD_HDR_READ_MASK 0x1
#define ISCSI_CMD_HDR_READ_SHIFT 6
#define ISCSI_CMD_HDR_FINAL_MASK 0x1
#define ISCSI_CMD_HDR_FINAL_SHIFT 7
u8 opcode;
#define ISCSI_CMD_HDR_ATTR_MASK 0x7
#define ISCSI_CMD_HDR_ATTR_SHIFT 0
#define ISCSI_CMD_HDR_RSRV_MASK 0x3
#define ISCSI_CMD_HDR_RSRV_SHIFT 3
#define ISCSI_CMD_HDR_WRITE_MASK 0x1
#define ISCSI_CMD_HDR_WRITE_SHIFT 5
#define ISCSI_CMD_HDR_READ_MASK 0x1
#define ISCSI_CMD_HDR_READ_SHIFT 6
#define ISCSI_CMD_HDR_FINAL_MASK 0x1
#define ISCSI_CMD_HDR_FINAL_SHIFT 7
u8 hdr_first_byte;
#define ISCSI_CMD_HDR_OPCODE_MASK 0x3F
#define ISCSI_CMD_HDR_OPCODE_SHIFT 0
#define ISCSI_CMD_HDR_IMM_MASK 0x1
#define ISCSI_CMD_HDR_IMM_SHIFT 6
#define ISCSI_CMD_HDR_RSRV1_MASK 0x1
#define ISCSI_CMD_HDR_RSRV1_SHIFT 7
__le32 hdr_second_dword;
#define ISCSI_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
#define ISCSI_CMD_HDR_DATA_SEG_LEN_SHIFT 0
@ -790,9 +784,9 @@ enum iscsi_error_types {
ISCSI_CONN_ERROR_LOCAL_COMPLETION_ERROR,
ISCSI_CONN_ERROR_DATA_OVERRUN,
ISCSI_CONN_ERROR_OUT_OF_SGES_ERROR,
ISCSI_CONN_ERROR_TCP_SEG_PROC_URG_ERROR,
ISCSI_CONN_ERROR_TCP_SEG_PROC_IP_OPTIONS_ERROR,
ISCSI_CONN_ERROR_TCP_SEG_PROC_CONNECT_INVALID_WS_OPTION,
ISCSI_CONN_ERROR_IP_OPTIONS_ERROR,
ISCSI_CONN_ERROR_PRS_ERRORS,
ISCSI_CONN_ERROR_CONNECT_INVALID_TCP_OPTION,
ISCSI_CONN_ERROR_TCP_IP_FRAGMENT_ERROR,
ISCSI_CONN_ERROR_PROTOCOL_ERR_AHS_LEN,
ISCSI_CONN_ERROR_PROTOCOL_ERR_AHS_TYPE,
@ -1304,22 +1298,6 @@ struct ystorm_iscsi_stats_drv {
struct regpair iscsi_tx_total_pdu_cnt;
};
struct iscsi_db_data {
u8 params;
#define ISCSI_DB_DATA_DEST_MASK 0x3
#define ISCSI_DB_DATA_DEST_SHIFT 0
#define ISCSI_DB_DATA_AGG_CMD_MASK 0x3
#define ISCSI_DB_DATA_AGG_CMD_SHIFT 2
#define ISCSI_DB_DATA_BYPASS_EN_MASK 0x1
#define ISCSI_DB_DATA_BYPASS_EN_SHIFT 4
#define ISCSI_DB_DATA_RESERVED_MASK 0x1
#define ISCSI_DB_DATA_RESERVED_SHIFT 5
#define ISCSI_DB_DATA_AGG_VAL_SEL_MASK 0x3
#define ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 sq_prod;
};
struct tstorm_iscsi_task_ag_ctx {
u8 byte0;
u8 byte1;
@ -1398,5 +1376,20 @@ struct tstorm_iscsi_task_ag_ctx {
__le32 reg1;
__le32 reg2;
};
struct iscsi_db_data {
u8 params;
#define ISCSI_DB_DATA_DEST_MASK 0x3
#define ISCSI_DB_DATA_DEST_SHIFT 0
#define ISCSI_DB_DATA_AGG_CMD_MASK 0x3
#define ISCSI_DB_DATA_AGG_CMD_SHIFT 2
#define ISCSI_DB_DATA_BYPASS_EN_MASK 0x1
#define ISCSI_DB_DATA_BYPASS_EN_SHIFT 4
#define ISCSI_DB_DATA_RESERVED_MASK 0x1
#define ISCSI_DB_DATA_RESERVED_SHIFT 5
#define ISCSI_DB_DATA_AGG_VAL_SEL_MASK 0x3
#define ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 sq_prod;
};
#endif /* __ISCSI_COMMON__ */

2
include/linux/qed/rdma_common.h
View File

@ -42,7 +42,7 @@
#define RDMA_MAX_SGE_PER_SQ_WQE (4)
#define RDMA_MAX_SGE_PER_RQ_WQE (4)
#define RDMA_MAX_DATA_SIZE_IN_WQE (0x7FFFFFFF)
#define RDMA_MAX_DATA_SIZE_IN_WQE (0x80000000)
#define RDMA_REQ_RD_ATOMIC_ELM_SIZE (0x50)
#define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20)

2
include/linux/qed/roce_common.h
View File

@ -37,6 +37,8 @@
#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288)
#define ROCE_MAX_QPS (32 * 1024)
#define ROCE_DCQCN_NP_MAX_QPS (64)
#define ROCE_DCQCN_RP_MAX_QPS (64)
enum roce_async_events_type {
ROCE_ASYNC_EVENT_NONE = 0,

5
include/linux/qed/tcp_common.h
View File

@ -111,7 +111,6 @@ struct tcp_offload_params {
__le32 snd_wnd;
__le32 rcv_wnd;
__le32 snd_wl1;
__le32 ts_time;
__le32 ts_recent;
__le32 ts_recent_age;
__le32 total_rt;
@ -122,7 +121,7 @@ struct tcp_offload_params {
u8 ka_probe_cnt;
u8 rt_cnt;
__le16 rtt_var;
__le16 reserved2;
__le16 fw_internal;
__le32 ka_timeout;
__le32 ka_interval;
__le32 max_rt_time;
@ -130,7 +129,7 @@ struct tcp_offload_params {
u8 snd_wnd_scale;
u8 ack_frequency;
__le16 da_timeout_value;
__le32 ts_ticks_per_second;
__le32 reserved3[2];
};
struct tcp_offload_params_opt2 {