hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ARM: tegra: apalis_t30: get rid of fake clocks simple bus 

Get rid of the fake clocks simple bus and use node names as per the
actual schematics.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Marcel Ziswiler 2018-08-31 18:38:06 +02:00 committed by Thierry Reding
parent 200be313fd
commit 7b0f47aa62
1 changed files with 9 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
arch/arm/boot/dts/tegra30-apalis.dtsi
View File

@ -1097,25 +1097,16 @@
mmc-ddr-1_8v;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: xtal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
clk32k_in: clk@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
clk16m: clk@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "clk16m";
};
clk16m: osc4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {