dma: shdma: transfer based runtime PM
Currently the shdma dmaengine driver uses runtime PM to save power, when no channel on the specific controller is requested by a user. This patch switches the driver to count individual DMA transfers. That way the controller can be powered down between transfers, even if some of its channels are in use. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski
Vinod Koul
parent
b4dae6e1ad
commit
7a1cd9ad87
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@ -259,15 +259,23 @@ static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
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return 0;
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}
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static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan);
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static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
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struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
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struct sh_dmae_slave *param = tx->chan->private;
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dma_async_tx_callback callback = tx->callback;
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dma_cookie_t cookie;
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unsigned long flags;
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bool power_up;
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spin_lock_irqsave(&sh_chan->desc_lock, flags);
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spin_lock_irq(&sh_chan->desc_lock);
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if (list_empty(&sh_chan->ld_queue))
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power_up = true;
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else
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power_up = false;
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cookie = sh_chan->common.cookie;
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cookie++;
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@ -303,7 +311,38 @@ static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
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tx->cookie, &last->async_tx, sh_chan->id,
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desc->hw.sar, desc->hw.tcr, desc->hw.dar);
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spin_unlock_irqrestore(&sh_chan->desc_lock, flags);
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if (power_up) {
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sh_chan->pm_state = DMAE_PM_BUSY;
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pm_runtime_get(sh_chan->dev);
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spin_unlock_irq(&sh_chan->desc_lock);
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pm_runtime_barrier(sh_chan->dev);
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spin_lock_irq(&sh_chan->desc_lock);
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/* Have we been reset, while waiting? */
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if (sh_chan->pm_state != DMAE_PM_ESTABLISHED) {
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dev_dbg(sh_chan->dev, "Bring up channel %d\n",
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sh_chan->id);
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if (param) {
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const struct sh_dmae_slave_config *cfg =
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param->config;
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dmae_set_dmars(sh_chan, cfg->mid_rid);
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dmae_set_chcr(sh_chan, cfg->chcr);
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} else {
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dmae_init(sh_chan);
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}
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if (sh_chan->pm_state == DMAE_PM_PENDING)
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sh_chan_xfer_ld_queue(sh_chan);
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sh_chan->pm_state = DMAE_PM_ESTABLISHED;
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}
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}
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spin_unlock_irq(&sh_chan->desc_lock);
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return cookie;
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}
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@ -347,8 +386,6 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
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struct sh_dmae_slave *param = chan->private;
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int ret;
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pm_runtime_get_sync(sh_chan->dev);
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/*
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* This relies on the guarantee from dmaengine that alloc_chan_resources
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* never runs concurrently with itself or free_chan_resources.
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@ -368,11 +405,6 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
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}
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param->config = cfg;
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dmae_set_dmars(sh_chan, cfg->mid_rid);
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dmae_set_chcr(sh_chan, cfg->chcr);
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} else {
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dmae_init(sh_chan);
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}
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while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
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@ -401,7 +433,6 @@ edescalloc:
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etestused:
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efindslave:
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chan->private = NULL;
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pm_runtime_put(sh_chan->dev);
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return ret;
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}
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@ -413,7 +444,6 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan)
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struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
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struct sh_desc *desc, *_desc;
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LIST_HEAD(list);
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int descs = sh_chan->descs_allocated;
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/* Protect against ISR */
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spin_lock_irq(&sh_chan->desc_lock);
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@ -440,9 +470,6 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan)
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spin_unlock_irq(&sh_chan->desc_lock);
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if (descs > 0)
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pm_runtime_put(sh_chan->dev);
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list_for_each_entry_safe(desc, _desc, &list, node)
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kfree(desc);
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}
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@ -676,7 +703,6 @@ static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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struct sh_desc, node);
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desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
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sh_chan->xmit_shift;
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}
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spin_unlock_irqrestore(&sh_chan->desc_lock, flags);
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@ -761,7 +787,13 @@ static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all
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async_tx_test_ack(&desc->async_tx)) || all) {
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/* Remove from ld_queue list */
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desc->mark = DESC_IDLE;
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list_move(&desc->node, &sh_chan->ld_free);
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if (list_empty(&sh_chan->ld_queue)) {
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dev_dbg(sh_chan->dev, "Bring down channel %d\n", sh_chan->id);
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pm_runtime_put(sh_chan->dev);
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}
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}
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}
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@ -791,16 +823,14 @@ static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
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;
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}
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/* Called under spin_lock_irq(&sh_chan->desc_lock) */
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static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
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{
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struct sh_desc *desc;
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spin_lock_irq(&sh_chan->desc_lock);
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/* DMA work check */
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if (dmae_is_busy(sh_chan)) {
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spin_unlock_irq(&sh_chan->desc_lock);
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if (dmae_is_busy(sh_chan))
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return;
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}
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/* Find the first not transferred descriptor */
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list_for_each_entry(desc, &sh_chan->ld_queue, node)
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@ -813,14 +843,18 @@ static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
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dmae_start(sh_chan);
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break;
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}
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spin_unlock_irq(&sh_chan->desc_lock);
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}
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static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
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{
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struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
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sh_chan_xfer_ld_queue(sh_chan);
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spin_lock_irq(&sh_chan->desc_lock);
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if (sh_chan->pm_state == DMAE_PM_ESTABLISHED)
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sh_chan_xfer_ld_queue(sh_chan);
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else
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sh_chan->pm_state = DMAE_PM_PENDING;
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spin_unlock_irq(&sh_chan->desc_lock);
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}
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static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
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@ -913,6 +947,12 @@ static bool sh_dmae_reset(struct sh_dmae_device *shdev)
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list_splice_init(&sh_chan->ld_queue, &dl);
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if (!list_empty(&dl)) {
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dev_dbg(sh_chan->dev, "Bring down channel %d\n", sh_chan->id);
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pm_runtime_put(sh_chan->dev);
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}
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sh_chan->pm_state = DMAE_PM_ESTABLISHED;
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spin_unlock(&sh_chan->desc_lock);
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/* Complete all */
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@ -966,10 +1006,10 @@ static void dmae_do_tasklet(unsigned long data)
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break;
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}
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}
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spin_unlock_irq(&sh_chan->desc_lock);
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/* Next desc */
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sh_chan_xfer_ld_queue(sh_chan);
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spin_unlock_irq(&sh_chan->desc_lock);
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sh_dmae_chan_ld_cleanup(sh_chan, false);
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}
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@ -1037,7 +1077,9 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
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return -ENOMEM;
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}
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/* copy struct dma_device */
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new_sh_chan->pm_state = DMAE_PM_ESTABLISHED;
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/* reference struct dma_device */
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new_sh_chan->common.device = &shdev->common;
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new_sh_chan->dev = shdev->common.dev;
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@ -23,6 +23,12 @@
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struct device;
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enum dmae_pm_state {
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DMAE_PM_ESTABLISHED,
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DMAE_PM_BUSY,
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DMAE_PM_PENDING,
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};
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struct sh_dmae_chan {
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dma_cookie_t completed_cookie; /* The maximum cookie completed */
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spinlock_t desc_lock; /* Descriptor operation lock */
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@ -38,6 +44,7 @@ struct sh_dmae_chan {
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u32 __iomem *base;
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char dev_id[16]; /* unique name per DMAC of channel */
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int pm_error;
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enum dmae_pm_state pm_state;
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};
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struct sh_dmae_device {
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