Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf tooling fixes from Ingo Molnar: "Leftover perf tooling fixes from the v4.17 cycle: they sync up updated ABI headers with their tooling versions" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf tools intel-pt-decoder: Update insn.h from the kernel sources tools headers: Sync x86 cpufeatures.h with the kernel sources tools headers: Synchronize prctl.h ABI header perf trace beauty prctl: Default header_dir to cwd to work without parms
This commit is contained in:
Linus Torvalds
commit
7a1b437379
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@ -198,7 +198,6 @@
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#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
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#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
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#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
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#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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@ -207,13 +206,19 @@
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#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
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#define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
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#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
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#define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */
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#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
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#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
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#define X86_FEATURE_SEV ( 7*32+20) /* AMD Secure Encrypted Virtualization */
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#define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
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#define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
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#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
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#define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */
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#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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@ -274,9 +279,10 @@
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#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
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#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
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#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
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#define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
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#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
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#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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@ -334,6 +340,7 @@
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#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
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#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
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#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
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/*
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* BUG word(s)
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@ -363,5 +370,6 @@
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#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */
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#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */
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#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
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#define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */
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#endif /* _ASM_X86_CPUFEATURES_H */
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@ -207,4 +207,16 @@ struct prctl_mm_map {
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# define PR_SVE_VL_LEN_MASK 0xffff
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# define PR_SVE_VL_INHERIT (1 << 17) /* inherit across exec */
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/* Per task speculation control */
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#define PR_GET_SPECULATION_CTRL 52
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#define PR_SET_SPECULATION_CTRL 53
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/* Speculation control variants */
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# define PR_SPEC_STORE_BYPASS 0
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/* Return and control values for PR_SET/GET_SPECULATION_CTRL */
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# define PR_SPEC_NOT_AFFECTED 0
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# define PR_SPEC_PRCTL (1UL << 0)
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# define PR_SPEC_ENABLE (1UL << 1)
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# define PR_SPEC_DISABLE (1UL << 2)
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# define PR_SPEC_FORCE_DISABLE (1UL << 3)
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#endif /* _LINUX_PRCTL_H */
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@ -1,6 +1,6 @@
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#!/bin/sh
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header_dir=$1
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[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/linux/
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printf "static const char *prctl_options[] = {\n"
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regex='^#define[[:space:]]+PR_([GS]ET\w+)[[:space:]]*([[:xdigit:]]+).*'
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@ -208,4 +208,22 @@ static inline int insn_offset_immediate(struct insn *insn)
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return insn_offset_displacement(insn) + insn->displacement.nbytes;
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}
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#define POP_SS_OPCODE 0x1f
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#define MOV_SREG_OPCODE 0x8e
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/*
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* Intel SDM Vol.3A 6.8.3 states;
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* "Any single-step trap that would be delivered following the MOV to SS
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* instruction or POP to SS instruction (because EFLAGS.TF is 1) is
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* suppressed."
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* This function returns true if @insn is MOV SS or POP SS. On these
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* instructions, single stepping is suppressed.
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*/
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static inline int insn_masking_exception(struct insn *insn)
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{
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return insn->opcode.bytes[0] == POP_SS_OPCODE ||
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(insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
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X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
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}
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#endif /* _ASM_X86_INSN_H */
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