iwlagn: iwl-trans.c can't dereference iwl_priv any more
This reaches encapsulation for this file. In order to reach this: * move priv->valid_context to iwl_shared * move the last_rejected initialization to the upper layer * define a wrapper iwl_nic_config in the upper layer that calls to cfg->lib->ops->nic_config Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -659,7 +659,7 @@ int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
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IWL_SCD_BE_MSK | IWL_SCD_BK_MSK |
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IWL_SCD_MGMT_MSK;
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if ((flush_control & BIT(IWL_RXON_CTX_PAN)) &&
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(priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)))
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(priv->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS)))
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flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK |
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IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK |
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IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK |
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@ -311,7 +311,7 @@ int iwlagn_set_pan_params(struct iwl_priv *priv)
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int slot0 = 300, slot1 = 0;
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int ret;
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if (priv->valid_contexts == BIT(IWL_RXON_CTX_BSS))
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if (priv->shrd->valid_contexts == BIT(IWL_RXON_CTX_BSS))
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return 0;
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BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
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@ -349,6 +349,7 @@ int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
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static int iwlagn_alive_notify(struct iwl_priv *priv)
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{
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struct iwl_rxon_context *ctx;
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int ret;
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if (!priv->tx_cmd_pool)
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@ -361,6 +362,8 @@ static int iwlagn_alive_notify(struct iwl_priv *priv)
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return -ENOMEM;
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iwl_trans_tx_start(trans(priv));
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for_each_context(priv, ctx)
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ctx->last_tx_rejected = false;
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ret = iwlagn_send_wimax_coex(priv);
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if (ret)
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@ -623,9 +623,9 @@ static void iwl_init_context(struct iwl_priv *priv, u32 ucode_flags)
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* The default context is always valid,
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* the PAN context depends on uCode.
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*/
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priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
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priv->shrd->valid_contexts = BIT(IWL_RXON_CTX_BSS);
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if (ucode_flags & IWL_UCODE_TLV_FLAGS_PAN)
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priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
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priv->shrd->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
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for (i = 0; i < NUM_IWL_RXON_CTX; i++)
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priv->contexts[i].ctxid = i;
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@ -2880,7 +2880,7 @@ static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
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struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
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int err = 0;
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if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
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if (!(priv->shrd->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
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return -EOPNOTSUPP;
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if (!(ctx->interface_modes & BIT(NL80211_IFTYPE_P2P_CLIENT)))
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@ -2945,7 +2945,7 @@ static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
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{
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struct iwl_priv *priv = hw->priv;
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if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
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if (!(priv->shrd->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
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return -EOPNOTSUPP;
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mutex_lock(&priv->shrd->mutex);
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@ -1870,3 +1870,9 @@ void iwl_set_hw_rfkill_state(struct iwl_priv *priv, bool state)
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{
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wiphy_rfkill_set_hw_state(priv->hw->wiphy, state);
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}
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void iwl_nic_config(struct iwl_priv *priv)
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{
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priv->cfg->lib->nic_config(priv);
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}
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@ -439,4 +439,22 @@
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*/
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#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
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/**********************************************************
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* CSR values
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**********************************************************/
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/*
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* host interrupt timeout value
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* used with setting interrupt coalescing timer
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* the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
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*
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* default interrupt coalescing timer is 64 x 32 = 2048 usecs
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* default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
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*/
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#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
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#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
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#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
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#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
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#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
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#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
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#endif /* !__iwl_csr_h__ */
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@ -117,21 +117,6 @@ struct iwl_channel_info {
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u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
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};
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#define IWL_TX_FIFO_BK 0 /* shared */
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#define IWL_TX_FIFO_BE 1
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#define IWL_TX_FIFO_VI 2 /* shared */
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#define IWL_TX_FIFO_VO 3
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#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
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#define IWL_TX_FIFO_BE_IPAN 4
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#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
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#define IWL_TX_FIFO_VO_IPAN 5
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/* re-uses the VO FIFO, uCode will properly flush/schedule */
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#define IWL_TX_FIFO_AUX 5
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#define IWL_TX_FIFO_UNUSED -1
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/* AUX (TX during scan dwell) queue */
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#define IWL_AUX_QUEUE 10
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/*
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* Minimum number of queues. MAX_NUM is defined in hw specific files.
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* Set the minimum to accommodate
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@ -544,9 +529,6 @@ struct iwl_chain_noise_data {
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#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
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#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
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#define IWL_TRAFFIC_ENTRIES (256)
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#define IWL_TRAFFIC_ENTRY_SIZE (64)
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enum {
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MEASUREMENT_READY = (1 << 0),
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MEASUREMENT_ACTIVE = (1 << 1),
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@ -687,21 +669,6 @@ struct iwl_event_log {
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int wraps_more_count;
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};
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/*
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* host interrupt timeout value
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* used with setting interrupt coalescing timer
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* the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
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*
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* default interrupt coalescing timer is 64 x 32 = 2048 usecs
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* default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
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*/
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#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
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#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
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#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
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#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
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#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
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#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
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/*
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* This is the threshold value of plcp error rate per 100mSecs. It is
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* used to set and check for the validity of plcp_delta.
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@ -933,9 +900,6 @@ struct iwl_priv {
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/*TODO: remove these pointers - use bus(priv) instead */
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struct iwl_bus *bus; /* bus specific data */
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/* microcode/device supports multiple contexts */
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u8 valid_contexts;
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/* max number of station keys */
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u8 sta_key_max_num;
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@ -1163,7 +1127,7 @@ iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
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#define for_each_context(priv, ctx) \
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for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
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ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
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if (priv->valid_contexts & BIT(ctx->ctxid))
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if (priv->shrd->valid_contexts & BIT(ctx->ctxid))
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static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
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{
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@ -213,6 +213,7 @@ struct iwl_tid_data {
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* @ucode_owner: IWL_OWNERSHIP_*
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* @cmd_queue: command queue number
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* @status: STATUS_*
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* @valid_contexts: microcode/device supports multiple contexts
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* @bus: pointer to the bus layer data
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* @priv: pointer to the upper layer data
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* @hw_params: see struct iwl_hw_params
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@ -233,6 +234,7 @@ struct iwl_shared {
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u8 cmd_queue;
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unsigned long status;
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bool wowlan;
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u8 valid_contexts;
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struct iwl_bus *bus;
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struct iwl_priv *priv;
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@ -387,6 +389,7 @@ void iwl_stop_tx_ba_trans_ready(struct iwl_priv *priv,
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enum iwl_rxon_context_id ctx,
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u8 sta_id, u8 tid);
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void iwl_set_hw_rfkill_state(struct iwl_priv *priv, bool state);
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void iwl_nic_config(struct iwl_priv *priv);
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void iwl_apm_stop(struct iwl_priv *priv);
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int iwl_apm_init(struct iwl_priv *priv);
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void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand);
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@ -408,6 +411,9 @@ static inline void iwl_print_rx_config_cmd(struct iwl_priv *priv, u8 ctxid);
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#define IWL_CMD(x) case x: return #x
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#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
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#define IWL_TRAFFIC_ENTRIES (256)
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#define IWL_TRAFFIC_ENTRY_SIZE (64)
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/*****************************************************
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* DRIVER STATUS FUNCTIONS
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******************************************************/
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@ -436,4 +436,19 @@ static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
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return index & (q->n_window - 1);
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}
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#define IWL_TX_FIFO_BK 0 /* shared */
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#define IWL_TX_FIFO_BE 1
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#define IWL_TX_FIFO_VI 2 /* shared */
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#define IWL_TX_FIFO_VO 3
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#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
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#define IWL_TX_FIFO_BE_IPAN 4
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#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
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#define IWL_TX_FIFO_VO_IPAN 5
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/* re-uses the VO FIFO, uCode will properly flush/schedule */
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#define IWL_TX_FIFO_AUX 5
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#define IWL_TX_FIFO_UNUSED -1
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/* AUX (TX during scan dwell) queue */
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#define IWL_AUX_QUEUE 10
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#endif /* __iwl_trans_int_pcie_h__ */
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@ -71,9 +71,7 @@
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#include "iwl-prph.h"
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#include "iwl-shared.h"
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#include "iwl-eeprom.h"
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/* TODO: the transport layer should not include this */
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#include "iwl-core.h"
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#include "iwl-agn-hw.h"
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static int iwl_trans_rx_alloc(struct iwl_trans *trans)
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{
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@ -638,7 +636,7 @@ static int iwl_nic_init(struct iwl_trans *trans)
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iwl_set_pwr_vmain(trans);
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priv(trans)->cfg->lib->nic_config(priv(trans));
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iwl_nic_config(priv(trans));
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/* Allocate the RX queue, or reset if it is already allocated */
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iwl_rx_init(trans);
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@ -831,8 +829,6 @@ static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
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static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
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{
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const struct queue_to_fifo_ac *queue_to_fifo;
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struct iwl_rxon_context *ctx;
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struct iwl_priv *priv = priv(trans);
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 a;
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@ -900,7 +896,7 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
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iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
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/* map queues to FIFOs */
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if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
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if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
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queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
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else
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queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
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@ -912,8 +908,6 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
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sizeof(trans_pcie->queue_stopped));
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for (i = 0; i < 4; i++)
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atomic_set(&trans_pcie->queue_stop_count[i], 0);
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for_each_context(priv, ctx)
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ctx->last_tx_rejected = false;
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/* reset to 0 to enable all the queue first */
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trans_pcie->txq_ctx_active_msk = 0;
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