ARM: OMAP4: hwmod data: add PRCM and related IP blocks
Add the PRCM, CM, PRM, and related hwmod and associated interconnect data. These IP blocks handle most of the on-chip power, reset, and clock control. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
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Paul Walmsley
parent
a0b5d81356
commit
794b480a37
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@ -292,16 +292,11 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
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* - They still need to be validated with the driver
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* properly adapted to omap_hwmod / omap_device
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*
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* cm_core
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* cm_core_aon
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* debugss
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* efuse_ctrl_cust
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* efuse_ctrl_std
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* mpu_c0
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* mpu_c1
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* prcm_mpu
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* prm
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* scrm
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* usb_phy_cm
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* usim
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*/
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@ -2506,6 +2501,73 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
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.opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
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};
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/*
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* 'prcm' class
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* power and reset manager (part of the prcm infrastructure) + clock manager 2
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* + clock manager 1 (in always on power domain) + local prm in mpu
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*/
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static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
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.name = "prcm",
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};
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/* prcm_mpu */
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static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
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.name = "prcm_mpu",
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.class = &omap44xx_prcm_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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};
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/* cm_core_aon */
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static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
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.name = "cm_core_aon",
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.class = &omap44xx_prcm_hwmod_class,
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.clkdm_name = "cm_clkdm",
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};
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/* cm_core */
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static struct omap_hwmod omap44xx_cm_core_hwmod = {
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.name = "cm_core",
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.class = &omap44xx_prcm_hwmod_class,
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.clkdm_name = "cm_clkdm",
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};
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/* prm */
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static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
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{ .irq = 11 + OMAP44XX_IRQ_GIC_START },
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{ .irq = -1 }
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};
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static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
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{ .name = "rst_global_warm_sw", .rst_shift = 0 },
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{ .name = "rst_global_cold_sw", .rst_shift = 1 },
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};
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static struct omap_hwmod omap44xx_prm_hwmod = {
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.name = "prm",
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.class = &omap44xx_prcm_hwmod_class,
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.clkdm_name = "prm_clkdm",
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.mpu_irqs = omap44xx_prm_irqs,
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.rst_lines = omap44xx_prm_resets,
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.rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
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};
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/*
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* 'scrm' class
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* system clock and reset manager
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*/
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static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
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.name = "scrm",
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};
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/* scrm */
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static struct omap_hwmod omap44xx_scrm_hwmod = {
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.name = "scrm",
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.class = &omap44xx_scrm_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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};
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/*
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* 'sl2if' class
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* shared level 2 memory interface
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@ -5170,6 +5232,96 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
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{
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.pa_start = 0x48243000,
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.pa_end = 0x48243fff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* mpu_private -> prcm_mpu */
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static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
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.master = &omap44xx_mpu_private_hwmod,
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.slave = &omap44xx_prcm_mpu_hwmod,
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.clk = "l3_div_ck",
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.addr = omap44xx_prcm_mpu_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
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{
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.pa_start = 0x4a004000,
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.pa_end = 0x4a004fff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_wkup -> cm_core_aon */
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static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
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.master = &omap44xx_l4_wkup_hwmod,
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.slave = &omap44xx_cm_core_aon_hwmod,
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.clk = "l4_wkup_clk_mux_ck",
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.addr = omap44xx_cm_core_aon_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
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{
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.pa_start = 0x4a008000,
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.pa_end = 0x4a009fff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_cfg -> cm_core */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
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.master = &omap44xx_l4_cfg_hwmod,
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.slave = &omap44xx_cm_core_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_cm_core_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
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{
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.pa_start = 0x4a306000,
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.pa_end = 0x4a307fff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_wkup -> prm */
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static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
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.master = &omap44xx_l4_wkup_hwmod,
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.slave = &omap44xx_prm_hwmod,
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.clk = "l4_wkup_clk_mux_ck",
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.addr = omap44xx_prm_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
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{
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.pa_start = 0x4a30a000,
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.pa_end = 0x4a30a7ff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_wkup -> scrm */
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static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
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.master = &omap44xx_l4_wkup_hwmod,
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.slave = &omap44xx_scrm_hwmod,
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.clk = "l4_wkup_clk_mux_ck",
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.addr = omap44xx_scrm_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_2 -> sl2if */
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static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
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.master = &omap44xx_l3_main_2_hwmod,
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@ -5901,6 +6053,11 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_l4_per__mmc5,
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&omap44xx_l3_main_2__ocmc_ram,
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&omap44xx_l4_cfg__ocp2scp_usb_phy,
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&omap44xx_mpu_private__prcm_mpu,
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&omap44xx_l4_wkup__cm_core_aon,
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&omap44xx_l4_cfg__cm_core,
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&omap44xx_l4_wkup__prm,
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&omap44xx_l4_wkup__scrm,
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&omap44xx_l3_main_2__sl2if,
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&omap44xx_l4_abe__slimbus1,
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&omap44xx_l4_abe__slimbus1_dma,
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