nds32: Power management for nds32
There are three sleep states in nds32: suspend to idle, suspend to standby, suspend to ram In suspend to ram, we use the 'standby' instruction to emulate power management device to hang the system util wakeup source send wakeup events to break the loop. First, we push the general purpose registers and system registers to stack. Second, we translate stack pointer to physical address and store to memory to save the stack pointer. Third, after write back and invalid the cache we hang in 'standby' intruction. When wakeup source trigger wake up events, the loop will be break and resume the system. Signed-off-by: Nick Hu <nickhu@andestech.com> Acked-by: Pavel Machek <pavel@ucw.cz> Acked-by: Greentime Hu <greentime@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com>
This commit is contained in:
Nick Hu
Greentime Hu
parent
cf26edd840
commit
7938e6315c
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@ -93,3 +93,13 @@ endmenu
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menu "Kernel Features"
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source "kernel/Kconfig.hz"
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endmenu
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menu "Power management options"
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config SYS_SUPPORTS_APM_EMULATION
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bool
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config ARCH_SUSPEND_POSSIBLE
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def_bool y
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source "kernel/power/Kconfig"
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endmenu
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2008-2017 Andes Technology Corporation
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#ifndef __ASM_NDS32_SUSPEND_H
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#define __ASM_NDS32_SUSPEND_H
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extern void suspend2ram(void);
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extern void cpu_resume(void);
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extern unsigned long wake_mask;
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#endif
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@ -16,7 +16,7 @@ obj-$(CONFIG_STACKTRACE) += stacktrace.o
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obj-$(CONFIG_OF) += devtree.o
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obj-$(CONFIG_CACHE_L2) += atl2c.o
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obj-$(CONFIG_PERF_EVENTS) += perf_event_cpu.o
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obj-$(CONFIG_PM) += pm.o sleep.o
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extra-y := head.o vmlinux.lds
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obj-y += vdso/
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@ -0,0 +1,79 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2008-2017 Andes Technology Corporation
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/device.h>
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#include <linux/printk.h>
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#include <linux/suspend.h>
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#include <asm/suspend.h>
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#include <nds32_intrinsic.h>
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unsigned int resume_addr;
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unsigned int *phy_addr_sp_tmp;
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static void nds32_suspend2ram(void)
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{
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pgd_t *pgdv;
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pud_t *pudv;
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pmd_t *pmdv;
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pte_t *ptev;
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pgdv = (pgd_t *)__va((__nds32__mfsr(NDS32_SR_L1_PPTB) &
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L1_PPTB_mskBASE)) + pgd_index((unsigned int)cpu_resume);
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pudv = pud_offset(pgdv, (unsigned int)cpu_resume);
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pmdv = pmd_offset(pudv, (unsigned int)cpu_resume);
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ptev = pte_offset_map(pmdv, (unsigned int)cpu_resume);
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resume_addr = ((*ptev) & TLB_DATA_mskPPN)
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| ((unsigned int)cpu_resume & 0x00000fff);
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suspend2ram();
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}
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static void nds32_suspend_cpu(void)
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{
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while (!(__nds32__mfsr(NDS32_SR_INT_PEND) & wake_mask))
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__asm__ volatile ("standby no_wake_grant\n\t");
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}
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static int nds32_pm_valid(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_ON:
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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return 1;
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default:
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return 0;
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}
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}
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static int nds32_pm_enter(suspend_state_t state)
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{
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pr_debug("%s:state:%d\n", __func__, state);
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switch (state) {
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case PM_SUSPEND_STANDBY:
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nds32_suspend_cpu();
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return 0;
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case PM_SUSPEND_MEM:
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nds32_suspend2ram();
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return 0;
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default:
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return -EINVAL;
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}
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}
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static const struct platform_suspend_ops nds32_pm_ops = {
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.valid = nds32_pm_valid,
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.enter = nds32_pm_enter,
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};
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static int __init nds32_pm_init(void)
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{
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pr_debug("Enter %s\n", __func__);
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suspend_set_ops(&nds32_pm_ops);
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return 0;
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}
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late_initcall(nds32_pm_init);
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@ -0,0 +1,129 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2017 Andes Technology Corporation */
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#include <asm/memory.h>
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.data
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.global sp_tmp
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sp_tmp:
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.long
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.text
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.globl suspend2ram
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.globl cpu_resume
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suspend2ram:
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pushm $r0, $r31
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#if defined(CONFIG_HWZOL)
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mfusr $r0, $lc
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mfusr $r1, $le
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mfusr $r2, $lb
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#endif
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mfsr $r3, $mr0
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mfsr $r4, $mr1
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mfsr $r5, $mr4
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mfsr $r6, $mr6
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mfsr $r7, $mr7
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mfsr $r8, $mr8
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mfsr $r9, $ir0
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mfsr $r10, $ir1
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mfsr $r11, $ir2
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mfsr $r12, $ir3
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mfsr $r13, $ir9
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mfsr $r14, $ir10
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mfsr $r15, $ir12
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mfsr $r16, $ir13
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mfsr $r17, $ir14
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mfsr $r18, $ir15
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pushm $r0, $r19
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tlbop FlushAll
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isb
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// transfer $sp from va to pa
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sethi $r0, hi20(PAGE_OFFSET)
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ori $r0, $r0, lo12(PAGE_OFFSET)
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movi $r2, PHYS_OFFSET
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sub $r1, $sp, $r0
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add $r2, $r1, $r2
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// store pa($sp) to sp_tmp
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sethi $r1, hi20(sp_tmp)
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swi $r2, [$r1 + lo12(sp_tmp)]
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pushm $r16, $r25
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pushm $r29, $r30
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#ifdef CONFIG_CACHE_L2
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jal dcache_wb_all_level
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#else
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jal cpu_dcache_wb_all
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#endif
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popm $r29, $r30
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popm $r16, $r25
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// get wake_mask and loop in standby
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la $r1, wake_mask
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lwi $r1, [$r1]
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self_loop:
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standby wake_grant
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mfsr $r2, $ir15
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and $r2, $r1, $r2
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beqz $r2, self_loop
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// set ipc to resume address
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la $r1, resume_addr
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lwi $r1, [$r1]
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mtsr $r1, $ipc
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isb
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// reset psw, turn off the address translation
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li $r2, 0x7000a
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mtsr $r2, $ipsw
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isb
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iret
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cpu_resume:
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// translate the address of sp_tmp variable to pa
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la $r1, sp_tmp
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sethi $r0, hi20(PAGE_OFFSET)
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ori $r0, $r0, lo12(PAGE_OFFSET)
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movi $r2, PHYS_OFFSET
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sub $r1, $r1, $r0
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add $r1, $r1, $r2
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// access the sp_tmp to get stack pointer
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lwi $sp, [$r1]
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popm $r0, $r19
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#if defined(CONFIG_HWZOL)
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mtusr $r0, $lb
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mtusr $r1, $lc
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mtusr $r2, $le
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#endif
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mtsr $r3, $mr0
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mtsr $r4, $mr1
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mtsr $r5, $mr4
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mtsr $r6, $mr6
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mtsr $r7, $mr7
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mtsr $r8, $mr8
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// set original psw to ipsw
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mtsr $r9, $ir1
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mtsr $r11, $ir2
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mtsr $r12, $ir3
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// set ipc to RR
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la $r13, RR
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mtsr $r13, $ir9
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mtsr $r14, $ir10
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mtsr $r15, $ir12
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mtsr $r16, $ir13
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mtsr $r17, $ir14
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mtsr $r18, $ir15
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popm $r0, $r31
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isb
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iret
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RR:
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ret
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@ -10,6 +10,8 @@
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#include <linux/irqchip.h>
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#include <nds32_intrinsic.h>
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unsigned long wake_mask;
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static void ativic32_ack_irq(struct irq_data *data)
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{
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__nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2);
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@ -27,11 +29,40 @@ static void ativic32_unmask_irq(struct irq_data *data)
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__nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2);
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}
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static int nointc_set_wake(struct irq_data *data, unsigned int on)
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{
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unsigned long int_mask = __nds32__mfsr(NDS32_SR_INT_MASK);
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static unsigned long irq_orig_bit;
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u32 bit = 1 << data->hwirq;
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if (on) {
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if (int_mask & bit)
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__assign_bit(data->hwirq, &irq_orig_bit, true);
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else
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__assign_bit(data->hwirq, &irq_orig_bit, false);
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__assign_bit(data->hwirq, &int_mask, true);
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__assign_bit(data->hwirq, &wake_mask, true);
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} else {
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if (!(irq_orig_bit & bit))
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__assign_bit(data->hwirq, &int_mask, false);
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__assign_bit(data->hwirq, &wake_mask, false);
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__assign_bit(data->hwirq, &irq_orig_bit, false);
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}
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__nds32__mtsr_dsb(int_mask, NDS32_SR_INT_MASK);
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return 0;
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}
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static struct irq_chip ativic32_chip = {
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.name = "ativic32",
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.irq_ack = ativic32_ack_irq,
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.irq_mask = ativic32_mask_irq,
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.irq_unmask = ativic32_unmask_irq,
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.irq_set_wake = nointc_set_wake,
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};
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static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 };
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