ASoC: rt5645: add API to select ASRC clock source
This patch defines an API to select the clock source for specified filters. Signed-off-by: Fang, Yang A <yang.a.fang@intel.com> Acked-by: Kevin Strasser <kevin.strasser@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Fang, Yang A
Mark Brown
parent
5c4ca99df7
commit
79080a8b42
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@ -613,6 +613,87 @@ static int is_using_asrc(struct snd_soc_dapm_widget *source,
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}
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/**
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* rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
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* @codec: SoC audio codec device.
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* @filter_mask: mask of filters.
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* @clk_src: clock source
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*
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* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
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* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
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* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
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* ASRC function will track i2s clock and generate a corresponding system clock
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* for codec. This function provides an API to select the clock source for a
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* set of filters specified by the mask. And the codec driver will turn on ASRC
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* for these filters if ASRC is selected as their clock source.
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*/
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int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
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unsigned int filter_mask, unsigned int clk_src)
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{
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unsigned int asrc2_mask = 0;
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unsigned int asrc2_value = 0;
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unsigned int asrc3_mask = 0;
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unsigned int asrc3_value = 0;
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switch (clk_src) {
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case RT5645_CLK_SEL_SYS:
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case RT5645_CLK_SEL_I2S1_ASRC:
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case RT5645_CLK_SEL_I2S2_ASRC:
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case RT5645_CLK_SEL_SYS2:
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break;
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default:
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return -EINVAL;
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}
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if (filter_mask & RT5645_DA_STEREO_FILTER) {
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asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
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asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
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| (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
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}
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if (filter_mask & RT5645_DA_MONO_L_FILTER) {
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asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
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asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
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| (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
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}
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if (filter_mask & RT5645_DA_MONO_R_FILTER) {
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asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
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asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
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| (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
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}
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if (filter_mask & RT5645_AD_STEREO_FILTER) {
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asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
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asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
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| (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
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}
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if (filter_mask & RT5645_AD_MONO_L_FILTER) {
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asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
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asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
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| (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
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}
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if (filter_mask & RT5645_AD_MONO_R_FILTER) {
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asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
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asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
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| (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
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}
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if (asrc2_mask)
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snd_soc_update_bits(codec, RT5645_ASRC_2,
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asrc2_mask, asrc2_value);
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if (asrc3_mask)
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snd_soc_update_bits(codec, RT5645_ASRC_3,
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asrc3_mask, asrc3_value);
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return 0;
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}
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EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
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/* Digital Mixer */
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static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
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SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
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@ -1120,50 +1120,27 @@
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#define RT5645_DMIC_2_M_NOR (0x0 << 8)
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#define RT5645_DMIC_2_M_ASYN (0x1 << 8)
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/* ASRC clock source selection (0x84, 0x85) */
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#define RT5645_CLK_SEL_SYS (0x0)
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#define RT5645_CLK_SEL_I2S1_ASRC (0x1)
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#define RT5645_CLK_SEL_I2S2_ASRC (0x2)
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#define RT5645_CLK_SEL_SYS2 (0x5)
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/* ASRC Control 2 (0x84) */
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#define RT5645_MDA_L_M_MASK (0x1 << 15)
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#define RT5645_MDA_L_M_SFT 15
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#define RT5645_MDA_L_M_NOR (0x0 << 15)
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#define RT5645_MDA_L_M_ASYN (0x1 << 15)
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#define RT5645_MDA_R_M_MASK (0x1 << 14)
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#define RT5645_MDA_R_M_SFT 14
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#define RT5645_MDA_R_M_NOR (0x0 << 14)
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#define RT5645_MDA_R_M_ASYN (0x1 << 14)
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#define RT5645_MAD_L_M_MASK (0x1 << 13)
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#define RT5645_MAD_L_M_SFT 13
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#define RT5645_MAD_L_M_NOR (0x0 << 13)
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#define RT5645_MAD_L_M_ASYN (0x1 << 13)
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#define RT5645_MAD_R_M_MASK (0x1 << 12)
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#define RT5645_MAD_R_M_SFT 12
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#define RT5645_MAD_R_M_NOR (0x0 << 12)
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#define RT5645_MAD_R_M_ASYN (0x1 << 12)
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#define RT5645_ADC_M_MASK (0x1 << 11)
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#define RT5645_ADC_M_SFT 11
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#define RT5645_ADC_M_NOR (0x0 << 11)
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#define RT5645_ADC_M_ASYN (0x1 << 11)
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#define RT5645_STO_DAC_M_MASK (0x1 << 5)
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#define RT5645_STO_DAC_M_SFT 5
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#define RT5645_STO_DAC_M_NOR (0x0 << 5)
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#define RT5645_STO_DAC_M_ASYN (0x1 << 5)
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#define RT5645_I2S1_R_D_MASK (0x1 << 4)
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#define RT5645_I2S1_R_D_SFT 4
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#define RT5645_I2S1_R_D_DIS (0x0 << 4)
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#define RT5645_I2S1_R_D_EN (0x1 << 4)
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#define RT5645_I2S2_R_D_MASK (0x1 << 3)
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#define RT5645_I2S2_R_D_SFT 3
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#define RT5645_I2S2_R_D_DIS (0x0 << 3)
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#define RT5645_I2S2_R_D_EN (0x1 << 3)
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#define RT5645_PRE_SCLK_MASK (0x3)
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#define RT5645_PRE_SCLK_SFT 0
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#define RT5645_PRE_SCLK_512 (0x0)
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#define RT5645_PRE_SCLK_1024 (0x1)
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#define RT5645_PRE_SCLK_2048 (0x2)
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#define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12)
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#define RT5645_DA_STO_CLK_SEL_SFT 12
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#define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8)
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#define RT5645_DA_MONOL_CLK_SEL_SFT 8
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#define RT5645_DA_MONOR_CLK_SEL_MASK (0xf << 4)
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#define RT5645_DA_MONOR_CLK_SEL_SFT 4
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#define RT5645_AD_STO1_CLK_SEL_MASK (0xf << 0)
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#define RT5645_AD_STO1_CLK_SEL_SFT 0
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/* ASRC Control 3 (0x85) */
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#define RT5645_I2S1_RATE_MASK (0xf << 12)
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#define RT5645_I2S1_RATE_SFT 12
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#define RT5645_I2S2_RATE_MASK (0xf << 8)
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#define RT5645_I2S2_RATE_SFT 8
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#define RT5645_AD_MONOL_CLK_SEL_MASK (0xf << 4)
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#define RT5645_AD_MONOL_CLK_SEL_SFT 4
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#define RT5645_AD_MONOR_CLK_SEL_MASK (0xf << 0)
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#define RT5645_AD_MONOR_CLK_SEL_SFT 0
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/* ASRC Control 4 (0x89) */
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#define RT5645_I2S1_PD_MASK (0x7 << 12)
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@ -2189,6 +2166,19 @@ enum {
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CODEC_TYPE_RT5650,
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};
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/* filter mask */
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enum {
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RT5645_DA_STEREO_FILTER = 0x1,
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RT5645_DA_MONO_L_FILTER = (0x1 << 1),
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RT5645_DA_MONO_R_FILTER = (0x1 << 2),
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RT5645_AD_STEREO_FILTER = (0x1 << 3),
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RT5645_AD_MONO_L_FILTER = (0x1 << 4),
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RT5645_AD_MONO_R_FILTER = (0x1 << 5),
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};
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int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
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unsigned int filter_mask, unsigned int clk_src);
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struct rt5645_priv {
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struct snd_soc_codec *codec;
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struct rt5645_platform_data pdata;
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