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clk: imx25: Remove osc clock from driver 

The 'osc' clock is already initialized by the fixed clock defined in
imx25.dtsi. The imx25 clock driver tries to add this clock for a second
time and fails with -EEXIST:
	i.MX clk 1: register failed with -17

As the clock is already properly setup in DT with a different driver, we
can completely remove the handling in the imx25 clock driver.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Markus Pargmann 2015-11-24 12:17:58 +01:00 committed by Shawn Guo
parent 8005c49d9a
commit 78ae71ac88
1 changed files with 2 additions and 16 deletions
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18
drivers/clk/imx/clk-imx25.c
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@ -96,13 +96,11 @@ static struct clk ** const uart_clks[] __initconst = {
NULL NULL
}; };
static int __init __mx25_clocks_init(unsigned long osc_rate, static int __init __mx25_clocks_init(void __iomem *ccm_base)
void __iomem *ccm_base)
{ {
BUG_ON(!ccm_base); BUG_ON(!ccm_base);
clk[dummy] = imx_clk_fixed("dummy", 0); clk[dummy] = imx_clk_fixed("dummy", 0);
clk[osc] = imx_clk_fixed("osc", osc_rate);
clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL));
clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL));
clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
@ -250,22 +248,10 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
static void __init mx25_clocks_init_dt(struct device_node *np) static void __init mx25_clocks_init_dt(struct device_node *np)
{ {
struct device_node *refnp;
unsigned long osc_rate = 24000000;
void __iomem *ccm; void __iomem *ccm;
/* retrieve the freqency of fixed clocks from device tree */
for_each_compatible_node(refnp, NULL, "fixed-clock") {
u32 rate;
if (of_property_read_u32(refnp, "clock-frequency", &rate))
continue;
if (of_device_is_compatible(refnp, "fsl,imx-osc"))
osc_rate = rate;
}
ccm = of_iomap(np, 0); ccm = of_iomap(np, 0);
__mx25_clocks_init(osc_rate, ccm); __mx25_clocks_init(ccm);
clk_data.clks = clk; clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk); clk_data.clk_num = ARRAY_SIZE(clk);