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ARM: DT updates for v4.10 

Lots of changes as usual, so I'm trying to be brief here. Most of the
 new hardware support has the respective driver changes merged through
 other trees or has had it available for a while, so this is where things
 come together.
 
 We get a DT descriptions for a couple of new SoCs, all of them variants
 of other chips we already support, and usually coming with a new
 evaluation board:
 
 - Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
 - Qualcomm MDM9615 LTE baseband
 - NXP imx6ull, the latest and smallest i.MX6 application processor variant
 - Renesas RZ/G (r8a7743 and r8a7745) application processors
 - Rockchip PX3, a variant of the rk3188 chip used in Android tablets
 - Rockchip rk1108 single-core application processor
 - ST stm32f746 Cortex-M7 based microcontroller
 - TI DRA71x automotive processors
 
 These are commercially available consumer platforms we now support:
 - Motorola Droid 4 (xt894) mobile phone
 - Rikomagic MK808 Android TV stick based on Rockchips rx3066
 - Cloud Engines PogoPlug v3 based on OX820
 - Various Broadcom based wireless devices:
   - Netgear R8500 router
   - Tenda AC9 router
   - TP-LINK Archer C9 V1
   - Luxul XAP-1510 Access point
 - Turris Omnia open hardware router based on Armada 385
 
 And a couple of new boards targeted at developers, makers
 or industrial integration:
 - Macnica Sodia development platform for Altera socfpga (Cyclone V)
 - MicroZed board based on Xilinx Zynq FPGA platforms
 - TOPEET itop/elite based on exynos4412
 - WP8548 MangOH Open Hardware platform for IOT, based on
   Qualcomm MDM9615
 - NextThing CHIP Pro gadget
 - NanoPi M1 development board
 - AM571x-IDK industrial board based on TI AM5718
 - i.MX6SX UDOO Neo
 - Boundary Devices Nitrogen6_SOM2 (i.MX6)
 - Engicam i.CoreM6
 - Grinn i.MX6UL liteSOM/liteBoard
 - Toradex Colibri iMX6 module
 
 Other changes:
 - added peripherals on renesas, davinci, stm32f429, uniphier, sti,
   mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
   mvebu, allwinner, broadcom, exynos, zynq
 
 - Continued fixes for W=1 dtc warnings
 
 - The old STiH415/416 SoC support gets removed, these never made it into
   products and have served their purpose in the kernel as a template
   for teh newer chips from ST
 
 - The exynos4415 dtsi file is removed as nothing uses it.
 
 - Intel PXA25x can now be booted using devicetree
 
 Conflicts:
 arch/arm/boot/dts/r8a*.dtsi: a node was added
 the clk tree, keep both sides and watch out for git
 dropping the required '};' at the end of each side.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Arnd Bergmann:
 "Lots of changes as usual, so I'm trying to be brief here. Most of the
  new hardware support has the respective driver changes merged through
  other trees or has had it available for a while, so this is where
  things come together.

  We get a DT descriptions for a couple of new SoCs, all of them
  variants of other chips we already support, and usually coming with a
  new evaluation board:

   - Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
   - Qualcomm MDM9615 LTE baseband
   - NXP imx6ull, the latest and smallest i.MX6 application processor variant
   - Renesas RZ/G (r8a7743 and r8a7745) application processors
   - Rockchip PX3, a variant of the rk3188 chip used in Android tablets
   - Rockchip rk1108 single-core application processor
   - ST stm32f746 Cortex-M7 based microcontroller
   - TI DRA71x automotive processors

  These are commercially available consumer platforms we now support:

   - Motorola Droid 4 (xt894) mobile phone
   - Rikomagic MK808 Android TV stick based on Rockchips rx3066
   - Cloud Engines PogoPlug v3 based on OX820
   - Various Broadcom based wireless devices:
      - Netgear R8500 router
      - Tenda AC9 router
      - TP-LINK Archer C9 V1
      - Luxul XAP-1510 Access point
   - Turris Omnia open hardware router based on Armada 385

  And a couple of new boards targeted at developers, makers or
  industrial integration:

   - Macnica Sodia development platform for Altera socfpga (Cyclone V)
   - MicroZed board based on Xilinx Zynq FPGA platforms
   - TOPEET itop/elite based on exynos4412
   - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615
   - NextThing CHIP Pro gadget
   - NanoPi M1 development board
   - AM571x-IDK industrial board based on TI AM5718
   - i.MX6SX UDOO Neo
   - Boundary Devices Nitrogen6_SOM2 (i.MX6)
   - Engicam i.CoreM6
   - Grinn i.MX6UL liteSOM/liteBoard
   - Toradex Colibri iMX6 module

  Other changes:

   - added peripherals on renesas, davinci, stm32f429, uniphier, sti,
     mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
     mvebu, allwinner, broadcom, exynos, zynq

   - Continued fixes for W=1 dtc warnings

   - The old STiH415/416 SoC support gets removed, these never made it
     into products and have served their purpose in the kernel as a
     template for teh newer chips from ST

   - The exynos4415 dtsi file is removed as nothing uses it.

   - Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits)
  arm: dts: zynq: Add MicroZed board support
  ARM: dts: da850: enable high speed for mmc
  ARM: dts: da850: Add node for pullup/pulldown pinconf
  ARM: dts: da850: enable memctrl and mstpri nodes per board
  ARM: dts: da850-lcdk: Add ethernet0 alias to DT
  ARM: dts: artpec: add pcie support
  ARM: dts: add support for Turris Omnia
  devicetree: Add vendor prefix for CZ.NIC
  ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node
  ARM: dts: berlin2q-marvell-dmp: fix regulators' name
  ARM: dts: Add xo to sdhc clock node on qcom platforms
  ARM: dts: r8a7794: Add device node for PRR
  ARM: dts: r8a7793: Add device node for PRR
  ARM: dts: r8a7792: Add device node for PRR
  ARM: dts: r8a7791: Add device node for PRR
  ARM: dts: r8a7790: Add device node for PRR
  ARM: dts: r8a7779: Add device node for PRR
  ARM: dts: r8a73a4: Add device node for PRR
  ARM: dts: sk-rzg1e: add Ether support
  ARM: dts: sk-rzg1e: initial device tree
  ...
This commit is contained in:
Linus Torvalds 2016-12-15 15:50:24 -08:00
parent 3bd776bbda 8237c0b957
commit 786a72d791
420 changed files with 18368 additions and 8093 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/cpus.txt
View File

@ -178,6 +178,7 @@ nodes to be present and contain the properties described below.
"marvell,pj4b"
"marvell,sheeva-v5"
"nvidia,tegra132-denver"
"nvidia,tegra186-denver"
"qcom,krait"
"qcom,kryo"
"qcom,scorpion"

3
Documentation/devicetree/bindings/arm/omap/omap.txt
View File

@ -178,6 +178,9 @@ Boards:
- AM5728 IDK
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
- AM5718 IDK
compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"
- DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"

5
Documentation/devicetree/bindings/arm/oxnas.txt
View File

@ -5,5 +5,10 @@ Boards with the OX810SE SoC shall have the following properties:
Required root node property:
compatible: "oxsemi,ox810se"
Boards with the OX820 SoC shall have the following properties:
Required root node property:
compatible: "oxsemi,ox820"
Board compatible values:
- "wd,mbwe" (OX810SE)
- "cloudengines,pogoplugv3" (OX820)

1
Documentation/devicetree/bindings/arm/qcom.txt
View File

@ -22,6 +22,7 @@ The 'SoC' element must be one of the following strings:
msm8916
msm8974
msm8996
mdm9615
The 'board' element must be one of the following strings:

4
Documentation/devicetree/bindings/arm/rockchip.txt
View File

@ -25,6 +25,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "radxa,rock2-square", "rockchip,rk3288";
- Rikomagic MK808 v1 board:
Required root node properties:
- compatible = "rikomagic,mk808", "rockchip,rk3066a";
- Firefly Firefly-RK3288 board:
Required root node properties:
- compatible = "firefly,firefly-rk3288", "rockchip,rk3288";

3
Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
View File

@ -22,6 +22,9 @@ Required root node properties:
* FriendlyARM
- "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
TINY4412 board.
* TOPEET
- "topeet,itop4412-elite" - for Exynos4412-based TOPEET
Elite base board.
* Google
- "google,pi" - for Exynos5800-based Google Peach Pi

12
Documentation/devicetree/bindings/arm/swir.txt Normal file
View File

@ -0,0 +1,12 @@
Sierra Wireless Modules device tree bindings
--------------------------------------------
Supported Modules :
- WP8548 : Includes MDM9615 and PM8018 in a module
Sierra Wireless modules shall have the following properties :
Required root node property
- compatible: "swir,wp8548" for the WP8548 CF3 Module
Board compatible values:
- "swir,mangoh-green-wp8548" for the mangOH green board with the WP8548 module

15
Documentation/devicetree/bindings/ata/ahci-st.txt
View File

@ -18,21 +18,6 @@ Optional properties:
Example:
/* Example for stih416 */
sata0: sata@fe380000 {
compatible = "st,ahci";
reg = <0xfe380000 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
interrupt-names = "hostc";
phys = <&phy_port0 PHY_TYPE_SATA>;
phy-names = "ahci_phy";
resets = <&powerdown STIH416_SATA0_POWERDOWN>,
<&softreset STIH416_SATA0_SOFTRESET>;
reset-names = "pwr-dwn", "sw-rst";
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ahci_clk";
};
/* Example for stih407 family silicon */
sata0: sata@9b20000 {
compatible = "st,ahci";

6
Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
View File

@ -17,7 +17,9 @@ Required properties:
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be one. It is the pin number.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify flags. See gpio.txt for possible
values.
Example for a MMP platform:
@ -27,7 +29,7 @@ Example for a MMP platform:
interrupts = <49>;
interrupt-names = "gpio_mux";
gpio-controller;
#gpio-cells = <1>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};

2
Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt
View File

@ -12,7 +12,7 @@ Required properties:
Example:
mailbox: mailbox@7e00b800 {
mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;

1
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
View File

@ -13,6 +13,7 @@ Required Properties:
- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
before RK3288
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399

3
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
View File

@ -7,6 +7,9 @@ Required properties:
- reg : offset and length of the register set for the mux registers
- #pinctrl-cells : number of cells in addition to the index, set to 1
for pinctrl-single,pins and 2 for pinctrl-single,bits
- pinctrl-single,register-width : pinmux register access width in bits
- pinctrl-single,function-mask : mask of allowed pinmux function bits

12
Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
View File

@ -16,15 +16,14 @@ Please refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "st,<chip>-powerdown"
ex: "st,stih415-powerdown", "st,stih416-powerdown"
- compatible: Should be "st,stih407-powerdown"
- #reset-cells: 1, see below
example:
powerdown: powerdown-controller {
compatible = "st,stih407-powerdown";
#reset-cells = <1>;
compatible = "st,stih415-powerdown";
};
@ -37,11 +36,10 @@ index specifying which channel to use, as described in reset.txt
example:
usb1: usb@fe200000 {
resets = <&powerdown STIH41X_USB1_POWERDOWN>;
st_dwc3: dwc3@8f94000 {
resets = <&powerdown STIH407_USB3_POWERDOWN>,
};
Macro definitions for the supported reset channels can be found in:
include/dt-bindings/reset/stih415-resets.h
include/dt-bindings/reset/stih416-resets.h
include/dt-bindings/reset/stih407-resets.h

8
Documentation/devicetree/bindings/reset/st,sti-softreset.txt
View File

@ -15,15 +15,14 @@ Please refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "st,<chip>-softreset" example:
"st,stih415-softreset" or "st,stih416-softreset";
- compatible: Should be st,stih407-softreset";
- #reset-cells: 1, see below
example:
softreset: softreset-controller {
#reset-cells = <1>;
compatible = "st,stih415-softreset";
compatible = "st,stih407-softreset";
};
@ -42,5 +41,4 @@ example:
Macro definitions for the supported reset channels can be found in:
include/dt-bindings/reset/stih415-resets.h
include/dt-bindings/reset/stih416-resets.h
include/dt-bindings/reset/stih407-resets.h

2
Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
View File

@ -10,7 +10,7 @@ Required properties:
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- serial
- dmas : Must contain an entry for each entry in clock-names.
- dmas : Must contain an entry for each entry in dma-names.
See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
- rx

13
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
View File

@ -9,17 +9,20 @@ domain control.
The driver implements the Generic PM domain bindings described in
power/power_domain.txt. It provides the power domains defined in
include/dt-bindings/power/mt8173-power.h.
include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
Required properties:
- compatible: Must be "mediatek,mt8173-scpsys"
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
- clock, clock-names: clocks according to the common clock binding.
The clocks needed "mm", "mfg", "venc" and "venc_lt".
These are the clocks which hardware needs to be enabled
before enabling certain power domains.
These are clocks which hardware needs to be
enabled before enabling certain power domains.
Required clocks for MT2701: "mm", "mfg", "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:
- vdec-supply: Power supply for the vdec power domain

17
Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt Normal file
View File

@ -0,0 +1,17 @@
Binding for Thermal Sensor driver for BCM2835 SoCs.
Required parameters:
-------------------
compatible: should be one of: "brcm,bcm2835-thermal",
"brcm,bcm2836-thermal" or "brcm,bcm2837-thermal"
reg: Address range of the thermal registers.
clocks: Phandle of the clock used by the thermal sensor.
Example:
thermal: thermal@7e212000 {
compatible = "brcm,bcm2835-thermal";
reg = <0x7e212000 0x8>;
clocks = <&clocks BCM2835_CLOCK_TSENS>;
};

28
Documentation/devicetree/bindings/thermal/st-thermal.txt
View File

@ -3,17 +3,8 @@ Binding for Thermal Sensor driver for STMicroelectronics STi series of SoCs.
Required parameters:
-------------------
compatible : st,<SoC>-<module>-thermal; should be one of:
"st,stih415-sas-thermal",
"st,stih415-mpe-thermal",
"st,stih416-sas-thermal"
"st,stih416-mpe-thermal"
"st,stid127-thermal" or
"st,stih407-thermal"
according to the SoC type (stih415, stih416, stid127, stih407)
and module type (sas or mpe). On stid127 & stih407 there is only
one die/module, so there is no module type in the compatible
string.
compatible : Should be "st,stih407-thermal"
clock-names : Should be "thermal".
See: Documentation/devicetree/bindings/resource-names.txt
clocks : Phandle of the clock used by the thermal sensor.
@ -25,18 +16,17 @@ Optional parameters:
reg : For non-sysconf based sensors, this should be the physical base
address and length of the sensor's registers.
interrupts : Standard way to define interrupt number.
Interrupt is mandatory to be defined when compatible is
"stih416-mpe-thermal".
NB: For thermal sensor's for which no interrupt has been
defined, a polling delay of 1000ms will be used to read the
temperature from device.
Example:
temp1@fdfe8000 {
compatible = "st,stih416-mpe-thermal";
reg = <0xfdfe8000 0x10>;
clock-names = "thermal";
clocks = <&clk_m_mpethsens>;
interrupts = <GIC_SPI 23 IRQ_TYPE_NONE>;
temp0@91a0000 {
compatible = "st,stih407-thermal";
reg = <0x91a0000 0x28>;
clock-names = "thermal";
clocks = <&CLK_SYSIN>;
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
st,passive_cooling_temp = <110>;
};

10
Documentation/devicetree/bindings/usb/atmel-usb.txt
View File

@ -6,9 +6,9 @@ Required properties:
- compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
used in host mode.
- reg: Address and length of the register set for the device
- interrupts: Should contain ehci interrupt
- interrupts: Should contain ohci interrupt
- clocks: Should reference the peripheral, host and system clocks
- clock-names: Should contains two strings
- clock-names: Should contain three strings
"ohci_clk" for the peripheral clock
"hclk" for the host clock
"uhpck" for the system clock
@ -35,7 +35,7 @@ Required properties:
- reg: Address and length of the register set for the device
- interrupts: Should contain ehci interrupt
- clocks: Should reference the peripheral and the UTMI clocks
- clock-names: Should contains two strings
- clock-names: Should contain two strings
"ehci_clk" for the peripheral clock
"usb_clk" for the UTMI clock
@ -58,7 +58,7 @@ Required properties:
- reg: Address and length of the register set for the device
- interrupts: Should contain macb interrupt
- clocks: Should reference the peripheral and the AHB clocks
- clock-names: Should contains two strings
- clock-names: Should contain two strings
"pclk" for the peripheral clock
"hclk" for the AHB clock
@ -85,7 +85,7 @@ Required properties:
- reg: Address and length of the register set for the device
- interrupts: Should contain usba interrupt
- clocks: Should reference the peripheral and host clocks
- clock-names: Should contains two strings
- clock-names: Should contain two strings
"pclk" for the peripheral clock
"hclk" for the host clock
- ep childnode: To specify the number of endpoints and their properties.

2
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -70,6 +70,7 @@ creative Creative Technology Ltd
crystalfontz Crystalfontz America, Inc.
cubietech Cubietech, Ltd.
cypress Cypress Semiconductor Corporation
cznic CZ.NIC, z.s.p.o.
dallas Maxim Integrated Products (formerly Dallas Semiconductor)
davicom DAVICOM Semiconductor, Inc.
delta Delta Electronics, Inc.
@ -242,6 +243,7 @@ realtek Realtek Semiconductor Corp.
renesas Renesas Electronics Corporation
richtek Richtek Technology Corporation
ricoh Ricoh Co. Ltd.
rikomagic Rikomagic Tech Corp. Ltd
rockchip Fuzhou Rockchip Electronics Co., Ltd
samsung Samsung Semiconductor
samtec Samtec/Softing company

5
MAINTAINERS
View File

@ -1503,8 +1503,9 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-oxnas@lists.tuxfamily.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-oxnas/
F: arch/arm/boot/dts/oxnas*
F: arch/arm/boot/dts/ox8*.dtsi
F: arch/arm/boot/dts/wd-mbwe.dts
F: arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
N: oxnas
ARM/Mediatek RTC DRIVER
@ -1805,9 +1806,7 @@ F: drivers/media/rc/st_rc.c
F: drivers/media/platform/sti/c8sectpfe/
F: drivers/mmc/host/sdhci-st.c
F: drivers/phy/phy-miphy28lp.c
F: drivers/phy/phy-miphy365x.c
F: drivers/phy/phy-stih407-usb.c
F: drivers/phy/phy-stih41x-usb.c
F: drivers/pinctrl/pinctrl-st.c
F: drivers/remoteproc/st_remoteproc.c
F: drivers/remoteproc/st_slim_rproc.c

50
arch/arm/boot/dts/Makefile
View File

@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4708-asus-rt-ac56u.dtb \
bcm4708-asus-rt-ac68u.dtb \
bcm4708-buffalo-wzr-1750dhp.dtb \
bcm4708-luxul-xap-1510.dtb \
bcm4708-luxul-xwc-1000.dtb \
bcm4708-netgear-r6250.dtb \
bcm4708-netgear-r6300-v2.dtb \
@ -86,11 +87,16 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-buffalo-wxr-1900dhp.dtb \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb \
bcm4709-tplink-archer-c9-v1.dtb \
bcm47094-dlink-dir-885l.dtb \
bcm47094-luxul-xwr-3100.dtb \
bcm47094-netgear-r8500.dtb \
bcm94708.dtb \
bcm94709.dtb \
bcm953012er.dtb \
bcm953012k.dtb
dtb-$(CONFIG_ARCH_BCM_53573) += \
bcm47189-tenda-ac9.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb
dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
@ -136,6 +142,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
exynos4210-universal_c210.dtb \
exynos4412-itop-elite.dtb \
exynos4412-odroidu3.dtb \
exynos4412-odroidx.dtb \
exynos4412-odroidx2.dtb \
@ -330,6 +337,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-aristainetos_7.dtb \
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
imx6dl-colibri-eval-v3.dtb \
imx6dl-cubox-i.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-gw51xx.dtb \
@ -340,6 +348,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw552x.dtb \
imx6dl-gw553x.dtb \
imx6dl-hummingboard.dtb \
imx6dl-icore.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \
@ -381,10 +390,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw553x.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-marsboard.dtb \
imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \
imx6q-nitrogen6_som2.dtb \
imx6q-novena.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-rex-pro.dtb \
@ -416,14 +427,19 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb-sai.dtb \
imx6sx-sdb.dtb
imx6sx-sdb.dtb \
imx6sx-udoo-neo-basic.dtb \
imx6sx-udoo-neo-extended.dtb \
imx6sx-udoo-neo-full.dtb
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-geam-kit.dtb \
imx6ul-liteboard.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-eval-v3.dtb \
@ -561,6 +577,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-sl50.dtb \
am335x-wega-rdk.dtb
dtb-$(CONFIG_ARCH_OMAP4) += \
omap4-droid4-xt894.dtb \
omap4-duovero-parlor.dtb \
omap4-kc1.dtb \
omap4-panda.dtb \
@ -588,15 +605,18 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
am57xx-cl-som-am57x.dtb \
am57xx-sbc-am57x.dtb \
am572x-idk.dtb \
am571x-idk.dtb \
dra7-evm.dtb \
dra72-evm.dtb \
dra72-evm-revc.dtb
dra72-evm-revc.dtb \
dra71-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-kuroboxpro.dtb \
orion5x-lacie-d2-network.dtb \
orion5x-lacie-ethernet-disk-mini-v2.dtb \
orion5x-linkstation-lsgl.dtb \
orion5x-linkstation-lswtgl.dtb \
orion5x-lschl.dtb \
orion5x-lswsgl.dtb \
orion5x-maxtor-shared-storage-2.dtb \
orion5x-netgear-wnr854t.dtb \
@ -604,7 +624,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_OXNAS) += \
wd-mbwe.dtb
wd-mbwe.dtb \
cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-arrow-sd-600eval.dtb \
@ -620,7 +641,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \
qcom-msm8974-sony-xperia-honami.dtb
qcom-msm8974-sony-xperia-honami.dtb \
qcom-mdm9615-wp8548-mangoh-green.dtb
dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb \
arm-realview-pb11mp.dtb \
@ -635,11 +657,14 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pba8.dtb \
arm-realview-pbx-a9.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk1108-evb.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-mk808.dtb \
rk3066a-rayeager.dtb \
rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
rk3229-evb.dtb \
@ -677,6 +702,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r7s72100-rskrza1.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
@ -690,12 +717,14 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_de0_sockit.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sodia.dtb \
socfpga_cyclone5_vining_fpga.dtb \
socfpga_vt.dtb
dtb-$(CONFIG_ARCH_SPEAR13XX) += \
@ -712,16 +741,12 @@ dtb-$(CONFIG_ARCH_STI) += \
stih407-b2120.dtb \
stih410-b2120.dtb \
stih410-b2260.dtb \
stih415-b2000.dtb \
stih415-b2020.dtb \
stih416-b2000.dtb \
stih416-b2020.dtb \
stih416-b2020e.dtb \
stih418-b2199.dtb
dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
stm32429i-eval.dtb
stm32429i-eval.dtb \
stm32746g-eval.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
@ -760,6 +785,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-q8-tablet.dtb \
sun5i-a13-utoo-p66.dtb \
sun5i-gr8-chip-pro.dtb \
sun5i-gr8-evb.dtb \
sun5i-r8-chip.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
@ -897,6 +923,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \
wm8750-apc8750.dtb \
wm8850-w70v2.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-microzed.dtb \
zynq-parallella.dtb \
zynq-zc702.dtb \
zynq-zc706.dtb \
@ -920,6 +947,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \
armada-385-linksys-cobra.dtb \
armada-385-turris-omnia.dtb \
armada-388-clearfog.dtb \
armada-388-db.dtb \
armada-388-gp.dtb \

10
arch/arm/boot/dts/am335x-baltos-ir2110.dts
View File

@ -54,16 +54,22 @@
dr_mode = "host";
};
&davinci_mdio {
phy0: ethernet-phy@0 {
reg = <1>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
phy-handle = <&phy0>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
phy-handle = <&phy1>;
};
&phy_sel {

2
arch/arm/boot/dts/am335x-baltos-ir3220.dts
View File

@ -109,9 +109,9 @@
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
phy-handle = <&phy1>;
};
&phy_sel {

4
arch/arm/boot/dts/am335x-baltos-ir5221.dts
View File

@ -114,7 +114,7 @@
&usb1 {
status = "okay";
dr_mode = "otg";
dr_mode = "host";
};
&cpsw_emac0 {
@ -127,9 +127,9 @@
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
phy-handle = <&phy1>;
};
&phy_sel {

9
arch/arm/boot/dts/am335x-baltos.dtsi
View File

@ -364,11 +364,14 @@
};
&davinci_mdio {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <7>;
};
};
&mmc1 {
@ -406,3 +409,7 @@
&gpio0 {
ti,no-reset-on-init;
};
&gpio3 {
ti,no-reset-on-init;
};

22
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -6,6 +6,8 @@
* published by the Free Software Foundation.
*/
#include <dt-bindings/mfd/tps65217.h>
/ {
cpus {
cpu@0 {
@ -310,8 +312,23 @@
* by the hardware problems. (Tip: double-check by performing a current
* measurement after shutdown: it should be less than 1 mA.)
*/
interrupts = <7>; /* NMI */
interrupt-parent = <&intc>;
ti,pmic-shutdown-controller;
charger {
interrupts = <TPS65217_IRQ_AC>, <TPS65217_IRQ_USB>;
interrupts-names = "AC", "USB";
status = "okay";
};
pwrbutton {
interrupts = <TPS65217_IRQ_PB>;
status = "okay";
};
regulators {
dcdc1_reg: regulator@0 {
regulator-name = "vdds_dpr";
@ -393,3 +410,8 @@
&sham {
status = "okay";
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clock-names = "ext-clk", "int-clk";
};

11
arch/arm/boot/dts/am335x-boneblack.dts
View File

@ -79,6 +79,14 @@
&lcdc {
status = "okay";
/* If you want to get 24 bit RGB and 16 BGR mode instead of
* current 16 bit RGB and 24 BGR modes, set the propety
* below to "crossed" and uncomment the video-ports -property
* in tda19988 node.
*/
blue-and-red-wiring = "straight";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&hdmi_0>;
@ -95,6 +103,9 @@
pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
/* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
/* video-ports = <0x234501>; */
#sound-dai-cells = <0>;
audio-ports = < TDA998x_I2S 0x03>;

5
arch/arm/boot/dts/am335x-evm.dts
View File

@ -783,3 +783,8 @@
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins_default>;
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clock-names = "ext-clk", "int-clk";
};

5
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -715,3 +715,8 @@
blue-and-red-wiring = "crossed";
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clock-names = "ext-clk", "int-clk";
};

47
arch/arm/boot/dts/am335x-icev2.dts
View File

@ -43,52 +43,52 @@
enable-active-high;
};
leds0 {
leds-iio {
status = "disabled";
compatible = "gpio-leds";
led0 {
led-out0 {
label = "out0";
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led1 {
led-out1 {
label = "out1";
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led2 {
led-out2 {
label = "out2";
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led3 {
led-out3 {
label = "out3";
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led4 {
led-out4 {
label = "out4";
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led5 {
led-out5 {
label = "out5";
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led6 {
led-out6 {
label = "out6";
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led7 {
led-out7 {
label = "out7";
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
@ -187,6 +187,8 @@
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */
AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
>;
};
@ -224,6 +226,31 @@
};
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_default>;
sn65hvs882@1 {
compatible = "pisosr-gpio";
gpio-controller;
#gpio-cells = <2>;
load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
reg = <1>;
spi-max-frequency = <1000000>;
spi-cpol;
};
};
&tscadc {
status = "okay";
adc {
ti,adc-channels = <1 2 3 4 5 6 7>;
};
};
#include "tps65910.dtsi"
&tps {

6
arch/arm/boot/dts/am33xx.dtsi
View File

@ -130,6 +130,7 @@
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <1>;
ranges = <0 0x210000 0x2000>;
am33xx_pinmux: pinmux@800 {
@ -137,6 +138,7 @@
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
@ -505,6 +507,8 @@
interrupts = <75
76>;
ti,hwmods = "rtc";
clocks = <&clkdiv32k_ick>;
clock-names = "int-clk";
};
spi0: spi@48030000 {
@ -855,6 +859,8 @@
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";
dmas = <&edma 53 0>, <&edma 57 0>;
dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";

1
arch/arm/boot/dts/am3517.dtsi
View File

@ -66,6 +66,7 @@
reg = <0x480025d8 0x24>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;

3
arch/arm/boot/dts/am4372.dtsi
View File

@ -189,6 +189,7 @@
reg = <0x800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
@ -871,6 +872,8 @@
clocks = <&adc_tsc_fck>;
clock-names = "fck";
status = "disabled";
dmas = <&edma 53 0>, <&edma 57 0>;
dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";

101
arch/arm/boot/dts/am437x-idk-evm.dts
View File

@ -117,6 +117,58 @@
compatible = "fixed-clock";
clock-frequency = <32768>;
};
leds-iio {
status = "disabled";
compatible = "gpio-leds";
led-out0 {
label = "out0";
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out1 {
label = "out1";
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out2 {
label = "out2";
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out3 {
label = "out3";
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out4 {
label = "out4";
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out5 {
label = "out5";
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out6 {
label = "out6";
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out7 {
label = "out7";
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&am43xx_pinmux {
@ -178,6 +230,24 @@
>;
};
spi1_pins_default: spi1_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */
AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */
AM4372_IOPAD(0x944, PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */
AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */
>;
};
spi1_pins_sleep: spi1_pins_sleep {
pinctrl-single,pins = <
AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
ecap0_pins_default: backlight_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
@ -290,6 +360,33 @@
pinctrl-0 = <&i2c2_pins_default>;
pinctrl-1 = <&i2c2_pins_sleep>;
clock-frequency = <100000>;
tpic2810: tpic2810@60 {
compatible = "ti,tpic2810";
reg = <0x60>;
gpio-controller;
#gpio-cells = <2>;
};
};
&spi1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_default>;
pinctrl-1 = <&spi1_pins_sleep>;
ti,pindir-d0-out-d1-in;
sn65hvs882: sn65hvs882@0 {
compatible = "pisosr-gpio";
gpio-controller;
#gpio-cells = <2>;
load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
reg = <0>;
spi-max-frequency = <1000000>;
spi-cpol;
};
};
&epwmss0 {
@ -310,6 +407,10 @@
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};

81
arch/arm/boot/dts/am571x-idk.dts Normal file
View File

@ -0,0 +1,81 @@
/*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
/ {
model = "TI AM5718 IDK";
compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};
leds {
compatible = "gpio-leds";
cpu0-led {
label = "status0:red:cpu0";
gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu0";
};
usr0-led {
label = "status0:green:usr";
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
heartbeat-led {
label = "status0:blue:heartbeat";
gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
usr1-led {
label = "status1:red:usr";
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
usr2-led {
label = "status1:green:usr";
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
mmc0-led {
label = "status1:blue:mmc0";
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc0";
};
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
};
};
&mmc1 {
status = "okay";
vmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};

4
arch/arm/boot/dts/am572x-idk.dts
View File

@ -83,3 +83,7 @@
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
&sn65hvs882 {
load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};

1
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View File

@ -204,6 +204,7 @@
interrupt-controller;
ti,system-power-controller;
ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";

75
arch/arm/boot/dts/am57xx-idk-common.dtsi
View File

@ -43,6 +43,58 @@
regulator-always-on;
regulator-boot-on;
};
leds-iio {
status = "disabled";
compatible = "gpio-leds";
led-out0 {
label = "out0";
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out1 {
label = "out1";
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out2 {
label = "out2";
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out3 {
label = "out3";
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out4 {
label = "out4";
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out5 {
label = "out5";
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out6 {
label = "out6";
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-out7 {
label = "out7";
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&i2c1 {
@ -57,6 +109,7 @@
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
@ -253,6 +306,28 @@
};
};
&mcspi3 {
status = "okay";
ti,pindir-d0-out-d1-in;
sn65hvs882: sn65hvs882@0 {
compatible = "pisosr-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
spi-max-frequency = <1000000>;
spi-cpol;
};
tpic2810: tpic2810@60 {
compatible = "ti,tpic2810";
reg = <0x60>;
gpio-controller;
#gpio-cells = <2>;
};
};
&uart3 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH

63
arch/arm/boot/dts/armada-370-db.dts
View File

@ -67,7 +67,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
@ -86,18 +86,6 @@
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@ -182,24 +170,6 @@
};
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
sound {
@ -261,6 +231,37 @@
};
};
&pciec {
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&spi0 {
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";

30
arch/arm/boot/dts/armada-370-dlink-dns327l.dts
View File

@ -62,7 +62,7 @@
stdout-path = &uart0;
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MiB */
};
@ -72,20 +72,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
sata@a0000 {
nr-ports = <2>;
@ -262,6 +248,20 @@
};
};
&pciec {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&pinctrl {
sata_l_white_pin: sata-l-white-pin {
marvell,pins = "mpp57";

57
arch/arm/boot/dts/armada-370-mirabox.dts
View File

@ -54,7 +54,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@ -64,22 +64,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected on the PCB to a USB 3.0 XHCI controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
@ -113,17 +97,6 @@
};
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@ -197,6 +170,34 @@
};
};
&pciec {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected on the PCB to a USB 3.0 XHCI controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&pinctrl {
pwr_led_pin: pwr-led-pin {
marvell,pins = "mpp63";

55
arch/arm/boot/dts/armada-370-netgear-rn102.dts
View File

@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@ -66,22 +66,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
/* Connected to Marvell 88SE9170 SATA controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to FL1009 USB 3.0 controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@ -99,14 +83,6 @@
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
};
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
@ -120,8 +96,11 @@
};
i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
isl12057: isl12057@68 {
@ -257,6 +236,30 @@
};
};
&pciec {
status = "okay";
/* Connected to Marvell 88SE9170 SATA controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to FL1009 USB 3.0 controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
};
&pinctrl {
power_led_pin: power-led-pin {
marvell,pins = "mpp57";

63
arch/arm/boot/dts/armada-370-netgear-rn104.dts
View File

@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@ -66,22 +66,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
/* Connected to FL1009 USB 3.0 controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to Marvell 88SE9215 SATA controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@ -93,18 +77,6 @@
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
reg = <1>;
};
};
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@ -126,8 +98,11 @@
};
i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
isl12057: isl12057@68 {
@ -279,6 +254,34 @@
};
};
&pciec {
status = "okay";
/* Connected to FL1009 USB 3.0 controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to Marvell 88SE9215 SATA controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
reg = <1>;
};
};
&pinctrl {
poweroff: poweroff {
marvell,pins = "mpp60";

57
arch/arm/boot/dts/armada-370-rd.dts
View File

@ -67,7 +67,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@ -77,22 +77,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Internal mini-PCIe connector */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
@ -102,14 +86,6 @@
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@ -146,7 +122,7 @@
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
button {
label = "Software Button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
@ -196,7 +172,7 @@
};
};
dsa@0 {
dsa {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
@ -235,7 +211,32 @@
};
};
};
};
};
&pciec {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Internal mini-PCIe connector */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&pinctrl {
fan_pins: fan-pins {

27
arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
View File

@ -28,20 +28,7 @@
compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp";
soc {
pcie-controller {
/* SATA AHCI controller 88SE9170 */
pcie@1,0 {
status = "okay";
};
};
internal-regs {
mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
@ -131,3 +118,17 @@
1300 0>;
};
};
&pciec {
/* SATA AHCI controller 88SE9170 */
pcie@1,0 {
status = "okay";
};
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};

45
arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
View File

@ -23,7 +23,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@ -32,15 +32,6 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/* USB 3.0 bridge ASM1042A */
pcie@2,0 {
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
@ -51,15 +42,6 @@
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
@ -159,19 +141,19 @@
#address-cells = <1>;
#size-cells = <0>;
button@1 {
power {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
button@2 {
backup {
label = "Backup button";
linux,code = <KEY_OPTION>;
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
button@3 {
reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
@ -208,6 +190,25 @@
};
};
&pciec {
status = "okay";
/* USB 3.0 bridge ASM1042A */
pcie@2,0 {
status = "okay";
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&pinctrl {
pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>;
pinctrl-names = "default";

44
arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
View File

@ -24,7 +24,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@ -33,15 +33,6 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/* USB 3.0 Bridge ASM1042A */
pcie@1,0 {
status = "okay";
};
};
internal-regs {
coherency-fabric@20200 {
broken-idle;
@ -51,15 +42,6 @@
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
@ -107,19 +89,19 @@
#address-cells = <1>;
#size-cells = <0>;
button@1 {
power {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
debounce-interval = <100>;
};
button@2 {
reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
button@3 {
button {
label = "USB VBUS error";
linux,code = <KEY_UNKNOWN>;
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
@ -143,6 +125,24 @@
};
};
&pciec {
status = "okay";
/* USB 3.0 Bridge ASM1042A */
pcie@1,0 {
status = "okay";
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&pinctrl {
pinctrl-0 = <&sata_led_pin>;
pinctrl-names = "default";

18
arch/arm/boot/dts/armada-370-synology-ds213j.dts
View File

@ -70,7 +70,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@ -127,12 +127,6 @@
status = "okay";
};
mdio {
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy1>;
@ -192,7 +186,7 @@
pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>;
pinctrl-names = "default";
sata1_regulator: sata1-regulator {
sata1_regulator: sata1-regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA1 Power";
@ -205,7 +199,7 @@
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
};
sata2_regulator: sata2-regulator {
sata2_regulator: sata2-regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA2 Power";
@ -220,6 +214,12 @@
};
};
&mdio {
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
reg = <1>;
};
};
&pinctrl {
disk1_led_pin: disk1-led-pin {
marvell,pins = "mpp31";

39
arch/arm/boot/dts/armada-370-xp.dtsi
View File

@ -50,8 +50,6 @@
* 370 and Armada XP SoC.
*/
/include/ "skeleton64.dtsi"
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
@ -86,7 +84,7 @@
pcie-mem-aperture = <0xf8000000 0x7e00000>;
pcie-io-aperture = <0xffe00000 0x100000>;
devbus-bootcs {
devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@ -96,7 +94,7 @@
status = "disabled";
};
devbus-cs0 {
devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@ -106,7 +104,7 @@
status = "disabled";
};
devbus-cs1 {
devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@ -116,7 +114,7 @@
status = "disabled";
};
devbus-cs2 {
devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@ -126,7 +124,7 @@
status = "disabled";
};
devbus-cs3 {
devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@ -142,7 +140,7 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
rtc@10300 {
rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <50>;
@ -214,33 +212,38 @@
msi-controller;
};
coherency-fabric@20200 {
coherencyfab: coherency-fabric@20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21010 0x1c>;
};
timer@20300 {
timer: timer@20300 {
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
};
watchdog@20300 {
watchdog: watchdog@20300 {
reg = <0x20300 0x34>, <0x20704 0x4>;
};
pmsu@22000 {
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x8>;
};
pmsu: pmsu@22000 {
compatible = "marvell,armada-370-pmsu";
reg = <0x22000 0x1000>;
};
usb@50000 {
usb0: usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
usb@51000 {
usb1: usb@51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
@ -254,7 +257,7 @@
status = "disabled";
};
mdio: mdio {
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
@ -269,7 +272,7 @@
status = "disabled";
};
sata@a0000 {
sata: sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <55>;
@ -278,7 +281,7 @@
status = "disabled";
};
nand@d0000 {
nand: nand@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
@ -288,7 +291,7 @@
status = "disabled";
};
mvsdio@d4000 {
sdio: mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <54>;

136
arch/arm/boot/dts/armada-370.dtsi
View File

@ -50,9 +50,11 @@
*/
#include "armada-370-xp.dtsi"
/include/ "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Marvell Armada 370 family SoC";
compatible = "marvell,armada370", "marvell,armada-370-xp";
@ -70,7 +72,7 @@
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
pcie-controller {
pciec: pcie-controller@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@ -89,7 +91,7 @@
0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
pcie@1,0 {
pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@ -106,7 +108,7 @@
status = "disabled";
};
pcie@2,0 {
pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@ -125,7 +127,7 @@
};
internal-regs {
L2: l2-cache {
L2: l2-cache@8000 {
compatible = "marvell,aurora-outer-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
@ -134,14 +136,6 @@
wt-override;
};
i2c0: i2c@11000 {
reg = <0x11000 0x20>;
};
i2c1: i2c@11100 {
reg = <0x11100 0x20>;
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
@ -175,22 +169,8 @@
interrupts = <91>;
};
/*
* Default UART pinctrl setting without RTS/CTS, can
* be overwritten on board level if a different
* configuration is used.
*/
uart0: serial@12000 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
uart1: serial@12100 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
};
system-controller@18200 {
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
};
@ -208,37 +188,18 @@
#clock-cells = <1>;
};
thermal@18300 {
thermal: thermal@18300 {
compatible = "marvell,armada370-thermal";
reg = <0x18300 0x4
0x18304 0x4>;
status = "okay";
};
sscg@18330 {
sscg: sscg@18330 {
reg = <0x18330 0x4>;
};
interrupt-controller@20a00 {
reg = <0x20a00 0x1d0>, <0x21870 0x58>;
};
timer@20300 {
compatible = "marvell,armada-370-timer";
clocks = <&coreclk 2>;
};
watchdog@20300 {
compatible = "marvell,armada-370-wdt";
clocks = <&coreclk 2>;
};
cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x8>;
};
cpu-config@21000 {
cpuconf: cpu-config@21000 {
compatible = "marvell,armada-370-cpu-config";
reg = <0x21000 0x8>;
};
@ -253,15 +214,7 @@
status = "disabled";
};
usb@50000 {
clocks = <&coreclk 0>;
};
usb@51000 {
clocks = <&coreclk 0>;
};
xor@60800 {
xor0: xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
@ -280,7 +233,7 @@
};
};
xor@60900 {
xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@ -299,15 +252,7 @@
};
};
ethernet@70000 {
compatible = "marvell,armada-370-neta";
};
ethernet@74000 {
compatible = "marvell,armada-370-neta";
};
crypto@90000 {
cesa: crypto@90000 {
compatible = "marvell,armada-370-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
@ -342,6 +287,59 @@
};
};
/*
* Default UART pinctrl setting without RTS/CTS, can be overwritten on
* board level if a different configuration is used.
*/
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
&uart1 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
};
&i2c0 {
reg = <0x11000 0x20>;
};
&i2c1 {
reg = <0x11100 0x20>;
};
&mpic {
reg = <0x20a00 0x1d0>, <0x21870 0x58>;
};
&timer {
compatible = "marvell,armada-370-timer";
clocks = <&coreclk 2>;
};
&watchdog {
compatible = "marvell,armada-370-wdt";
clocks = <&coreclk 2>;
};
&usb0 {
clocks = <&coreclk 0>;
};
&usb1 {
clocks = <&coreclk 0>;
};
&eth0 {
compatible = "marvell,armada-370-neta";
};
&eth1 {
compatible = "marvell,armada-370-neta";
};
&pinctrl {
compatible = "marvell,mv88f6710-pinctrl";

271
arch/arm/boot/dts/armada-375-db.dts
View File

@ -58,7 +58,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
@ -69,138 +69,141 @@
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
/*
* SPI conflicts with NAND, so we disable it
* here, and select NAND as the enabled device
* by default.
*/
status = "disabled";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
};
i2c@11100 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
};
serial@12000 {
status = "okay";
};
pinctrl {
sdio_st_pins: sdio-st-pins {
marvell,pins = "mpp44", "mpp45";
marvell,function = "gpio";
};
};
sata@a0000 {
status = "okay";
nr-ports = <2>;
};
nand: nand@d0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "U-Boot";
reg = <0 0x800000>;
};
partition@800000 {
label = "Linux";
reg = <0x800000 0x800000>;
};
partition@1000000 {
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
usb@54000 {
status = "okay";
};
usb3@58000 {
status = "okay";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins &sdio_st_pins>;
pinctrl-names = "default";
status = "okay";
cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
ethernet@f0000 {
status = "okay";
eth0@c4000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
eth1@c5000 {
status = "okay";
phy = <&phy3>;
phy-mode = "gmii";
};
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};
&pciec {
status = "okay";
};
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
&pcie0 {
/* Port 0, Lane 0 */
status = "okay";
};
&pcie1 {
/* Port 1, Lane 0 */
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
/*
* SPI conflicts with NAND, so we disable it here, and
* select NAND as the enabled device by default.
*/
status = "disabled";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
};
&uart0 {
status = "okay";
};
&pinctrl {
sdio_st_pins: sdio-st-pins {
marvell,pins = "mpp44", "mpp45";
marvell,function = "gpio";
};
};
&sata {
status = "okay";
nr-ports = <2>;
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "U-Boot";
reg = <0 0x800000>;
};
partition@800000 {
label = "Linux";
reg = <0x800000 0x800000>;
};
partition@1000000 {
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
&sdio {
pinctrl-0 = <&sdio_pins &sdio_st_pins>;
pinctrl-names = "default";
status = "okay";
cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
&ethernet {
status = "okay";
};
&eth0 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
&eth1 {
status = "okay";
phy = <&phy3>;
phy-mode = "gmii";
};

72
arch/arm/boot/dts/armada-375.dtsi
View File

@ -45,7 +45,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
@ -53,6 +52,9 @@
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Marvell Armada 375 family SoC";
compatible = "marvell,armada375";
@ -65,7 +67,7 @@
};
clocks {
/* 2 GHz fixed main PLL */
/* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -84,12 +86,12 @@
#size-cells = <0>;
enable-method = "marvell,armada-375-smp";
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
@ -115,7 +117,7 @@
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
devbus-bootcs {
devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@ -125,7 +127,7 @@
status = "disabled";
};
devbus-cs0 {
devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@ -135,7 +137,7 @@
status = "disabled";
};
devbus-cs1 {
devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@ -145,7 +147,7 @@
status = "disabled";
};
devbus-cs2 {
devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@ -155,7 +157,7 @@
status = "disabled";
};
devbus-cs3 {
devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@ -182,12 +184,12 @@
prefetch-data = <1>;
};
scu@c000 {
scu: scu@c000 {
compatible = "arm,cortex-a9-scu";
reg = <0xc000 0x58>;
};
timer@c600 {
timer0: timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
@ -203,7 +205,7 @@
<0xc100 0x100>;
};
mdio {
mdio: mdio@c0054 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
@ -212,7 +214,7 @@
};
/* Network controller */
ethernet@f0000 {
ethernet: ethernet@f0000 {
compatible = "marvell,armada-375-pp2";
reg = <0xf0000 0xa000>, /* Packet Processor regs */
<0xc0000 0x3060>, /* LMS regs */
@ -222,20 +224,20 @@
clock-names = "pp_clk", "gop_clk";
status = "disabled";
eth0: eth0@c4000 {
eth0: eth0 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
status = "disabled";
};
eth1: eth1@c5000 {
eth1: eth1 {
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
status = "disabled";
};
};
rtc@10300 {
rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@ -307,7 +309,7 @@
status = "disabled";
};
pinctrl {
pinctrl: pinctrl@18000 {
compatible = "marvell,mv88f6720-pinctrl";
reg = <0x18000 0x24>;
@ -382,7 +384,7 @@
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
system-controller@18200 {
systemc: system-controller@18200 {
compatible = "marvell,armada-375-system-controller";
reg = <0x18200 0x100>;
};
@ -415,7 +417,7 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer@20300 {
timer1: timer@20300 {
compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
@ -428,24 +430,24 @@
clock-names = "nbclk", "fixed";
};
watchdog@20300 {
watchdog: watchdog@20300 {
compatible = "marvell,armada-375-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
clocks = <&coreclk 0>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst@20800 {
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
coherency-fabric@21010 {
coherencyfab: coherency-fabric@21010 {
compatible = "marvell,armada-375-coherency-fabric";
reg = <0x21010 0x1c>;
};
usb@50000 {
usb0: usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
@ -455,7 +457,7 @@
status = "disabled";
};
usb@54000 {
usb1: usb@54000 {
compatible = "marvell,orion-ehci";
reg = <0x54000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@ -463,7 +465,7 @@
status = "disabled";
};
usb3@58000 {
usb2: usb3@58000 {
compatible = "marvell,armada-375-xhci";
reg = <0x58000 0x20000>,<0x5b880 0x80>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@ -473,7 +475,7 @@
status = "disabled";
};
xor@60800 {
xor0: xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
@ -493,7 +495,7 @@
};
};
xor@60900 {
xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@ -513,7 +515,7 @@
};
};
crypto@90000 {
cesa: crypto@90000 {
compatible = "marvell,armada-375-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
@ -528,7 +530,7 @@
marvell,crypto-sram-size = <0x800>;
};
sata@a0000 {
sata: sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@ -537,7 +539,7 @@
status = "disabled";
};
nand@d0000 {
nand: nand@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
@ -547,7 +549,7 @@
status = "disabled";
};
mvsdio@d4000 {
sdio: mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@ -559,7 +561,7 @@
status = "disabled";
};
thermal@e8078 {
thermal: thermal@e8078 {
compatible = "marvell,armada375-thermal";
reg = <0xe8078 0x4>, <0xe807c 0x8>;
status = "okay";
@ -580,7 +582,7 @@
};
};
pcie-controller {
pciec: pcie-controller@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@ -599,7 +601,7 @@
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
pcie@1,0 {
pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@ -616,7 +618,7 @@
status = "disabled";
};
pcie@2,0 {
pcie1: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;

340
arch/arm/boot/dts/armada-385-turris-omnia.dts Normal file
View File

@ -0,0 +1,340 @@
/*
* Device Tree file for the Turris Omnia
*
* Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
* Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385.dtsi"
/ {
model = "Turris Omnia";
compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1024 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
/* USB part of the PCIe2/USB 2.0 port */
usb@58000 {
status = "okay";
};
sata@a8000 {
status = "okay";
};
sdhci@d8000 {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
status = "okay";
bus-width = <8>;
no-1-8-v;
non-removable;
};
usb3@f0000 {
status = "okay";
};
usb3@f8000 {
status = "okay";
};
};
pcie-controller {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
pcie@3,0 {
/* Port 2, Lane 0 */
status = "okay";
};
};
};
};
/* Connected to 88E6176 switch, port 6 */
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&ge0_rgmii_pins>;
status = "okay";
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* Connected to 88E6176 switch, port 5 */
&eth1 {
pinctrl-names = "default";
pinctrl-0 = <&ge1_rgmii_pins>;
status = "okay";
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* WAN port */
&eth2 {
status = "okay";
phy-mode = "sgmii";
phy = <&phy1>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
i2cmux@70 {
compatible = "nxp,pca9547";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
status = "okay";
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* STM32F0 command interface at address 0x2a */
/* leds device (in STM32F0) at address 0x2b */
eeprom@54 {
compatible = "at,24c64";
reg = <0x54>;
/* The EEPROM contains data for bootloader.
* Contents:
* struct omnia_eeprom {
* u32 magic; (=0x0341a034 in LE)
* u32 ramsize; (in GiB)
* char regdomain[4];
* u32 crc32;
* };
*/
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* routed to PCIe0/mSATA connector (CN7A) */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* routed to PCIe1/USB2 connector (CN61A) */
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
/* routed to PCIe2 connector (CN62A) */
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* routed to SFP+ */
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
/* ATSHA204A at address 0x64 */
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
/* exposed on pin header */
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
pcawan: gpio@71 {
/*
* GPIO expander for SFP+ signals and
* and phy irq
*/
compatible = "nxp,pca9538";
reg = <0x71>;
pinctrl-names = "default";
pinctrl-0 = <&pcawan_pins>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
phy1: phy@1 {
status = "okay";
compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
reg = <1>;
/* irq is connected to &pcawan pin 7 */
};
/* Switch MV88E7176 at address 0x10 */
};
&pinctrl {
pcawan_pins: pcawan-pins {
marvell,pins = "mpp46";
marvell,function = "gpio";
};
spi0cs0_pins: spi0cs0-pins {
marvell,pins = "mpp25";
marvell,function = "spi0";
};
spi0cs1_pins: spi0cs1-pins {
marvell,pins = "mpp26";
marvell,function = "spi0";
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
status = "okay";
spi-nor@0 {
compatible = "spansion,s25fl164k", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x00100000>;
label = "U-Boot";
};
partition@100000 {
reg = <0x00100000 0x00700000>;
label = "Rescue system";
};
};
};
/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
};
&uart0 {
/* Pin header CN10 */
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
/* Pin header CN11 */
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};

2
arch/arm/boot/dts/armada-38x.dtsi
View File

@ -661,7 +661,7 @@
};
clocks {
/* 2 GHz fixed main PLL */
/* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;

2
arch/arm/boot/dts/armada-39x.dtsi
View File

@ -573,7 +573,7 @@
};
clocks {
/* 2 GHz fixed main PLL */
/* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;

68
arch/arm/boot/dts/armada-xp-axpwifiap.dts
View File

@ -62,7 +62,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
};
@ -73,28 +73,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/* First mini-PCIe port */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Second mini-PCIe port */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Renesas uPD720202 USB 3.0 controller */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
};
};
internal-regs {
/* UART0 */
serial@12000 {
@ -111,16 +89,6 @@
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@ -145,7 +113,7 @@
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
button@1 {
reset {
label = "Factory Reset Button";
linux,code = <KEY_SETUP>;
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@ -153,6 +121,38 @@
};
};
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&pciec {
status = "okay";
/* First mini-PCIe port */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Second mini-PCIe port */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Renesas uPD720202 USB 3.0 controller */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
};
};
&pinctrl {
pinctrl-0 = <&phy_int_pin>;
pinctrl-names = "default";

104
arch/arm/boot/dts/armada-xp-db.dts
View File

@ -67,7 +67,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
};
@ -108,39 +108,6 @@
};
};
pcie-controller {
status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
@ -160,24 +127,6 @@
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <25>;
};
phy3: ethernet-phy@3 {
reg = <27>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@ -266,6 +215,57 @@
};
};
&pciec {
status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <25>;
};
phy3: ethernet-phy@3 {
reg = <27>;
};
};
&spi0 {
status = "okay";

80
arch/arm/boot/dts/armada-xp-gp.dts
View File

@ -68,7 +68,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
/*
* 8 GB of plug-in RAM modules by default.The amount
@ -127,27 +127,6 @@
};
};
pcie-controller {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
@ -175,24 +154,6 @@
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <16>;
};
phy1: ethernet-phy@1 {
reg = <17>;
};
phy2: ethernet-phy@2 {
reg = <18>;
};
phy3: ethernet-phy@3 {
reg = <19>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@ -251,6 +212,45 @@
};
};
&pciec {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 {
reg = <16>;
};
phy1: ethernet-phy@1 {
reg = <17>;
};
phy2: ethernet-phy@2 {
reg = <18>;
};
phy3: ethernet-phy@3 {
reg = <19>;
};
};
&spi0 {
status = "okay";

53
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
View File

@ -57,7 +57,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x20000000>; /* 512MB */
};
@ -68,37 +68,11 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/* Quad port sata: Marvell 88SX7042 */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* USB 3.0 xHCI controller: NEC D720200F1 */
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
};
mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
reg = <1>;
};
};
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@ -295,6 +269,31 @@
gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};
};
&pciec {
status = "okay";
/* Quad port sata: Marvell 88SX7042 */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* USB 3.0 xHCI controller: NEC D720200F1 */
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
reg = <1>;
};
};
&pinctrl {
poweroff_pin: poweroff-pin {

52
arch/arm/boot/dts/armada-xp-linksys-mamba.dts
View File

@ -62,7 +62,7 @@
stdout-path = &uart0;
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
};
@ -73,28 +73,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/* Etron EJ168 USB 3.0 controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* First mini-PCIe port */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Second mini-PCIe port */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
};
};
internal-regs {
rtc@10300 {
@ -289,13 +267,13 @@
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
button@1 {
wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
};
button@2 {
reset {
label = "Factory Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@ -323,7 +301,7 @@
4500 1>;
};
dsa@0 {
dsa {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
@ -369,6 +347,28 @@
};
};
&pciec {
status = "okay";
/* Etron EJ168 USB 3.0 controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* First mini-PCIe port */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Second mini-PCIe port */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
};
};
&pinctrl {
keys_pin: keys-pin {

20
arch/arm/boot/dts/armada-xp-matrix.dts
View File

@ -55,7 +55,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
/*
* This board has 4 GB of RAM, but the last 256 MB of
@ -99,18 +99,18 @@
};
};
pcie-controller {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
usb@50000 {
status = "okay";
};
};
};
};
&pciec {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};

12
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View File

@ -86,7 +86,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x1 only.
*/
pcie-controller {
pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@ -114,7 +114,7 @@
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
pcie@1,0 {
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@ -131,7 +131,7 @@
status = "disabled";
};
pcie@2,0 {
pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@ -148,7 +148,7 @@
status = "disabled";
};
pcie@3,0 {
pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@ -165,7 +165,7 @@
status = "disabled";
};
pcie@4,0 {
pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@ -182,7 +182,7 @@
status = "disabled";
};
pcie@5,0 {
pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;

20
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View File

@ -87,7 +87,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x4 only.
*/
pcie-controller {
pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@ -129,7 +129,7 @@
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
pcie@1,0 {
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@ -146,7 +146,7 @@
status = "disabled";
};
pcie@2,0 {
pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@ -163,7 +163,7 @@
status = "disabled";
};
pcie@3,0 {
pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@ -180,7 +180,7 @@
status = "disabled";
};
pcie@4,0 {
pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@ -197,7 +197,7 @@
status = "disabled";
};
pcie@5,0 {
pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
@ -214,7 +214,7 @@
status = "disabled";
};
pcie@6,0 {
pcie6: pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
@ -231,7 +231,7 @@
status = "disabled";
};
pcie@7,0 {
pcie7: pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
@ -248,7 +248,7 @@
status = "disabled";
};
pcie@8,0 {
pcie8: pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
@ -265,7 +265,7 @@
status = "disabled";
};
pcie@9,0 {
pcie9: pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;

22
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View File

@ -104,7 +104,7 @@
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
pcie-controller {
pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@ -150,7 +150,7 @@
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
pcie@1,0 {
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@ -167,7 +167,7 @@
status = "disabled";
};
pcie@2,0 {
pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@ -184,7 +184,7 @@
status = "disabled";
};
pcie@3,0 {
pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@ -201,7 +201,7 @@
status = "disabled";
};
pcie@4,0 {
pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@ -218,7 +218,7 @@
status = "disabled";
};
pcie@5,0 {
pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
@ -235,7 +235,7 @@
status = "disabled";
};
pcie@6,0 {
pcie6: pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
@ -252,7 +252,7 @@
status = "disabled";
};
pcie@7,0 {
pcie7: pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
@ -269,7 +269,7 @@
status = "disabled";
};
pcie@8,0 {
pcie8: pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
@ -286,7 +286,7 @@
status = "disabled";
};
pcie@9,0 {
pcie9: pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
@ -303,7 +303,7 @@
status = "disabled";
};
pcie@10,0 {
pcie10: pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;

74
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
View File

@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x80000000>; /* 2GB */
};
@ -67,28 +67,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/* Connected to first Marvell 88SE9170 SATA controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to second Marvell 88SE9170 SATA controller */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Connected to Fresco Logic FL1009 USB 3.0 controller */
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@ -97,7 +75,6 @@
};
i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
clock-frequency = <400000>;
status = "okay";
@ -154,23 +131,19 @@
status = "okay";
};
mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
reg = <1>;
};
};
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
@ -295,6 +268,39 @@
};
};
&pciec {
status = "okay";
/* Connected to first Marvell 88SE9170 SATA controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to second Marvell 88SE9170 SATA controller */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Connected to Fresco Logic FL1009 USB 3.0 controller */
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
reg = <1>;
};
};
&pinctrl {
poweroff: poweroff {
marvell,pins = "mpp42";

58
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View File

@ -57,7 +57,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */
};
@ -98,15 +98,6 @@
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
internal-regs {
rtc@10300 {
/* No crystal connected to the internal RTC */
@ -148,31 +139,13 @@
#address-cells = <1>;
#size-cells = <0>;
button@1 {
init {
label = "Init Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
};
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@ -240,6 +213,33 @@
};
};
&pciec {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
&pinctrl {
led_pins: led-pins-0 {
marvell,pins = "mpp49", "mpp51", "mpp53";

75
arch/arm/boot/dts/armada-xp-synology-ds414.dts
View File

@ -70,7 +70,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1GB */
};
@ -81,28 +81,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/*
* Connected to Marvell 88SX7042 SATA-II controller
* handling the four disks.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/*
* Connected to EtronTech EJ168A XHCI controller
* providing the two rear USB 3.0 ports.
*/
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
/* RTC is provided by Seiko S-35390A below */
@ -150,16 +128,6 @@
status = "okay";
};
mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
@ -186,7 +154,7 @@
&sata3_pwr_pin &sata4_pwr_pin>;
pinctrl-names = "default";
sata1_regulator: sata1-regulator {
sata1_regulator: sata1-regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA1 Power";
@ -199,7 +167,7 @@
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
sata2_regulator: sata2-regulator {
sata2_regulator: sata2-regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA2 Power";
@ -212,7 +180,7 @@
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
sata3_regulator: sata3-regulator {
sata3_regulator: sata3-regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "SATA3 Power";
@ -225,7 +193,7 @@
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
sata4_regulator: sata4-regulator {
sata4_regulator: sata4-regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "SATA4 Power";
@ -240,6 +208,39 @@
};
};
&pciec {
status = "okay";
/*
* Connected to Marvell 88SX7042 SATA-II controller
* handling the four disks.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/*
* Connected to EtronTech EJ168A XHCI controller
* providing the two rear USB 3.0 ports.
*/
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
reg = <1>;
};
};
&pinctrl {
sata1_pwr_pin: sata1-pwr-pin {
marvell,pins = "mpp42";

94
arch/arm/boot/dts/armada-xp.dtsi
View File

@ -53,6 +53,9 @@
#include "armada-370-xp.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
@ -75,7 +78,7 @@
reg = <0x1400 0x500>;
};
L2: l2-cache {
L2: l2-cache@8000 {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
@ -84,16 +87,6 @@
wt-override;
};
i2c0: i2c@11000 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
i2c1: i2c@11100 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
uart2: serial@12200 {
compatible = "snps,dw-apb-uart";
pinctrl-0 = <&uart2_pins>;
@ -118,7 +111,7 @@
status = "disabled";
};
system-controller@18200 {
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
@ -136,7 +129,7 @@
#clock-cells = <1>;
};
thermal@182b0 {
thermal: thermal@182b0 {
compatible = "marvell,armadaxp-thermal";
reg = <0x182b0 0x4
0x184d0 0x4>;
@ -150,27 +143,6 @@
clocks = <&coreclk 1>;
};
interrupt-controller@20a00 {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
timer@20300 {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
watchdog@20300 {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x20>;
};
cpu-config@21000 {
compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
@ -184,15 +156,7 @@
status = "disabled";
};
usb@50000 {
clocks = <&gateclk 18>;
};
usb@51000 {
clocks = <&gateclk 19>;
};
usb@52000 {
usb2: usb@52000 {
compatible = "marvell,orion-ehci";
reg = <0x52000 0x500>;
interrupts = <47>;
@ -200,7 +164,7 @@
status = "disabled";
};
xor@60900 {
xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@ -228,7 +192,7 @@
compatible = "marvell,armada-xp-neta";
};
crypto@90000 {
cesa: crypto@90000 {
compatible = "marvell,armada-xp-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
@ -248,7 +212,7 @@
status = "disabled";
};
xor@f0900 {
xor0: xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
0xF0B00 0x100>;
@ -309,6 +273,44 @@
};
};
&i2c0 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
&mpic {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
&timer {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&watchdog {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&cpurst {
reg = <0x20800 0x20>;
};
&usb0 {
clocks = <&gateclk 18>;
};
&usb1 {
clocks = <&gateclk 19>;
};
&pinctrl {
ge0_gmii_pins: ge0-gmii-pins {
marvell,pins =

4
arch/arm/boot/dts/artpec6-devboard.dts
View File

@ -46,6 +46,10 @@
status = "okay";
};
&pcie {
status = "okay";
};
&ethernet {
status = "okay";

29
arch/arm/boot/dts/artpec6.dtsi
View File

@ -67,7 +67,7 @@
};
};
syscon {
syscon: syscon@f8000000 {
compatible = "axis,artpec6-syscon", "syscon";
reg = <0xf8000000 0x48>;
};
@ -154,6 +154,33 @@
interrupt-parent = <&intc>;
};
pcie: pcie@f8050000 {
compatible = "axis,artpec6-pcie", "snps,dw-pcie";
reg = <0xf8050000 0x2000
0xf8040000 0x1000
0xc0000000 0x2000>;
reg-names = "dbi", "phy", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
/* downstream I/O */
ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
/* non-prefetchable memory */
0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
num-lanes = <2>;
bus-range = <0x00 0xff>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
axis,syscon-pcie = <&syscon>;
status = "disabled";
};
amba@0 {
compatible = "simple-bus";
#address-cells = <0x1>;

4
arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
View File

@ -12,8 +12,8 @@
#include "sama5d4.dtsi"
/ {
model = "DENX MA5D4";
compatible = "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
model = "Aries/DENX MA5D4";
compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
memory {
reg = <0x20000000 0x10000000>;

4
arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
View File

@ -13,8 +13,8 @@
#include "at91-sama5d4_ma5d4.dtsi"
/ {
model = "DENX MA5D4EVK";
compatible = "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
model = "Aries/DENX MA5D4EVK";
compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
chosen {
stdout-path = "serial3:115200n8";

4
arch/arm/boot/dts/at91rm9200.dtsi
View File

@ -481,8 +481,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};

4
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -412,8 +412,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */
<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};

4
arch/arm/boot/dts/at91sam9260ek.dts
View File

@ -174,14 +174,14 @@
label = "Button 3";
gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
linux,code = <0x103>;
gpio-key,wakeup;
wakeup-source;
};
btn4 {
label = "Button 4";
gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
gpio-key,wakeup;
wakeup-source;
};
};

4
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -302,8 +302,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};

4
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -412,8 +412,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
<AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};

4
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -478,8 +478,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};

4
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@ -500,8 +500,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};

4
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -438,8 +438,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};

4
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -460,8 +460,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};

21
arch/arm/boot/dts/bcm-cygnus.dtsi
View File

@ -91,6 +91,13 @@
#address-cells = <1>;
#size-cells = <1>;
otp: otp@0301c800 {
compatible = "brcm,ocotp";
reg = <0x0301c800 0x2c>;
brcm,ocotp-size = <2048>;
status = "disabled";
};
pcie_phy: phy@0301d0a0 {
compatible = "brcm,cygnus-pcie-phy";
reg = <0x0301d0a0 0x14>;
@ -108,12 +115,21 @@
};
};
pinctrl: pinctrl@0x0301d0c8 {
pinctrl: pinctrl@0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
<0x0301d24c 0x2c>;
};
mailbox: mailbox@03024024 {
compatible = "brcm,iproc-mailbox";
reg = <0x03024024 0x40>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-controller;
#mbox-cells = <1>;
};
gpio_crmu: gpio@03024800 {
compatible = "brcm,cygnus-crmu-gpio";
reg = <0x03024800 0x50>,
@ -121,6 +137,9 @@
ngpios = <6>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&mailbox>;
interrupts = <0>;
};
i2c0: i2c@18008000 {

41
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -160,7 +160,7 @@
axi {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x0011ba08>;
ranges = <0x00000000 0x18000000 0x0011c40a>;
#address-cells = <1>;
#size-cells = <1>;
@ -241,6 +241,16 @@
brcm,nand-has-wp;
};
gpiob: gpio@30000 {
compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
reg = <0x30000 0x50>;
#gpio-cells = <2>;
gpio-controller;
ngpios = <4>;
interrupt-controller;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
};
pwm: pwm@31000 {
compatible = "brcm,iproc-pwm";
reg = <0x31000 0x28>;
@ -254,6 +264,35 @@
reg = <0x33000 0x14>;
};
qspi: qspi@27200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
reg = <0x027200 0x184>,
<0x027000 0x124>,
<0x11c408 0x004>,
<0x0273a0 0x01c>;
reg-names = "mspi", "bspi", "intr_regs",
"intr_status_reg";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overhead",
"mspi_done",
"mspi_halted";
clocks = <&iprocmed>;
clock-names = "iprocmed";
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
ccbtimer0: timer@34000 {
compatible = "arm,sp804";
reg = <0x34000 0x1000>;

67
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
View File

@ -22,7 +22,72 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
/*
* This is based on the unreleased schematic for the Model A+.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD0",
"RXD0",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"SDA0",
"SCL0",
"NC", /* GPIO30 */
"NC", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"PWR_LOW_N", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"USB_LIMIT", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"NC", /* GPIO44 */
"PWM1_OUT", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {

69
arch/arm/boot/dts/bcm2835-rpi-a.dts
View File

@ -15,7 +15,74 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
/*
* Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
* RPI00021 sheet 02
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"CAM_GPIO1",
"LAN_RUN",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"NC", /* GPIO12 */
"NC", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
"NC", /* GPIO19 */
"NC", /* GPIO20 */
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"NC", /* GPIO26 */
"CAM_GPIO0",
/* Binary number representing build/revision */
"CONFIG0",
"CONFIG1",
"CONFIG2",
"CONFIG3",
"NC", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"NC", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"NC", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT",
"NC", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"NC", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {

68
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
View File

@ -23,7 +23,73 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
/*
* Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf
* RPI-BPLUS sheet 1
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD0",
"RXD0",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"SDA0",
"SCL0",
"NC", /* GPIO30 */
"LAN_RUN", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"PWR_LOW_N", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"USB_LIMIT", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"ETHCLK", /* GPIO44 */
"PWM1_OUT", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {

68
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
View File

@ -16,7 +16,73 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
/*
* Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf
* RPI00022 sheet 02
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"CAM_CLK",
"LAN_RUN",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"NC", /* GPIO12 */
"NC", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
"NC", /* GPIO19 */
"NC", /* GPIO20 */
"CAM_GPIO",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"NC", /* GPIO26 */
"GPIO27",
"GPIO28",
"GPIO29",
"GPIO30",
"GPIO31",
"NC", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"NC", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"NC", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT",
"NC", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"NC", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {

69
arch/arm/boot/dts/bcm2835-rpi-b.dts
View File

@ -16,7 +16,74 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &alt3>;
/*
* Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
* RPI00021 sheet 02
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"CAM_GPIO1",
"LAN_RUN",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"NC", /* GPIO12 */
"NC", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
"NC", /* GPIO19 */
"NC", /* GPIO20 */
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"NC", /* GPIO26 */
"CAM_GPIO0",
/* Binary number representing build/revision */
"CONFIG0",
"CONFIG1",
"CONFIG2",
"CONFIG3",
"NC", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"NC", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"NC", /* GPIO38 */
"NC", /* GPIO39 */
"PWM0_OUT",
"NC", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"NC", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0>;
};
&hdmi {

67
arch/arm/boot/dts/bcm2835-rpi-zero.dts
View File

@ -26,7 +26,72 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
/*
* This is based on the official GPU firmware DT blob.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "SDA0",
"SCL0",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD0",
"RXD0",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"SDA0",
"SCL0",
"NC", /* GPIO30 */
"NC", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"NC", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"NC", /* GPIO38 */
"NC", /* GPIO39 */
"NC", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
"NC", /* GPIO42 */
"NC", /* GPIO43 */
"NC", /* GPIO44 */
"NC", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED_N",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {

15
arch/arm/boot/dts/bcm2835-rpi.dtsi
View File

@ -39,22 +39,21 @@
};
alt0: alt0 {
brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
brcm,pins = <4 5 7 8 9 10 11 14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
alt3: alt3 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_gpio0>;
status = "okay";
clock-frequency = <100000>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_gpio2>;
status = "okay";
clock-frequency = <100000>;
};
@ -64,11 +63,15 @@
};
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio48>;
status = "okay";
bus-width = <4>;
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
status = "okay";
};

6
arch/arm/boot/dts/bcm2835.dtsi
View File

@ -23,3 +23,9 @@
};
};
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2835-thermal";
status = "okay";
};

2
arch/arm/boot/dts/bcm2836-rpi-2-b.dts
View File

@ -27,7 +27,7 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {

6
arch/arm/boot/dts/bcm2836.dtsi
View File

@ -76,3 +76,9 @@
interrupt-parent = <&local_intc>;
interrupts = <8>;
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2836-thermal";
status = "okay";
};

212
arch/arm/boot/dts/bcm283x.dtsi
View File

@ -104,7 +104,7 @@
reg = <0x7e104000 0x10>;
};
mailbox: mailbox@7e00b800 {
mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
@ -132,6 +132,209 @@
interrupt-controller;
#interrupt-cells = <2>;
/* Defines pin muxing groups according to
* BCM2835-ARM-Peripherals.pdf page 102.
*
* While each pin can have its mux selected
* for various functions individually, some
* groups only make sense to switch to a
* particular function together.
*/
dpi_gpio0: dpi_gpio0 {
brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
emmc_gpio22: emmc_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
emmc_gpio34: emmc_gpio34 {
brcm,pins = <34 35 36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT3>;
brcm,pull = <BCM2835_PUD_OFF
BCM2835_PUD_UP
BCM2835_PUD_UP
BCM2835_PUD_UP
BCM2835_PUD_UP
BCM2835_PUD_UP>;
};
emmc_gpio48: emmc_gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
gpclk0_gpio4: gpclk0_gpio4 {
brcm,pins = <4>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk1_gpio5: gpclk1_gpio5 {
brcm,pins = <5>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk1_gpio42: gpclk1_gpio42 {
brcm,pins = <42>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk1_gpio44: gpclk1_gpio44 {
brcm,pins = <44>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk2_gpio6: gpclk2_gpio6 {
brcm,pins = <6>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk2_gpio43: gpclk2_gpio43 {
brcm,pins = <43>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c0_gpio0: i2c0_gpio0 {
brcm,pins = <0 1>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c0_gpio32: i2c0_gpio32 {
brcm,pins = <32 34>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c0_gpio44: i2c0_gpio44 {
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT1>;
};
i2c1_gpio2: i2c1_gpio2 {
brcm,pins = <2 3>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c1_gpio44: i2c1_gpio44 {
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
i2c_slave_gpio18: i2c_slave_gpio18 {
brcm,pins = <18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
jtag_gpio4: jtag_gpio4 {
brcm,pins = <4 5 6 12 13>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
jtag_gpio22: jtag_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
pcm_gpio18: pcm_gpio18 {
brcm,pins = <18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pcm_gpio28: pcm_gpio28 {
brcm,pins = <28 29 30 31>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
pwm0_gpio12: pwm0_gpio12 {
brcm,pins = <12>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm0_gpio18: pwm0_gpio18 {
brcm,pins = <18>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
pwm0_gpio40: pwm0_gpio40 {
brcm,pins = <40>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm1_gpio13: pwm1_gpio13 {
brcm,pins = <13>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm1_gpio19: pwm1_gpio19 {
brcm,pins = <19>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
pwm1_gpio41: pwm1_gpio41 {
brcm,pins = <41>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm1_gpio45: pwm1_gpio45 {
brcm,pins = <45>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
sdhost_gpio48: sdhost_gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
spi0_gpio7: spi0_gpio7 {
brcm,pins = <7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
spi0_gpio35: spi0_gpio35 {
brcm,pins = <35 36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
spi1_gpio16: spi1_gpio16 {
brcm,pins = <16 17 18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
spi2_gpio40: spi2_gpio40 {
brcm,pins = <40 41 42 43 44 45>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
uart0_gpio14: uart0_gpio14 {
brcm,pins = <14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
/* Separate from the uart0_gpio14 group
* because it conflicts with spi1_gpio16, and
* people often run uart0 on the two pins
* without flow contrl.
*/
uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
brcm,pins = <16 17>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
uart0_gpio30: uart0_gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
uart1_gpio14: uart1_gpio14 {
brcm,pins = <14 15>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
brcm,pins = <16 17>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_gpio32: uart1_gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_gpio36: uart1_gpio36 {
brcm,pins = <36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart1_gpio40: uart1_gpio40 {
brcm,pins = <40 41>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
brcm,pins = <42 43>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
};
uart0: serial@7e201000 {
@ -187,6 +390,13 @@
interrupts = <2 14>; /* pwa1 */
};
thermal: thermal@7e212000 {
compatible = "brcm,bcm2835-thermal";
reg = <0x7e212000 0x8>;
clocks = <&clocks BCM2835_CLOCK_TSENS>;
status = "disabled";
};
aux: aux@0x7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;

64
arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts Normal file
View File

@ -0,0 +1,64 @@
/*
* Copyright 2016 Luxul Inc.
*
* Licensed under the ISC license.
*/
/dts-v1/;
#include "bcm4708.dtsi"
/ {
compatible = "luxul,xap-1510v1", "brcm,bcm4708";
model = "Luxul XAP-1510 V1";
chosen {
bootargs = "console=ttyS0,115200 earlycon";
};
memory {
reg = <0x00000000 0x08000000>;
};
leds {
compatible = "gpio-leds";
5ghz {
label = "bcm53xx:blue:5ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
};
};
&uart0 {
status = "okay";
};
&spi_nor {
status = "okay";
};

2
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
View File

@ -9,7 +9,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {

2
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
View File

@ -9,7 +9,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {

2
arch/arm/boot/dts/bcm4709-netgear-r7000.dts
View File

@ -9,7 +9,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {

6
arch/arm/boot/dts/bcm4709-netgear-r8000.dts
View File

@ -9,7 +9,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
@ -107,6 +107,10 @@
};
};
&uart0 {
status = "okay";
};
&usb2 {
vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
};

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