mlx5-fixes-2020-02-18
-----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGhZs6bAKwk/OTgTpSD+KveBX+j4FAl5MpQAACgkQSD+KveBX +j7kcwgAtUPPpulo9AqMjk+2dJ67lT+GKl4JlrQR2kFs9o0j5vO8apixckqBGXyV wHTHLR79T710T1LD2mdIPFwFE5ecXKQL3mVrYMcyPCdkntZnNK7K3LpRWOo0t3yf JBeQoN+VuCXFAsyuQ39W+cr0+i4tO8DQ9kBj7usLu/8apuyo3KzA/3uLFE69zZeb vC7Cc+TcSWeiDvgCZGFRYtoRBvV2+AcyDNjY3Kaz6Yl+hgu53pGJfJWgV+lCxxr8 vavJJgQQeAjFX52QttiXQBsvkfX+cqNfzVc/W9tI5rq5C0qmH4yGndrTOwsvCFen Q+5pbP6KYNX6X7urHfuJ25q5/mUkeA== =xZyi -----END PGP SIGNATURE----- Merge tag 'mlx5-fixes-2020-02-18' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== Mellanox, mlx5 fixes 2020-02-18 This series introduces some fixes to mlx5 driver. Please pull and let me know if there is any problem. For -stable v5.3 ('net/mlx5: Fix sleep while atomic in mlx5_eswitch_get_vepa') For -stable v5.4 ('net/mlx5: DR, Fix matching on vport gvmi') ('net/mlx5e: Fix crash in recovery flow without devlink reporter') For -stable v5.5 ('net/mlx5e: Reset RQ doorbell counter before moving RQ state from RST to RDY') ('net/mlx5e: Don't clear the whole vf config when switching modes') ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
7822dee5d1
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@ -200,7 +200,7 @@ int mlx5e_health_report(struct mlx5e_priv *priv,
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netdev_err(priv->netdev, err_str);
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if (!reporter)
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return err_ctx->recover(&err_ctx->ctx);
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return err_ctx->recover(err_ctx->ctx);
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return devlink_health_report(reporter, err_str, err_ctx);
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}
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@ -179,6 +179,14 @@ mlx5e_tx_dma_unmap(struct device *pdev, struct mlx5e_sq_dma *dma)
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}
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}
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static inline void mlx5e_rqwq_reset(struct mlx5e_rq *rq)
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{
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if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
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mlx5_wq_ll_reset(&rq->mpwqe.wq);
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else
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mlx5_wq_cyc_reset(&rq->wqe.wq);
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}
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/* SW parser related functions */
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struct mlx5e_swp_spec {
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@ -712,6 +712,9 @@ int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
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if (!in)
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return -ENOMEM;
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if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
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mlx5e_rqwq_reset(rq);
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rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
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MLX5_SET(modify_rq_in, in, rq_state, curr_state);
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@ -459,12 +459,16 @@ static void esw_destroy_legacy_table(struct mlx5_eswitch *esw)
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static int esw_legacy_enable(struct mlx5_eswitch *esw)
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{
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int ret;
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struct mlx5_vport *vport;
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int ret, i;
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ret = esw_create_legacy_table(esw);
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if (ret)
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return ret;
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mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
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vport->info.link_state = MLX5_VPORT_ADMIN_STATE_AUTO;
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ret = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_LEGACY_SRIOV_VPORT_EVENTS);
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if (ret)
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esw_destroy_legacy_table(esw);
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@ -2452,25 +2456,17 @@ out:
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int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting)
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{
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int err = 0;
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if (!esw)
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return -EOPNOTSUPP;
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if (!ESW_ALLOWED(esw))
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return -EPERM;
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mutex_lock(&esw->state_lock);
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if (esw->mode != MLX5_ESWITCH_LEGACY) {
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err = -EOPNOTSUPP;
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goto out;
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}
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if (esw->mode != MLX5_ESWITCH_LEGACY)
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return -EOPNOTSUPP;
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*setting = esw->fdb_table.legacy.vepa_uplink_rule ? 1 : 0;
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out:
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mutex_unlock(&esw->state_lock);
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return err;
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return 0;
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}
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int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
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@ -1172,7 +1172,7 @@ static int esw_offloads_start(struct mlx5_eswitch *esw,
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return -EINVAL;
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}
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mlx5_eswitch_disable(esw, true);
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mlx5_eswitch_disable(esw, false);
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mlx5_eswitch_update_num_of_vfs(esw, esw->dev->priv.sriov.num_vfs);
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err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_OFFLOADS);
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if (err) {
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@ -2065,7 +2065,7 @@ static int esw_offloads_stop(struct mlx5_eswitch *esw,
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{
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int err, err1;
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mlx5_eswitch_disable(esw, true);
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mlx5_eswitch_disable(esw, false);
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err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_LEGACY);
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if (err) {
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NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
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@ -35,7 +35,7 @@
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static const unsigned int ESW_POOLS[] = { 4 * 1024 * 1024,
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1 * 1024 * 1024,
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64 * 1024,
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4 * 1024, };
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128 };
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struct mlx5_esw_chains_priv {
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struct rhashtable chains_ht;
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@ -2307,7 +2307,9 @@ static int dr_ste_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value,
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struct mlx5dr_cmd_vport_cap *vport_cap;
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struct mlx5dr_domain *dmn = sb->dmn;
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struct mlx5dr_cmd_caps *caps;
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u8 *bit_mask = sb->bit_mask;
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u8 *tag = hw_ste->tag;
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bool source_gvmi_set;
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DR_STE_SET_TAG(src_gvmi_qp, tag, source_qp, misc, source_sqn);
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@ -2328,7 +2330,8 @@ static int dr_ste_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value,
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if (!vport_cap)
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return -EINVAL;
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if (vport_cap->vport_gvmi)
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source_gvmi_set = MLX5_GET(ste_src_gvmi_qp, bit_mask, source_gvmi);
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if (vport_cap->vport_gvmi && source_gvmi_set)
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MLX5_SET(ste_src_gvmi_qp, tag, source_gvmi, vport_cap->vport_gvmi);
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misc->source_eswitch_owner_vhca_id = 0;
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@ -66,15 +66,20 @@ static int mlx5_cmd_dr_create_flow_table(struct mlx5_flow_root_namespace *ns,
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struct mlx5_flow_table *next_ft)
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{
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struct mlx5dr_table *tbl;
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u32 flags;
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int err;
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if (mlx5_dr_is_fw_table(ft->flags))
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return mlx5_fs_cmd_get_fw_cmds()->create_flow_table(ns, ft,
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log_size,
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next_ft);
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flags = ft->flags;
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/* turn off encap/decap if not supported for sw-str by fw */
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if (!MLX5_CAP_FLOWTABLE(ns->dev, sw_owner_reformat_supported))
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flags = ft->flags & ~(MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
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MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
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tbl = mlx5dr_table_create(ns->fs_dr_domain.dr_domain,
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ft->level, ft->flags);
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tbl = mlx5dr_table_create(ns->fs_dr_domain.dr_domain, ft->level, flags);
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if (!tbl) {
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mlx5_core_err(ns->dev, "Failed creating dr flow_table\n");
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return -EINVAL;
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@ -94,6 +94,13 @@ void mlx5_wq_cyc_wqe_dump(struct mlx5_wq_cyc *wq, u16 ix, u8 nstrides)
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print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, wqe, len, false);
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}
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void mlx5_wq_cyc_reset(struct mlx5_wq_cyc *wq)
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{
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wq->wqe_ctr = 0;
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wq->cur_sz = 0;
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mlx5_wq_cyc_update_db_record(wq);
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}
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int mlx5_wq_qp_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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void *qpc, struct mlx5_wq_qp *wq,
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struct mlx5_wq_ctrl *wq_ctrl)
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@ -192,6 +199,19 @@ err_db_free:
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return err;
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}
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static void mlx5_wq_ll_init_list(struct mlx5_wq_ll *wq)
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{
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struct mlx5_wqe_srq_next_seg *next_seg;
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int i;
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for (i = 0; i < wq->fbc.sz_m1; i++) {
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next_seg = mlx5_wq_ll_get_wqe(wq, i);
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next_seg->next_wqe_index = cpu_to_be16(i + 1);
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}
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next_seg = mlx5_wq_ll_get_wqe(wq, i);
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wq->tail_next = &next_seg->next_wqe_index;
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}
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int mlx5_wq_ll_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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void *wqc, struct mlx5_wq_ll *wq,
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struct mlx5_wq_ctrl *wq_ctrl)
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@ -199,9 +219,7 @@ int mlx5_wq_ll_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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u8 log_wq_stride = MLX5_GET(wq, wqc, log_wq_stride);
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u8 log_wq_sz = MLX5_GET(wq, wqc, log_wq_sz);
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struct mlx5_frag_buf_ctrl *fbc = &wq->fbc;
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struct mlx5_wqe_srq_next_seg *next_seg;
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int err;
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int i;
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err = mlx5_db_alloc_node(mdev, &wq_ctrl->db, param->db_numa_node);
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if (err) {
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@ -220,13 +238,7 @@ int mlx5_wq_ll_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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mlx5_init_fbc(wq_ctrl->buf.frags, log_wq_stride, log_wq_sz, fbc);
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for (i = 0; i < fbc->sz_m1; i++) {
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next_seg = mlx5_wq_ll_get_wqe(wq, i);
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next_seg->next_wqe_index = cpu_to_be16(i + 1);
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}
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next_seg = mlx5_wq_ll_get_wqe(wq, i);
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wq->tail_next = &next_seg->next_wqe_index;
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mlx5_wq_ll_init_list(wq);
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wq_ctrl->mdev = mdev;
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return 0;
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@ -237,6 +249,15 @@ err_db_free:
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return err;
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}
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void mlx5_wq_ll_reset(struct mlx5_wq_ll *wq)
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{
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wq->head = 0;
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wq->wqe_ctr = 0;
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wq->cur_sz = 0;
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mlx5_wq_ll_init_list(wq);
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mlx5_wq_ll_update_db_record(wq);
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}
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void mlx5_wq_destroy(struct mlx5_wq_ctrl *wq_ctrl)
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{
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mlx5_frag_buf_free(wq_ctrl->mdev, &wq_ctrl->buf);
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@ -80,6 +80,7 @@ int mlx5_wq_cyc_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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void *wqc, struct mlx5_wq_cyc *wq,
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struct mlx5_wq_ctrl *wq_ctrl);
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void mlx5_wq_cyc_wqe_dump(struct mlx5_wq_cyc *wq, u16 ix, u8 nstrides);
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void mlx5_wq_cyc_reset(struct mlx5_wq_cyc *wq);
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int mlx5_wq_qp_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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void *qpc, struct mlx5_wq_qp *wq,
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@ -92,6 +93,7 @@ int mlx5_cqwq_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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int mlx5_wq_ll_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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void *wqc, struct mlx5_wq_ll *wq,
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struct mlx5_wq_ctrl *wq_ctrl);
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void mlx5_wq_ll_reset(struct mlx5_wq_ll *wq);
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void mlx5_wq_destroy(struct mlx5_wq_ctrl *wq_ctrl);
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@ -688,7 +688,10 @@ struct mlx5_ifc_flow_table_nic_cap_bits {
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u8 nic_rx_multi_path_tirs[0x1];
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u8 nic_rx_multi_path_tirs_fts[0x1];
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u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
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u8 reserved_at_3[0x1d];
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u8 reserved_at_3[0x4];
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u8 sw_owner_reformat_supported[0x1];
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u8 reserved_at_8[0x18];
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u8 encap_general_header[0x1];
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u8 reserved_at_21[0xa];
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u8 log_max_packet_reformat_context[0x5];
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