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Merge branch 'hns3-ethtool-dump' 

Salil Mehta says:

====================
Adds VF/PF PCIe reg dump(ethtool -d) support to HNS3 driver

This patchset adds VF/PF PCIe register dump support to HNS3 VF and PF
driver using "ethtool -d" command.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2018-12-03 15:26:34 -08:00
parent d1420bb995 ea4750caa0
commit 77ac327c54
4 changed files with 345 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

120
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
View File

@ -48,6 +48,62 @@ static const struct pci_device_id ae_algo_pci_tbl[] = {
MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
static const u32 cmdq_reg_addr_list[] = {HCLGE_CMDQ_TX_ADDR_L_REG,
HCLGE_CMDQ_TX_ADDR_H_REG,
HCLGE_CMDQ_TX_DEPTH_REG,
HCLGE_CMDQ_TX_TAIL_REG,
HCLGE_CMDQ_TX_HEAD_REG,
HCLGE_CMDQ_RX_ADDR_L_REG,
HCLGE_CMDQ_RX_ADDR_H_REG,
HCLGE_CMDQ_RX_DEPTH_REG,
HCLGE_CMDQ_RX_TAIL_REG,
HCLGE_CMDQ_RX_HEAD_REG,
HCLGE_VECTOR0_CMDQ_SRC_REG,
HCLGE_CMDQ_INTR_STS_REG,
HCLGE_CMDQ_INTR_EN_REG,
HCLGE_CMDQ_INTR_GEN_REG};
static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
HCLGE_VECTOR0_OTER_EN_REG,
HCLGE_MISC_RESET_STS_REG,
HCLGE_MISC_VECTOR_INT_STS,
HCLGE_GLOBAL_RESET_REG,
HCLGE_FUN_RST_ING,
HCLGE_GRO_EN_REG};
static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG,
HCLGE_RING_RX_ADDR_H_REG,
HCLGE_RING_RX_BD_NUM_REG,
HCLGE_RING_RX_BD_LENGTH_REG,
HCLGE_RING_RX_MERGE_EN_REG,
HCLGE_RING_RX_TAIL_REG,
HCLGE_RING_RX_HEAD_REG,
HCLGE_RING_RX_FBD_NUM_REG,
HCLGE_RING_RX_OFFSET_REG,
HCLGE_RING_RX_FBD_OFFSET_REG,
HCLGE_RING_RX_STASH_REG,
HCLGE_RING_RX_BD_ERR_REG,
HCLGE_RING_TX_ADDR_L_REG,
HCLGE_RING_TX_ADDR_H_REG,
HCLGE_RING_TX_BD_NUM_REG,
HCLGE_RING_TX_PRIORITY_REG,
HCLGE_RING_TX_TC_REG,
HCLGE_RING_TX_MERGE_EN_REG,
HCLGE_RING_TX_TAIL_REG,
HCLGE_RING_TX_HEAD_REG,
HCLGE_RING_TX_FBD_NUM_REG,
HCLGE_RING_TX_OFFSET_REG,
HCLGE_RING_TX_EBD_NUM_REG,
HCLGE_RING_TX_EBD_OFFSET_REG,
HCLGE_RING_TX_BD_ERR_REG,
HCLGE_RING_EN_REG};
static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG,
HCLGE_TQP_INTR_GL0_REG,
HCLGE_TQP_INTR_GL1_REG,
HCLGE_TQP_INTR_GL2_REG,
HCLGE_TQP_INTR_RL_REG};
static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
"App Loopback test",
"Serdes serial Loopback test",
@ -7637,8 +7693,15 @@ static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
return 0;
}
#define MAX_SEPARATE_NUM 4
#define SEPARATOR_VALUE 0xFFFFFFFF
#define REG_NUM_PER_LINE 4
#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
static int hclge_get_regs_len(struct hnae3_handle *handle)
{
int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
struct hnae3_knic_private_info *kinfo = &handle->kinfo;
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
u32 regs_num_32_bit, regs_num_64_bit;
@ -7651,15 +7714,25 @@ static int hclge_get_regs_len(struct hnae3_handle *handle)
return -EOPNOTSUPP;
}
return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps +
tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE +
regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
}
static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
void *data)
{
struct hnae3_knic_private_info *kinfo = &handle->kinfo;
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
u32 regs_num_32_bit, regs_num_64_bit;
int i, j, reg_um, separator_num;
u32 *reg = data;
int ret;
*version = hdev->fw_version;
@ -7671,16 +7744,53 @@ static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
return;
}
ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
/* fetching per-PF registers valus from PF PCIe register space */
reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
for (i = 0; i < reg_um; i++)
*reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
for (i = 0; i < separator_num; i++)
*reg++ = SEPARATOR_VALUE;
reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
for (i = 0; i < reg_um; i++)
*reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]);
for (i = 0; i < separator_num; i++)
*reg++ = SEPARATOR_VALUE;
reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
for (j = 0; j < kinfo->num_tqps; j++) {
for (i = 0; i < reg_um; i++)
*reg++ = hclge_read_dev(&hdev->hw,
ring_reg_addr_list[i] +
0x200 * j);
for (i = 0; i < separator_num; i++)
*reg++ = SEPARATOR_VALUE;
}
reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
for (j = 0; j < hdev->num_msi_used - 1; j++) {
for (i = 0; i < reg_um; i++)
*reg++ = hclge_read_dev(&hdev->hw,
tqp_intr_reg_addr_list[i] +
4 * j);
for (i = 0; i < separator_num; i++)
*reg++ = SEPARATOR_VALUE;
}
/* fetching PF common registers values from firmware */
ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg);
if (ret) {
dev_err(&hdev->pdev->dev,
"Get 32 bit register failed, ret = %d.\n", ret);
return;
}
data = (u32 *)data + regs_num_32_bit;
ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
data);
reg += regs_num_32_bit;
ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg);
if (ret)
dev_err(&hdev->pdev->dev,
"Get 64 bit register failed, ret = %d.\n", ret);

56
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
View File

@ -28,6 +28,62 @@
#define HCLGE_VECTOR_REG_OFFSET 0x4
#define HCLGE_VECTOR_VF_OFFSET 0x100000
#define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000
#define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004
#define HCLGE_CMDQ_TX_DEPTH_REG 0x27008
#define HCLGE_CMDQ_TX_TAIL_REG 0x27010
#define HCLGE_CMDQ_TX_HEAD_REG 0x27014
#define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018
#define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C
#define HCLGE_CMDQ_RX_DEPTH_REG 0x27020
#define HCLGE_CMDQ_RX_TAIL_REG 0x27024
#define HCLGE_CMDQ_RX_HEAD_REG 0x27028
#define HCLGE_CMDQ_INTR_SRC_REG 0x27100
#define HCLGE_CMDQ_INTR_STS_REG 0x27104
#define HCLGE_CMDQ_INTR_EN_REG 0x27108
#define HCLGE_CMDQ_INTR_GEN_REG 0x2710C
/* bar registers for common func */
#define HCLGE_VECTOR0_OTER_EN_REG 0x20600
#define HCLGE_RAS_OTHER_STS_REG 0x20B00
#define HCLGE_FUNC_RESET_STS_REG 0x20C00
#define HCLGE_GRO_EN_REG 0x28000
/* bar registers for rcb */
#define HCLGE_RING_RX_ADDR_L_REG 0x80000
#define HCLGE_RING_RX_ADDR_H_REG 0x80004
#define HCLGE_RING_RX_BD_NUM_REG 0x80008
#define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
#define HCLGE_RING_RX_MERGE_EN_REG 0x80014
#define HCLGE_RING_RX_TAIL_REG 0x80018
#define HCLGE_RING_RX_HEAD_REG 0x8001C
#define HCLGE_RING_RX_FBD_NUM_REG 0x80020
#define HCLGE_RING_RX_OFFSET_REG 0x80024
#define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
#define HCLGE_RING_RX_STASH_REG 0x80030
#define HCLGE_RING_RX_BD_ERR_REG 0x80034
#define HCLGE_RING_TX_ADDR_L_REG 0x80040
#define HCLGE_RING_TX_ADDR_H_REG 0x80044
#define HCLGE_RING_TX_BD_NUM_REG 0x80048
#define HCLGE_RING_TX_PRIORITY_REG 0x8004C
#define HCLGE_RING_TX_TC_REG 0x80050
#define HCLGE_RING_TX_MERGE_EN_REG 0x80054
#define HCLGE_RING_TX_TAIL_REG 0x80058
#define HCLGE_RING_TX_HEAD_REG 0x8005C
#define HCLGE_RING_TX_FBD_NUM_REG 0x80060
#define HCLGE_RING_TX_OFFSET_REG 0x80064
#define HCLGE_RING_TX_EBD_NUM_REG 0x80068
#define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
#define HCLGE_RING_TX_BD_ERR_REG 0x80074
#define HCLGE_RING_EN_REG 0x80090
/* bar registers for tqp interrupt */
#define HCLGE_TQP_INTR_CTRL_REG 0x20000
#define HCLGE_TQP_INTR_GL0_REG 0x20100
#define HCLGE_TQP_INTR_GL1_REG 0x20200
#define HCLGE_TQP_INTR_GL2_REG 0x20300
#define HCLGE_TQP_INTR_RL_REG 0x20900
#define HCLGE_RSS_IND_TBL_SIZE 512
#define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
#define HCLGE_RSS_KEY_SIZE 40

120
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
View File

@ -23,6 +23,58 @@ static const struct pci_device_id ae_algovf_pci_tbl[] = {
MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
HCLGEVF_CMDQ_TX_ADDR_H_REG,
HCLGEVF_CMDQ_TX_DEPTH_REG,
HCLGEVF_CMDQ_TX_TAIL_REG,
HCLGEVF_CMDQ_TX_HEAD_REG,
HCLGEVF_CMDQ_RX_ADDR_L_REG,
HCLGEVF_CMDQ_RX_ADDR_H_REG,
HCLGEVF_CMDQ_RX_DEPTH_REG,
HCLGEVF_CMDQ_RX_TAIL_REG,
HCLGEVF_CMDQ_RX_HEAD_REG,
HCLGEVF_VECTOR0_CMDQ_SRC_REG,
HCLGEVF_CMDQ_INTR_STS_REG,
HCLGEVF_CMDQ_INTR_EN_REG,
HCLGEVF_CMDQ_INTR_GEN_REG};
static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
HCLGEVF_RST_ING,
HCLGEVF_GRO_EN_REG};
static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
HCLGEVF_RING_RX_ADDR_H_REG,
HCLGEVF_RING_RX_BD_NUM_REG,
HCLGEVF_RING_RX_BD_LENGTH_REG,
HCLGEVF_RING_RX_MERGE_EN_REG,
HCLGEVF_RING_RX_TAIL_REG,
HCLGEVF_RING_RX_HEAD_REG,
HCLGEVF_RING_RX_FBD_NUM_REG,
HCLGEVF_RING_RX_OFFSET_REG,
HCLGEVF_RING_RX_FBD_OFFSET_REG,
HCLGEVF_RING_RX_STASH_REG,
HCLGEVF_RING_RX_BD_ERR_REG,
HCLGEVF_RING_TX_ADDR_L_REG,
HCLGEVF_RING_TX_ADDR_H_REG,
HCLGEVF_RING_TX_BD_NUM_REG,
HCLGEVF_RING_TX_PRIORITY_REG,
HCLGEVF_RING_TX_TC_REG,
HCLGEVF_RING_TX_MERGE_EN_REG,
HCLGEVF_RING_TX_TAIL_REG,
HCLGEVF_RING_TX_HEAD_REG,
HCLGEVF_RING_TX_FBD_NUM_REG,
HCLGEVF_RING_TX_OFFSET_REG,
HCLGEVF_RING_TX_EBD_NUM_REG,
HCLGEVF_RING_TX_EBD_OFFSET_REG,
HCLGEVF_RING_TX_BD_ERR_REG,
HCLGEVF_RING_EN_REG};
static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
HCLGEVF_TQP_INTR_GL0_REG,
HCLGEVF_TQP_INTR_GL1_REG,
HCLGEVF_TQP_INTR_GL2_REG,
HCLGEVF_TQP_INTR_RL_REG};
static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
struct hnae3_handle *handle)
{
@ -2473,6 +2525,72 @@ static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
return hdev->reset_count;
}
#define MAX_SEPARATE_NUM 4
#define SEPARATOR_VALUE 0xFFFFFFFF
#define REG_NUM_PER_LINE 4
#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
static int hclgevf_get_regs_len(struct hnae3_handle *handle)
{
int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
}
static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
void *data)
{
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
int i, j, reg_um, separator_num;
u32 *reg = data;
*version = hdev->fw_version;
/* fetching per-VF registers values from VF PCIe register space */
reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
for (i = 0; i < reg_um; i++)
*reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
for (i = 0; i < separator_num; i++)
*reg++ = SEPARATOR_VALUE;
reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
for (i = 0; i < reg_um; i++)
*reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
for (i = 0; i < separator_num; i++)
*reg++ = SEPARATOR_VALUE;
reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
for (j = 0; j < hdev->num_tqps; j++) {
for (i = 0; i < reg_um; i++)
*reg++ = hclgevf_read_dev(&hdev->hw,
ring_reg_addr_list[i] +
0x200 * j);
for (i = 0; i < separator_num; i++)
*reg++ = SEPARATOR_VALUE;
}
reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
for (j = 0; j < hdev->num_msi_used - 1; j++) {
for (i = 0; i < reg_um; i++)
*reg++ = hclgevf_read_dev(&hdev->hw,
tqp_intr_reg_addr_list[i] +
4 * j);
for (i = 0; i < separator_num; i++)
*reg++ = SEPARATOR_VALUE;
}
}
static const struct hnae3_ae_ops hclgevf_ops = {
.init_ae_dev = hclgevf_init_ae_dev,
.uninit_ae_dev = hclgevf_uninit_ae_dev,
@ -2514,6 +2632,8 @@ static const struct hnae3_ae_ops hclgevf_ops = {
.set_default_reset_request = hclgevf_set_def_reset_request,
.get_channels = hclgevf_get_channels,
.get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
.get_regs_len = hclgevf_get_regs_len,
.get_regs = hclgevf_get_regs,
.get_status = hclgevf_get_status,
.get_ksettings_an_result = hclgevf_get_ksettings_an_result,
.get_media_type = hclgevf_get_media_type,

54
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
View File

@ -27,6 +27,60 @@
#define HCLGEVF_VECTOR_REG_OFFSET 0x4
#define HCLGEVF_VECTOR_VF_OFFSET 0x100000
/* bar registers for cmdq */
#define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000
#define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004
#define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008
#define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010
#define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014
#define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018
#define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C
#define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020
#define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024
#define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028
#define HCLGEVF_CMDQ_INTR_SRC_REG 0x27100
#define HCLGEVF_CMDQ_INTR_STS_REG 0x27104
#define HCLGEVF_CMDQ_INTR_EN_REG 0x27108
#define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C
/* bar registers for common func */
#define HCLGEVF_GRO_EN_REG 0x28000
/* bar registers for rcb */
#define HCLGEVF_RING_RX_ADDR_L_REG 0x80000
#define HCLGEVF_RING_RX_ADDR_H_REG 0x80004
#define HCLGEVF_RING_RX_BD_NUM_REG 0x80008
#define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C
#define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014
#define HCLGEVF_RING_RX_TAIL_REG 0x80018
#define HCLGEVF_RING_RX_HEAD_REG 0x8001C
#define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020
#define HCLGEVF_RING_RX_OFFSET_REG 0x80024
#define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028
#define HCLGEVF_RING_RX_STASH_REG 0x80030
#define HCLGEVF_RING_RX_BD_ERR_REG 0x80034
#define HCLGEVF_RING_TX_ADDR_L_REG 0x80040
#define HCLGEVF_RING_TX_ADDR_H_REG 0x80044
#define HCLGEVF_RING_TX_BD_NUM_REG 0x80048
#define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C
#define HCLGEVF_RING_TX_TC_REG 0x80050
#define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054
#define HCLGEVF_RING_TX_TAIL_REG 0x80058
#define HCLGEVF_RING_TX_HEAD_REG 0x8005C
#define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060
#define HCLGEVF_RING_TX_OFFSET_REG 0x80064
#define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068
#define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070
#define HCLGEVF_RING_TX_BD_ERR_REG 0x80074
#define HCLGEVF_RING_EN_REG 0x80090
/* bar registers for tqp interrupt */
#define HCLGEVF_TQP_INTR_CTRL_REG 0x20000
#define HCLGEVF_TQP_INTR_GL0_REG 0x20100
#define HCLGEVF_TQP_INTR_GL1_REG 0x20200
#define HCLGEVF_TQP_INTR_GL2_REG 0x20300
#define HCLGEVF_TQP_INTR_RL_REG 0x20900
/* Vector0 interrupt CMDQ event source register(RW) */
#define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100
/* CMDQ register bits for RX event(=MBX event) */