Davinci: pinmux - use ioremap()
This patch modifies the pinmux implementation so as to ioremap() the pinmux register area on first use. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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bd80894704
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@ -1191,6 +1191,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
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.cpu_clks = da830_clks,
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.cpu_clks = da830_clks,
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.psc_bases = da830_psc_bases,
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.psc_bases = da830_psc_bases,
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.psc_bases_num = ARRAY_SIZE(da830_psc_bases),
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.psc_bases_num = ARRAY_SIZE(da830_psc_bases),
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.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
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.pinmux_pins = da830_pins,
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.pinmux_pins = da830_pins,
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.pinmux_pins_num = ARRAY_SIZE(da830_pins),
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.pinmux_pins_num = ARRAY_SIZE(da830_pins),
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.intc_base = DA8XX_CP_INTC_BASE,
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.intc_base = DA8XX_CP_INTC_BASE,
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@ -1213,7 +1214,5 @@ void __init da830_init(void)
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if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
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if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
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return;
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return;
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davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
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davinci_common_init(&davinci_soc_info_da830);
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davinci_common_init(&davinci_soc_info_da830);
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}
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}
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@ -1076,6 +1076,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
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.cpu_clks = da850_clks,
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.cpu_clks = da850_clks,
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.psc_bases = da850_psc_bases,
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.psc_bases = da850_psc_bases,
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.psc_bases_num = ARRAY_SIZE(da850_psc_bases),
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.psc_bases_num = ARRAY_SIZE(da850_psc_bases),
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.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
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.pinmux_pins = da850_pins,
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.pinmux_pins = da850_pins,
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.pinmux_pins_num = ARRAY_SIZE(da850_pins),
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.pinmux_pins_num = ARRAY_SIZE(da850_pins),
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.intc_base = DA8XX_CP_INTC_BASE,
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.intc_base = DA8XX_CP_INTC_BASE,
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@ -1106,8 +1107,6 @@ void __init da850_init(void)
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if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
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if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
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return;
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return;
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davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
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davinci_common_init(&davinci_soc_info_da850);
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davinci_common_init(&davinci_soc_info_da850);
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/*
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/*
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@ -844,7 +844,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
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.cpu_clks = dm355_clks,
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.cpu_clks = dm355_clks,
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.psc_bases = dm355_psc_bases,
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.psc_bases = dm355_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
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.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
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.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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.pinmux_pins = dm355_pins,
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.pinmux_pins = dm355_pins,
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.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
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.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
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.intc_base = DAVINCI_ARM_INTC_BASE,
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.intc_base = DAVINCI_ARM_INTC_BASE,
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@ -1049,7 +1049,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
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.cpu_clks = dm365_clks,
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.cpu_clks = dm365_clks,
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.psc_bases = dm365_psc_bases,
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.psc_bases = dm365_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
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.psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
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.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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.pinmux_pins = dm365_pins,
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.pinmux_pins = dm365_pins,
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.pinmux_pins_num = ARRAY_SIZE(dm365_pins),
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.pinmux_pins_num = ARRAY_SIZE(dm365_pins),
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.intc_base = DAVINCI_ARM_INTC_BASE,
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.intc_base = DAVINCI_ARM_INTC_BASE,
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@ -735,7 +735,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
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.cpu_clks = dm644x_clks,
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.cpu_clks = dm644x_clks,
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.psc_bases = dm644x_psc_bases,
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.psc_bases = dm644x_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
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.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
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.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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.pinmux_pins = dm644x_pins,
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.pinmux_pins = dm644x_pins,
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.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
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.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
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.intc_base = DAVINCI_ARM_INTC_BASE,
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.intc_base = DAVINCI_ARM_INTC_BASE,
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@ -819,7 +819,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
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.cpu_clks = dm646x_clks,
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.cpu_clks = dm646x_clks,
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.psc_bases = dm646x_psc_bases,
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.psc_bases = dm646x_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
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.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
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.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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.pinmux_pins = dm646x_pins,
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.pinmux_pins = dm646x_pins,
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.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
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.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
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.intc_base = DAVINCI_ARM_INTC_BASE,
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.intc_base = DAVINCI_ARM_INTC_BASE,
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@ -51,7 +51,7 @@ struct davinci_soc_info {
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struct clk_lookup *cpu_clks;
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struct clk_lookup *cpu_clks;
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u32 *psc_bases;
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u32 *psc_bases;
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unsigned long psc_bases_num;
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unsigned long psc_bases_num;
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void __iomem *pinmux_base;
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u32 pinmux_base;
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const struct mux_config *pinmux_pins;
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const struct mux_config *pinmux_pins;
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unsigned long pinmux_pins_num;
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unsigned long pinmux_pins_num;
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u32 intc_base;
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u32 intc_base;
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@ -22,6 +22,8 @@
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#include <mach/mux.h>
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#include <mach/mux.h>
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#include <mach/common.h>
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#include <mach/common.h>
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static void __iomem *pinmux_base;
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/*
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/*
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* Sets the DAVINCI MUX register based on the table
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* Sets the DAVINCI MUX register based on the table
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*/
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*/
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@ -29,14 +31,19 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
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{
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{
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static DEFINE_SPINLOCK(mux_spin_lock);
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static DEFINE_SPINLOCK(mux_spin_lock);
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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void __iomem *base = soc_info->pinmux_base;
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unsigned long flags;
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unsigned long flags;
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const struct mux_config *cfg;
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const struct mux_config *cfg;
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unsigned int reg_orig = 0, reg = 0;
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unsigned int reg_orig = 0, reg = 0;
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unsigned int mask, warn = 0;
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unsigned int mask, warn = 0;
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if (!soc_info->pinmux_pins)
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if (WARN_ON(!soc_info->pinmux_pins))
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BUG();
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return -ENODEV;
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if (!pinmux_base) {
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pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
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if (WARN_ON(!pinmux_base))
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return -ENOMEM;
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}
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if (index >= soc_info->pinmux_pins_num) {
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if (index >= soc_info->pinmux_pins_num) {
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printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
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printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
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@ -57,7 +64,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
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unsigned tmp1, tmp2;
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unsigned tmp1, tmp2;
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spin_lock_irqsave(&mux_spin_lock, flags);
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spin_lock_irqsave(&mux_spin_lock, flags);
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reg_orig = __raw_readl(base + cfg->mux_reg);
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reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
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mask = (cfg->mask << cfg->mask_offset);
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mask = (cfg->mask << cfg->mask_offset);
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tmp1 = reg_orig & mask;
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tmp1 = reg_orig & mask;
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@ -69,7 +76,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
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if (tmp1 != tmp2)
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if (tmp1 != tmp2)
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warn = 1;
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warn = 1;
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__raw_writel(reg, base + cfg->mux_reg);
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__raw_writel(reg, pinmux_base + cfg->mux_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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}
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}
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