[SPARC]: Add reboot_command[] extern decl to asm/system.h
Kill off some sparse warnings. Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -139,8 +139,6 @@ void cpu_idle(void)
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#endif
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#endif
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extern char reboot_command [];
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/* XXX cli/sti -> local_irq_xxx here, check this works once SMP is fixed. */
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/* XXX cli/sti -> local_irq_xxx here, check this works once SMP is fixed. */
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void machine_halt(void)
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void machine_halt(void)
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{
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{
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@ -114,8 +114,6 @@ void cpu_idle(void)
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}
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}
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}
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}
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extern char reboot_command [];
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void machine_halt(void)
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void machine_halt(void)
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{
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{
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sstate_halt();
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sstate_halt();
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@ -44,6 +44,8 @@ extern enum sparc_cpu sparc_cpu_model;
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#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
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#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
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extern char reboot_command[];
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extern struct thread_info *current_set[NR_CPUS];
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extern struct thread_info *current_set[NR_CPUS];
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extern unsigned long empty_bad_page;
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extern unsigned long empty_bad_page;
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@ -30,6 +30,8 @@ enum sparc_cpu {
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#define ARCH_SUN4C_SUN4 0
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#define ARCH_SUN4C_SUN4 0
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#define ARCH_SUN4 0
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#define ARCH_SUN4 0
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extern char reboot_command[];
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/* These are here in an effort to more fully work around Spitfire Errata
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/* These are here in an effort to more fully work around Spitfire Errata
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* #51. Essentially, if a memory barrier occurs soon after a mispredicted
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* #51. Essentially, if a memory barrier occurs soon after a mispredicted
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* branch, the chip can stop executing instructions until a trap occurs.
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* branch, the chip can stop executing instructions until a trap occurs.
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