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memory: tegra: Fix missed registers values latching 

Some of Memory Controller registers are shadowed and require latching in
order to copy assembly state into the active, MC_EMEM_ARB_CFG is one of
these registers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2019-04-12 01:12:47 +03:00 committed by Thierry Reding
parent cb2b58391e
commit 76b959a44c
1 changed files with 6 additions and 0 deletions
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6
drivers/memory/tegra/mc.c
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@ -51,6 +51,9 @@
#define MC_EMEM_ADR_CFG 0x54
#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
#define MC_TIMING_CONTROL 0xfc
#define MC_TIMING_UPDATE BIT(0)
static const struct of_device_id tegra_mc_of_match[] = {
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
@ -301,6 +304,9 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
writel(value, mc->regs + la->reg);
}
/* latch new values */
writel(MC_TIMING_UPDATE, mc->regs + MC_TIMING_CONTROL);
return 0;
}