ARM: dts: rockchip: add usb phys to Cortex-A9 socs
This adds the usbphy nodes to rk3066 and rk3188, which share the usb hosts in rk3xxx.dtsi and also enables it on boards based around these socs. The usb-phy itself is the same as used on the rk3288 already. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -202,6 +202,10 @@
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status = "okay";
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};
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&usbphy {
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status = "okay";
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};
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&wdt {
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status = "okay";
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};
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@ -460,6 +460,10 @@
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status = "okay";
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};
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&usbphy {
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status = "okay";
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};
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&usb_otg {
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status = "okay";
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};
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@ -169,6 +169,28 @@
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clock-names = "timer", "pclk";
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};
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usbphy: phy {
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compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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usbphy0: usb-phy0 {
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#phy-cells = <0>;
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reg = <0x17c>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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};
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usbphy1: usb-phy1 {
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#phy-cells = <0>;
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reg = <0x188>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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};
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3066a-pinctrl";
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rockchip,grf = <&grf>;
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@ -359,6 +359,10 @@
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status = "okay";
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};
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&usbphy {
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status = "okay";
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};
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&usb_host {
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status = "okay";
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};
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@ -130,6 +130,28 @@
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#reset-cells = <1>;
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};
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usbphy: phy {
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compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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usbphy0: usb-phy0 {
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#phy-cells = <0>;
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reg = <0x10c>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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};
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usbphy1: usb-phy1 {
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#phy-cells = <0>;
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reg = <0x11c>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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};
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3188-pinctrl";
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rockchip,grf = <&grf>;
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@ -177,6 +177,8 @@
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g-rx-fifo-size = <275>;
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g-tx-fifo-size = <256 128 128 64 64 32>;
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g-use-dma;
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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@ -187,6 +189,8 @@
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clocks = <&cru HCLK_OTG1>;
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clock-names = "otg";
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dr_mode = "host";
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phys = <&usbphy1>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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