[PATCH] SHPC: Cleanup SHPC register access
This patch cleans up the code to access SHPC working register sets. This patch has no functional changes. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Cc: Kristen Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Kenji Kaneshige
Greg Kroah-Hartman
parent
40abb96c51
commit
75d97c59a1
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@ -208,6 +208,49 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
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static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
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static int hpc_check_cmd_status(struct controller *ctrl);
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static inline u8 shpc_readb(struct controller *ctrl, int reg)
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{
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return readb(ctrl->hpc_ctlr_handle->creg + reg);
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}
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static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
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{
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writeb(val, ctrl->hpc_ctlr_handle->creg + reg);
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}
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static inline u16 shpc_readw(struct controller *ctrl, int reg)
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{
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return readw(ctrl->hpc_ctlr_handle->creg + reg);
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}
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static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
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{
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writew(val, ctrl->hpc_ctlr_handle->creg + reg);
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}
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static inline u32 shpc_readl(struct controller *ctrl, int reg)
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{
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return readl(ctrl->hpc_ctlr_handle->creg + reg);
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}
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static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
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{
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writel(val, ctrl->hpc_ctlr_handle->creg + reg);
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}
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static inline int shpc_indirect_read(struct controller *ctrl, int index,
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u32 *value)
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{
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int rc;
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u32 cap_offset = ctrl->cap_offset;
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struct pci_dev *pdev = ctrl->pci_dev;
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rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
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if (rc)
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return rc;
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return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
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}
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/* This is the interrupt polling timeout function. */
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static void int_poll_timeout(unsigned long lphp_ctlr)
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{
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@ -273,6 +316,7 @@ static inline int shpc_wait_cmd(struct controller *ctrl)
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static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
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{
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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u16 cmd_status;
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int retval = 0;
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u16 temp_word;
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@ -289,7 +333,7 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
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}
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for (i = 0; i < 10; i++) {
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cmd_status = readw(php_ctlr->creg + CMD_STATUS);
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cmd_status = shpc_readw(ctrl, CMD_STATUS);
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if (!(cmd_status & 0x1))
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break;
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@ -297,7 +341,7 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
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msleep(100);
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}
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cmd_status = readw(php_ctlr->creg + CMD_STATUS);
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cmd_status = shpc_readw(ctrl, CMD_STATUS);
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if (cmd_status & 0x1) {
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/* After 1 sec and and the controller is still busy */
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@ -314,7 +358,7 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
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* command.
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*/
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slot->ctrl->cmd_busy = 1;
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writew(temp_word, php_ctlr->creg + CMD);
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shpc_writew(ctrl, CMD, temp_word);
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/*
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* Wait for command completion.
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@ -338,7 +382,6 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
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static int hpc_check_cmd_status(struct controller *ctrl)
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{
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struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
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u16 cmd_status;
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int retval = 0;
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@ -349,7 +392,7 @@ static int hpc_check_cmd_status(struct controller *ctrl)
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return -1;
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}
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cmd_status = readw(php_ctlr->creg + CMD_STATUS) & 0x000F;
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cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
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switch (cmd_status >> 1) {
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case 0:
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@ -378,7 +421,7 @@ static int hpc_check_cmd_status(struct controller *ctrl)
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static int hpc_get_attention_status(struct slot *slot, u8 *status)
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{
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u16 slot_status;
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u8 atten_led_state;
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@ -390,7 +433,7 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status)
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return -1;
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}
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slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
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slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot));
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slot_status = (u16) slot_reg;
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atten_led_state = (slot_status & 0x0030) >> 4;
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@ -418,7 +461,7 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status)
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static int hpc_get_power_status(struct slot * slot, u8 *status)
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{
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u16 slot_status;
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u8 slot_state;
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@ -431,7 +474,7 @@ static int hpc_get_power_status(struct slot * slot, u8 *status)
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return -1;
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}
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slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
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slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot));
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slot_status = (u16) slot_reg;
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slot_state = (slot_status & 0x0003);
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@ -460,7 +503,7 @@ static int hpc_get_power_status(struct slot * slot, u8 *status)
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static int hpc_get_latch_status(struct slot *slot, u8 *status)
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{
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u16 slot_status;
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@ -471,7 +514,7 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status)
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return -1;
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}
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slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
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slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot));
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slot_status = (u16)slot_reg;
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*status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */
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@ -483,7 +526,7 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status)
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static int hpc_get_adapter_status(struct slot *slot, u8 *status)
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{
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u16 slot_status;
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u8 card_state;
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@ -495,7 +538,7 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status)
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return -1;
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}
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slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
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slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot));
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slot_status = (u16)slot_reg;
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card_state = (u8)((slot_status & 0x0C00) >> 10);
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*status = (card_state != 0x3) ? 1 : 0;
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@ -506,7 +549,7 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status)
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static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
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{
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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DBG_ENTER_ROUTINE
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@ -515,7 +558,7 @@ static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
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return -1;
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}
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*prog_int = readb(php_ctlr->creg + PROG_INTERFACE);
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*prog_int = shpc_readb(ctrl, PROG_INTERFACE);
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DBG_LEAVE_ROUTINE
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return 0;
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@ -524,8 +567,8 @@ static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
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static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
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{
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int retval = 0;
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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u32 slot_reg = readl(php_ctlr->creg + SLOT1 + 4 * slot->hp_slot);
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg = shpc_readl(ctrl, SLOT1 + 4 * slot->hp_slot);
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u8 pcix_cap = (slot_reg >> 12) & 7;
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u8 m66_cap = (slot_reg >> 9) & 1;
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@ -564,7 +607,7 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
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static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
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{
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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u16 sec_bus_status;
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u8 pi;
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int retval = 0;
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@ -576,8 +619,8 @@ static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
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return -1;
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}
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pi = readb(php_ctlr->creg + PROG_INTERFACE);
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sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
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pi = shpc_readb(ctrl, PROG_INTERFACE);
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sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
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if (pi == 2) {
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*mode = (sec_bus_status & 0x0100) >> 8;
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@ -593,7 +636,7 @@ static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
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static int hpc_query_power_fault(struct slot * slot)
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{
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u16 slot_status;
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u8 pwr_fault_state, status;
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@ -605,7 +648,7 @@ static int hpc_query_power_fault(struct slot * slot)
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return -1;
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}
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slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
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slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot));
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slot_status = (u16) slot_reg;
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pwr_fault_state = (slot_status & 0x0040) >> 7;
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status = (pwr_fault_state == 1) ? 0 : 1;
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@ -724,7 +767,7 @@ int shpc_get_ctlr_slot_config(struct controller *ctrl,
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int *updown, /* physical_slot_num increament: 1 or -1 */
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int *flags)
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{
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struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
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u32 slot_config;
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DBG_ENTER_ROUTINE
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@ -733,12 +776,13 @@ int shpc_get_ctlr_slot_config(struct controller *ctrl,
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return -1;
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}
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*first_device_num = php_ctlr->slot_device_offset; /* Obtained in shpc_init() */
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*num_ctlr_slots = php_ctlr->num_slots; /* Obtained in shpc_init() */
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slot_config = shpc_readl(ctrl, SLOT_CONFIG);
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*first_device_num = (slot_config & FIRST_DEV_NUM) >> 8;
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*num_ctlr_slots = slot_config & SLOT_NUM;
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*physical_slot_num = (slot_config & PSN) >> 16;
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*updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
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*physical_slot_num = (readl(php_ctlr->creg + SLOT_CONFIG) & PSN) >> 16;
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dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
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*updown = ((readl(php_ctlr->creg + SLOT_CONFIG) & UPDOWN ) >> 29) ? 1 : -1;
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DBG_LEAVE_ROUTINE
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return 0;
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@ -761,7 +805,7 @@ static void hpc_release_ctlr(struct controller *ctrl)
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* Mask all slot event interrupts
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*/
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for (i = 0; i < ctrl->num_slots; i++)
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writel(0xffff3fff, php_ctlr->creg + SLOT1 + (4 * i));
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shpc_writel(ctrl, SLOT1 + (4 * i), 0xffff3fff);
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cleanup_slots(ctrl);
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@ -901,12 +945,12 @@ static int hpc_slot_disable(struct slot * slot)
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static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
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{
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int retval;
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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u8 pi, cmd;
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DBG_ENTER_ROUTINE
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pi = readb(php_ctlr->creg + PROG_INTERFACE);
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pi = shpc_readb(ctrl, PROG_INTERFACE);
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if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
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return -EINVAL;
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@ -992,7 +1036,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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return IRQ_NONE;
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/* Check to see if it was our interrupt */
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intr_loc = readl(php_ctlr->creg + INTR_LOC);
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intr_loc = shpc_readl(ctrl, INTR_LOC);
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if (!intr_loc)
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return IRQ_NONE;
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@ -1001,11 +1045,11 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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if(!shpchp_poll_mode) {
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/* Mask Global Interrupt Mask - see implementation note on p. 139 */
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/* of SHPC spec rev 1.0*/
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temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
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temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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temp_dword |= 0x00000001;
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writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
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shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
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intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
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intr_loc2 = shpc_readl(ctrl, INTR_LOC);
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dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
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}
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@ -1015,9 +1059,9 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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* RO only - clear by writing 1 to the Command Completion
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* Detect bit in Controller SERR-INT register
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*/
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temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
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temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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temp_dword &= 0xfffdffff;
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writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
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shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
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ctrl->cmd_busy = 0;
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wake_up_interruptible(&ctrl->queue);
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}
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@ -1028,7 +1072,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
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/* To find out which slot has interrupt pending */
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if ((intr_loc >> hp_slot) & 0x01) {
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temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot));
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temp_dword = shpc_readl(ctrl, SLOT1 + (4*hp_slot));
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dbg("%s: Slot %x with intr, slot register = %x\n",
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__FUNCTION__, hp_slot, temp_dword);
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temp_byte = (temp_dword >> 16) & 0xFF;
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@ -1047,18 +1091,18 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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/* Clear all slot events */
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temp_dword = 0xe01f3fff;
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writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot));
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shpc_writel(ctrl, SLOT1 + (4*hp_slot), temp_dword);
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intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
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intr_loc2 = shpc_readl(ctrl, INTR_LOC);
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dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
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}
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}
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out:
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if (!shpchp_poll_mode) {
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/* Unmask Global Interrupt Mask */
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temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
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temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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temp_dword &= 0xfffffffe;
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writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
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shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
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}
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return IRQ_HANDLED;
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@ -1067,11 +1111,11 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
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{
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int retval = 0;
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct controller *ctrl = slot->ctrl;
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enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
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u8 pi = readb(php_ctlr->creg + PROG_INTERFACE);
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u32 slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
|
||||
u32 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
|
||||
u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
|
||||
u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
|
||||
u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
|
||||
|
||||
DBG_ENTER_ROUTINE
|
||||
|
||||
|
|
@ -1114,10 +1158,10 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
|
|||
static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
|
||||
{
|
||||
int retval = 0;
|
||||
struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
|
||||
struct controller *ctrl = slot->ctrl;
|
||||
enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
|
||||
u16 sec_bus_reg = readw(php_ctlr->creg + SEC_BUS_CONFIG);
|
||||
u8 pi = readb(php_ctlr->creg + PROG_INTERFACE);
|
||||
u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
|
||||
u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
|
||||
u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
|
||||
|
||||
DBG_ENTER_ROUTINE
|
||||
|
|
@ -1206,19 +1250,6 @@ static struct hpc_ops shpchp_hpc_ops = {
|
|||
.release_ctlr = hpc_release_ctlr,
|
||||
};
|
||||
|
||||
inline static int shpc_indirect_creg_read(struct controller *ctrl, int index,
|
||||
u32 *value)
|
||||
{
|
||||
int rc;
|
||||
u32 cap_offset = ctrl->cap_offset;
|
||||
struct pci_dev *pdev = ctrl->pci_dev;
|
||||
|
||||
rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
|
||||
if (rc)
|
||||
return rc;
|
||||
return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
|
||||
}
|
||||
|
||||
int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
|
||||
{
|
||||
struct php_ctlr_state_s *php_ctlr, *p;
|
||||
|
|
@ -1227,7 +1258,7 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
|
|||
u8 hp_slot;
|
||||
static int first = 1;
|
||||
u32 shpc_base_offset;
|
||||
u32 tempdword, slot_reg;
|
||||
u32 tempdword, slot_reg, slot_config;
|
||||
u8 i;
|
||||
|
||||
DBG_ENTER_ROUTINE
|
||||
|
|
@ -1257,13 +1288,13 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
|
|||
}
|
||||
dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
|
||||
|
||||
rc = shpc_indirect_creg_read(ctrl, 0, &shpc_base_offset);
|
||||
rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
|
||||
if (rc) {
|
||||
err("%s: cannot read base_offset\n", __FUNCTION__);
|
||||
goto abort_free_ctlr;
|
||||
}
|
||||
|
||||
rc = shpc_indirect_creg_read(ctrl, 3, &tempdword);
|
||||
rc = shpc_indirect_read(ctrl, 3, &tempdword);
|
||||
if (rc) {
|
||||
err("%s: cannot read slot config\n", __FUNCTION__);
|
||||
goto abort_free_ctlr;
|
||||
|
|
@ -1272,7 +1303,7 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
|
|||
dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
|
||||
|
||||
for (i = 0; i < 9 + num_slots; i++) {
|
||||
rc = shpc_indirect_creg_read(ctrl, i, &tempdword);
|
||||
rc = shpc_indirect_read(ctrl, i, &tempdword);
|
||||
if (rc) {
|
||||
err("%s: cannot read creg (index = %d)\n",
|
||||
__FUNCTION__, i);
|
||||
|
|
@ -1326,29 +1357,33 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
|
|||
php_ctlr->power_fault_callback = shpchp_handle_power_fault;
|
||||
php_ctlr->callback_instance_id = instance_id;
|
||||
|
||||
ctrl->hpc_ctlr_handle = php_ctlr;
|
||||
ctrl->hpc_ops = &shpchp_hpc_ops;
|
||||
|
||||
/* Return PCI Controller Info */
|
||||
php_ctlr->slot_device_offset = (readl(php_ctlr->creg + SLOT_CONFIG) & FIRST_DEV_NUM ) >> 8;
|
||||
php_ctlr->num_slots = readl(php_ctlr->creg + SLOT_CONFIG) & SLOT_NUM;
|
||||
slot_config = shpc_readl(ctrl, SLOT_CONFIG);
|
||||
php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
|
||||
php_ctlr->num_slots = slot_config & SLOT_NUM;
|
||||
dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
|
||||
dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
|
||||
|
||||
/* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
|
||||
tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
|
||||
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
||||
dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
|
||||
tempdword = 0x0003000f;
|
||||
writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
|
||||
tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
|
||||
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
|
||||
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
||||
dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
|
||||
|
||||
/* Mask the MRL sensor SERR Mask of individual slot in
|
||||
* Slot SERR-INT Mask & clear all the existing event if any
|
||||
*/
|
||||
for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
|
||||
slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
|
||||
slot_reg = shpc_readl(ctrl, SLOT1 + 4*hp_slot );
|
||||
dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
|
||||
hp_slot, slot_reg);
|
||||
tempdword = 0xffff3fff;
|
||||
writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
|
||||
shpc_writel(ctrl, SLOT1 + (4*hp_slot), tempdword);
|
||||
}
|
||||
|
||||
if (shpchp_poll_mode) {/* Install interrupt polling code */
|
||||
|
|
@ -1392,24 +1427,21 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
|
|||
}
|
||||
spin_unlock(&list_lock);
|
||||
|
||||
|
||||
ctlr_seq_num++;
|
||||
ctrl->hpc_ctlr_handle = php_ctlr;
|
||||
ctrl->hpc_ops = &shpchp_hpc_ops;
|
||||
|
||||
for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
|
||||
slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
|
||||
slot_reg = shpc_readl(ctrl, SLOT1 + 4*hp_slot );
|
||||
dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
|
||||
hp_slot, slot_reg);
|
||||
tempdword = 0xe01f3fff;
|
||||
writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
|
||||
shpc_writel(ctrl, SLOT1 + (4*hp_slot), tempdword);
|
||||
}
|
||||
if (!shpchp_poll_mode) {
|
||||
/* Unmask all general input interrupts and SERR */
|
||||
tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
|
||||
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
||||
tempdword = 0x0000000a;
|
||||
writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
|
||||
tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
|
||||
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
|
||||
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
|
||||
dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue