ARM: SoC fixes for 3.16-rc
This week's arm-soc fixes: - A set of of OMAP patches that we had missed Tony's pull request of: - Reset fix for am43xx - Proper OPP table for omap5 - Fix for SoC detection of one of the DRA7 SoCs - hwmod updates to get SATA and OCP to work on omap5 (drivers merged in 3.16) - ... plus a handful of smaller fixes - sunxi needed to re-add machine specific restart code that was removed in anticipation of a watchdog driver being merged for 3.16, and it didn't make it in. - Marvell fixes for PCIe on SMP and a big-endian fix. - A trivial defconfig update to make my capri test board boot with bcm_defconfig again. ... and a couple of MAINTAINERS updates, one to claim new Keystone drivers that have been merged, and one to merge MXS and i.MX (both Freescale platforms). The largest diffs come from the hwmod code for omap5 and the re-add of the restart code on sunxi. The hwmod stuff is quite late at this point but it slipped through cracks repeatedly while coming up the maintainer chain and only affects the one SoC so risk is low. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTuFXOAAoJEIwa5zzehBx30dYQAJ2jfunXR0R4BldQw7UzYoob 3ht/tgIRglMcGIGbdvwRznOjjAsZTTssUzZvCvdU/B5ckILg7FCsaHFo6eYhB0NE bvxpMD1XyfO2JPF1r7jQqQsuwUXWtyAnkxFiuFkeBnriwo69ikbZnPb5g0bcMaXx HzPZoSoODn9g2vbgEH3jL3+AClWvHgJ7lXQxUSH9xvCqjqQjiwFx8l6QY/+qgkde QuRfZ0UCBuRFpTdR4jfvTIO4mctD6ObfaRRiQpzIQPa8HDGcWmD2LJm+IeCdclFv PwINZnf5aICz+CEJa8oo7tyKpEUNQwJL2YPesCXeRnVxcCHMn0UCDuZ3Z2MR3C8I w21msVS+bxr+tisj7QY3KCi73DMlTjOPj21OaPrpTAjDI/5tZxTCCvCWctg0aF4S HKKETWtrWhN6qiIpkKalCcr6CHlqf9p7QOz7d4yzE89O3thyg7YrRff7KOCtoaZo +aJnW7Z3gTuJFWTpAOQL+DeRQsY0ZpYqG6wVc8bIgM+vYYPBJO7mGa2ARBiz4Piw a+iEOP3ej8uqa60YfehXRS/YTGnOVkUf9Qk4zmyKjyoXSNhasQDHG/ujb7/hxzpd Lq4X2CkLZTOX+kjlXWD7kk3OBhIxdu38UtWPomd3QVZqEg7dCYxQooXuiidqYQ9x xquFfKAuIJlvBzVpWIbz =J9xD -----END PGP SIGNATURE----- Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "This week's arm-soc fixes: - A set of of OMAP patches that we had missed Tony's pull request of: * Reset fix for am43xx * Proper OPP table for omap5 * Fix for SoC detection of one of the DRA7 SoCs * hwmod updates to get SATA and OCP to work on omap5 (drivers merged in 3.16) * ... plus a handful of smaller fixes - sunxi needed to re-add machine specific restart code that was removed in anticipation of a watchdog driver being merged for 3.16, and it didn't make it in. - Marvell fixes for PCIe on SMP and a big-endian fix. - A trivial defconfig update to make my capri test board boot with bcm_defconfig again. ... and a couple of MAINTAINERS updates, one to claim new Keystone drivers that have been merged, and one to merge MXS and i.MX (both Freescale platforms). The largest diffs come from the hwmod code for omap5 and the re-add of the restart code on sunxi. The hwmod stuff is quite late at this point but it slipped through cracks repeatedly while coming up the maintainer chain and only affects the one SoC so risk is low" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: MAINTAINERS: Add few more Keystone drivers MAINTAINERS: merge MXS entry into IMX one ARM: sunxi: Reintroduce the restart code for A10/A20 SoCs ARM: mvebu: fix cpuidle implementation to work on big-endian systems ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup ARM: mvebu: move Armada 375 external abort logic as a quirk ARM: bcm: Fix bcm and multi_v7 defconfigs ARM: dts: dra7-evm: remove interrupt binding ARM: OMAP2+: Fix parser-bug in platform muxing code ARM: DTS: dra7/dra7xx-clocks: ATL related changes ARM: OMAP2+: drop unused function ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm ARM: dts: omap5: Update CPU OPP table as per final production Manual ARM: DRA722: add detection of SoC information ARM: dts: Enable twl4030 off-idle configuration for selected omaps ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX
This commit is contained in:
commit
75bf757edc
34
MAINTAINERS
34
MAINTAINERS
|
@ -943,16 +943,10 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
|||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
|
||||
F: arch/arm/mach-imx/
|
||||
F: arch/arm/mach-mxs/
|
||||
F: arch/arm/boot/dts/imx*
|
||||
F: arch/arm/configs/imx*_defconfig
|
||||
|
||||
ARM/FREESCALE MXS ARM ARCHITECTURE
|
||||
M: Shawn Guo <shawn.guo@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
|
||||
F: arch/arm/mach-mxs/
|
||||
|
||||
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
@ -1052,9 +1046,33 @@ M: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
|||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-keystone/
|
||||
F: drivers/clk/keystone/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
|
||||
|
||||
ARM/TEXAS INSTRUMENT KEYSTONE CLOCK FRAMEWORK
|
||||
M: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/clk/keystone/
|
||||
|
||||
ARM/TEXAS INSTRUMENT KEYSTONE ClOCKSOURCE
|
||||
M: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/clocksource/timer-keystone.c
|
||||
|
||||
ARM/TEXAS INSTRUMENT KEYSTONE RESET DRIVER
|
||||
M: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/power/reset/keystone-reset.c
|
||||
|
||||
ARM/TEXAS INSTRUMENT AEMIF/EMIF DRIVERS
|
||||
M: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/memory/*emif*
|
||||
|
||||
ARM/LOGICPD PXA270 MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
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||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
|
@ -319,6 +319,10 @@
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|||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
&phy_sel {
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rmii-clock-ext;
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};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
|
@ -773,7 +773,6 @@
|
|||
clocks = <&qspi_gfclk_div>;
|
||||
clock-names = "fck";
|
||||
num-cs = <4>;
|
||||
interrupts = <0 343 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -984,6 +983,17 @@
|
|||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
atl: atl@4843c000 {
|
||||
compatible = "ti,dra7-atl";
|
||||
reg = <0x4843c000 0x3ff>;
|
||||
ti,hwmods = "atl";
|
||||
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
|
||||
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -10,26 +10,26 @@
|
|||
&cm_core_aon_clocks {
|
||||
atl_clkin0_ck: atl_clkin0_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
atl_clkin1_ck: atl_clkin1_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
atl_clkin2_ck: atl_clkin2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
atl_clkin3_ck: atl_clkin3_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
hdmi_clkin_ck: hdmi_clkin_ck {
|
||||
|
|
|
@ -251,6 +251,11 @@
|
|||
codec {
|
||||
};
|
||||
};
|
||||
|
||||
twl_power: power {
|
||||
compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off";
|
||||
ti,use_poweroff;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -301,6 +306,7 @@
|
|||
};
|
||||
|
||||
&uart3 {
|
||||
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
};
|
||||
|
|
|
@ -50,6 +50,13 @@
|
|||
gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&twl {
|
||||
twl_power: power {
|
||||
compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle";
|
||||
ti,use_poweroff;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
|
|
@ -351,6 +351,11 @@
|
|||
compatible = "ti,twl4030-audio";
|
||||
ti,enable-vibra = <1>;
|
||||
};
|
||||
|
||||
twl_power: power {
|
||||
compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
|
||||
ti,use_poweroff;
|
||||
};
|
||||
};
|
||||
|
||||
&twl_keypad {
|
||||
|
|
|
@ -45,7 +45,6 @@
|
|||
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
500000 880000
|
||||
1000000 1060000
|
||||
1500000 1250000
|
||||
>;
|
||||
|
|
|
@ -94,10 +94,10 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
|||
CONFIG_BACKLIGHT_PWM=y
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_TEST=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_BCM_KONA=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
|
|
|
@ -223,12 +223,12 @@ CONFIG_POWER_RESET_GPIO=y
|
|||
CONFIG_POWER_RESET_SUN6I=y
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_DOVE_THERMAL=y
|
||||
CONFIG_ARMADA_THERMAL=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_ORION_WATCHDOG=y
|
||||
CONFIG_SUNXI_WATCHDOG=y
|
||||
CONFIG_MFD_AS3722=y
|
||||
CONFIG_MFD_BCM590XX=y
|
||||
CONFIG_MFD_CROS_EC=y
|
||||
CONFIG_MFD_CROS_EC_SPI=y
|
||||
CONFIG_MFD_MAX8907=y
|
||||
|
@ -240,6 +240,7 @@ CONFIG_MFD_TPS65910=y
|
|||
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
|
||||
CONFIG_REGULATOR_AB8500=y
|
||||
CONFIG_REGULATOR_AS3722=y
|
||||
CONFIG_REGULATOR_BCM590XX=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_MAX8907=y
|
||||
CONFIG_REGULATOR_PALMAS=y
|
||||
|
|
|
@ -7,7 +7,7 @@ CFLAGS_pmsu.o := -march=armv7-a
|
|||
obj-y += system-controller.o mvebu-soc-id.o
|
||||
|
||||
ifeq ($(CONFIG_MACH_MVEBU_V7),y)
|
||||
obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o
|
||||
obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
endif
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/mbus.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -71,15 +72,21 @@ static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
|
|||
return 1;
|
||||
}
|
||||
|
||||
static void __init mvebu_timer_and_clk_init(void)
|
||||
static void __init mvebu_init_irq(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
clocksource_of_init();
|
||||
irqchip_init();
|
||||
mvebu_scu_enable();
|
||||
coherency_init();
|
||||
BUG_ON(mvebu_mbus_dt_init(coherency_available()));
|
||||
}
|
||||
|
||||
static void __init external_abort_quirk(void)
|
||||
{
|
||||
u32 dev, rev;
|
||||
|
||||
if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
|
||||
return;
|
||||
|
||||
if (of_machine_is_compatible("marvell,armada375"))
|
||||
hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
|
||||
"imprecise external abort");
|
||||
}
|
||||
|
@ -169,8 +176,10 @@ static void __init mvebu_dt_init(void)
|
|||
{
|
||||
if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
|
||||
i2c_quirk();
|
||||
if (of_machine_is_compatible("marvell,a375-db"))
|
||||
if (of_machine_is_compatible("marvell,a375-db")) {
|
||||
external_abort_quirk();
|
||||
thermal_quirk();
|
||||
}
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
@ -185,7 +194,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
|
|||
.l2c_aux_mask = ~0,
|
||||
.smp = smp_ops(armada_xp_smp_ops),
|
||||
.init_machine = mvebu_dt_init,
|
||||
.init_time = mvebu_timer_and_clk_init,
|
||||
.init_irq = mvebu_init_irq,
|
||||
.restart = mvebu_restart,
|
||||
.dt_compat = armada_370_xp_dt_compat,
|
||||
MACHINE_END
|
||||
|
@ -198,7 +207,7 @@ static const char * const armada_375_dt_compat[] = {
|
|||
DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
.init_time = mvebu_timer_and_clk_init,
|
||||
.init_irq = mvebu_init_irq,
|
||||
.init_machine = mvebu_dt_init,
|
||||
.restart = mvebu_restart,
|
||||
.dt_compat = armada_375_dt_compat,
|
||||
|
@ -213,7 +222,7 @@ static const char * const armada_38x_dt_compat[] = {
|
|||
DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
.init_time = mvebu_timer_and_clk_init,
|
||||
.init_irq = mvebu_init_irq,
|
||||
.restart = mvebu_restart,
|
||||
.dt_compat = armada_38x_dt_compat,
|
||||
MACHINE_END
|
||||
|
|
|
@ -66,6 +66,8 @@ static void __iomem *pmsu_mp_base;
|
|||
extern void ll_disable_coherency(void);
|
||||
extern void ll_enable_coherency(void);
|
||||
|
||||
extern void armada_370_xp_cpu_resume(void);
|
||||
|
||||
static struct platform_device armada_xp_cpuidle_device = {
|
||||
.name = "cpuidle-armada-370-xp",
|
||||
};
|
||||
|
@ -140,13 +142,6 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
|
|||
writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
|
||||
}
|
||||
|
||||
static void armada_370_xp_cpu_resume(void)
|
||||
{
|
||||
asm volatile("bl ll_add_cpu_to_smp_group\n\t"
|
||||
"bl ll_enable_coherency\n\t"
|
||||
"b cpu_resume\n\t");
|
||||
}
|
||||
|
||||
/* No locking is needed because we only access per-CPU registers */
|
||||
void armada_370_xp_pmsu_idle_prepare(bool deepidle)
|
||||
{
|
||||
|
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
* Gregory Clement <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
|
||||
/*
|
||||
* This is the entry point through which CPUs exiting cpuidle deep
|
||||
* idle state are going.
|
||||
*/
|
||||
ENTRY(armada_370_xp_cpu_resume)
|
||||
ARM_BE8(setend be ) @ go BE8 if entered LE
|
||||
bl ll_add_cpu_to_smp_group
|
||||
bl ll_enable_coherency
|
||||
b cpu_resume
|
||||
ENDPROC(armada_370_xp_cpu_resume)
|
||||
|
|
@ -110,14 +110,16 @@ obj-y += prm_common.o cm_common.o
|
|||
obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
|
||||
obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
|
||||
omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
|
||||
prcm_mpu44xx.o prminst44xx.o \
|
||||
vc44xx_data.o vp44xx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
|
||||
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
|
||||
obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
|
||||
obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common)
|
||||
am33xx-43xx-prcm-common += prm33xx.o cm33xx.o
|
||||
obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common)
|
||||
obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
|
||||
$(am33xx-43xx-prcm-common)
|
||||
|
||||
# OMAP voltage domains
|
||||
voltagedomain-common := voltage.o vc.o vp.o
|
||||
|
|
|
@ -380,7 +380,7 @@ void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
|
|||
void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
|
||||
void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
|
||||
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
|
||||
extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
|
||||
u16 clkctrl_offs);
|
||||
extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
|
||||
|
|
|
@ -248,7 +248,6 @@ static inline void __iomem *omap4_get_scu_base(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
extern void __init gic_init_irq(void);
|
||||
extern void gic_dist_disable(void);
|
||||
extern void gic_dist_enable(void);
|
||||
extern bool gic_dist_disabled(void);
|
||||
|
|
|
@ -649,6 +649,18 @@ void __init dra7xxx_check_revision(void)
|
|||
}
|
||||
break;
|
||||
|
||||
case 0xb9bc:
|
||||
switch (rev) {
|
||||
case 0:
|
||||
omap_revision = DRA722_REV_ES1_0;
|
||||
break;
|
||||
default:
|
||||
/* If we have no new revisions */
|
||||
omap_revision = DRA722_REV_ES1_0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Unknown default to latest silicon rev as default*/
|
||||
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
|
||||
|
|
|
@ -183,7 +183,9 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
|
|||
m0_entry = mux->muxnames[0];
|
||||
|
||||
/* First check for full name in mode0.muxmode format */
|
||||
if (mode0_len && strncmp(muxname, m0_entry, mode0_len))
|
||||
if (mode0_len)
|
||||
if (strncmp(muxname, m0_entry, mode0_len) ||
|
||||
(strlen(m0_entry) != mode0_len))
|
||||
continue;
|
||||
|
||||
/* Then check for muxmode only */
|
||||
|
|
|
@ -102,26 +102,6 @@ void __init omap_barriers_init(void)
|
|||
{}
|
||||
#endif
|
||||
|
||||
void __init gic_init_irq(void)
|
||||
{
|
||||
void __iomem *omap_irq_base;
|
||||
|
||||
/* Static mapping, never released */
|
||||
gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
|
||||
BUG_ON(!gic_dist_base_addr);
|
||||
|
||||
twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
|
||||
BUG_ON(!twd_base);
|
||||
|
||||
/* Static mapping, never released */
|
||||
omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
|
||||
BUG_ON(!omap_irq_base);
|
||||
|
||||
omap_wakeupgen_init();
|
||||
|
||||
gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
|
||||
}
|
||||
|
||||
void gic_dist_disable(void)
|
||||
{
|
||||
if (gic_dist_base_addr)
|
||||
|
|
|
@ -4251,9 +4251,9 @@ void __init omap_hwmod_init(void)
|
|||
soc_ops.enable_module = _omap4_enable_module;
|
||||
soc_ops.disable_module = _omap4_disable_module;
|
||||
soc_ops.wait_target_ready = _omap4_wait_target_ready;
|
||||
soc_ops.assert_hardreset = _omap4_assert_hardreset;
|
||||
soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
|
||||
soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
|
||||
soc_ops.assert_hardreset = _am33xx_assert_hardreset;
|
||||
soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
|
||||
soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
|
||||
soc_ops.init_clkdm = _init_clkdm;
|
||||
} else if (soc_is_am33xx()) {
|
||||
soc_ops.enable_module = _am33xx_enable_module;
|
||||
|
|
|
@ -2020,6 +2020,77 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
|
|||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'ocp2scp' class
|
||||
* bridge to transform ocp interface protocol to scp (serial control port)
|
||||
* protocol
|
||||
*/
|
||||
/* ocp2scp3 */
|
||||
static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
|
||||
/* l4_cfg -> ocp2scp3 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
|
||||
.master = &omap54xx_l4_cfg_hwmod,
|
||||
.slave = &omap54xx_ocp2scp3_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
|
||||
.name = "ocp2scp3",
|
||||
.class = &omap54xx_ocp2scp_hwmod_class,
|
||||
.clkdm_name = "l3init_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'sata' class
|
||||
* sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
|
||||
.sysc_offs = 0x0000,
|
||||
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
||||
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
||||
.sysc_fields = &omap_hwmod_sysc_type2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
|
||||
.name = "sata",
|
||||
.sysc = &omap54xx_sata_sysc,
|
||||
};
|
||||
|
||||
/* sata */
|
||||
static struct omap_hwmod omap54xx_sata_hwmod = {
|
||||
.name = "sata",
|
||||
.class = &omap54xx_sata_hwmod_class,
|
||||
.clkdm_name = "l3init_clkdm",
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||
.main_clk = "func_48m_fclk",
|
||||
.mpu_rt_idx = 1,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_cfg -> sata */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
|
||||
.master = &omap54xx_l4_cfg_hwmod,
|
||||
.slave = &omap54xx_sata_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/*
|
||||
* Interfaces
|
||||
|
@ -2765,6 +2836,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
|
|||
&omap54xx_l4_cfg__usb_tll_hs,
|
||||
&omap54xx_l4_cfg__usb_otg_ss,
|
||||
&omap54xx_l4_wkup__wd_timer2,
|
||||
&omap54xx_l4_cfg__ocp2scp3,
|
||||
&omap54xx_l4_cfg__sata,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
@ -462,6 +462,7 @@ IS_OMAP_TYPE(3430, 0x3430)
|
|||
#define DRA7XX_CLASS 0x07000000
|
||||
#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
|
||||
#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
|
||||
#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
|
||||
|
||||
void omap2xxx_check_revision(void);
|
||||
void omap3xxx_check_revision(void);
|
||||
|
|
|
@ -12,8 +12,81 @@
|
|||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#define SUN4I_WATCHDOG_CTRL_REG 0x00
|
||||
#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
|
||||
#define SUN4I_WATCHDOG_MODE_REG 0x04
|
||||
#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
|
||||
#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
|
||||
|
||||
#define SUN6I_WATCHDOG1_IRQ_REG 0x00
|
||||
#define SUN6I_WATCHDOG1_CTRL_REG 0x10
|
||||
#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
|
||||
#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
|
||||
#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
|
||||
#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
|
||||
#define SUN6I_WATCHDOG1_MODE_REG 0x18
|
||||
#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
|
||||
|
||||
static void __iomem *wdt_base;
|
||||
|
||||
static void sun4i_restart(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
if (!wdt_base)
|
||||
return;
|
||||
|
||||
/* Enable timer and set reset bit in the watchdog */
|
||||
writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
|
||||
wdt_base + SUN4I_WATCHDOG_MODE_REG);
|
||||
|
||||
/*
|
||||
* Restart the watchdog. The default (and lowest) interval
|
||||
* value for the watchdog is 0.5s.
|
||||
*/
|
||||
writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
|
||||
|
||||
while (1) {
|
||||
mdelay(5);
|
||||
writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
|
||||
wdt_base + SUN4I_WATCHDOG_MODE_REG);
|
||||
}
|
||||
}
|
||||
|
||||
static struct of_device_id sunxi_restart_ids[] = {
|
||||
{ .compatible = "allwinner,sun4i-a10-wdt" },
|
||||
{ /*sentinel*/ }
|
||||
};
|
||||
|
||||
static void sunxi_setup_restart(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_matching_node(NULL, sunxi_restart_ids);
|
||||
if (WARN(!np, "unable to setup watchdog restart"))
|
||||
return;
|
||||
|
||||
wdt_base = of_iomap(np, 0);
|
||||
WARN(!wdt_base, "failed to map watchdog base address");
|
||||
}
|
||||
|
||||
static void __init sunxi_dt_init(void)
|
||||
{
|
||||
sunxi_setup_restart();
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char * const sunxi_board_dt_compat[] = {
|
||||
"allwinner,sun4i-a10",
|
||||
|
@ -23,7 +96,9 @@ static const char * const sunxi_board_dt_compat[] = {
|
|||
};
|
||||
|
||||
DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
|
||||
.init_machine = sunxi_dt_init,
|
||||
.dt_compat = sunxi_board_dt_compat,
|
||||
.restart = sun4i_restart,
|
||||
MACHINE_END
|
||||
|
||||
static const char * const sun6i_board_dt_compat[] = {
|
||||
|
@ -51,5 +126,7 @@ static const char * const sun7i_board_dt_compat[] = {
|
|||
};
|
||||
|
||||
DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
|
||||
.init_machine = sunxi_dt_init,
|
||||
.dt_compat = sun7i_board_dt_compat,
|
||||
.restart = sun4i_restart,
|
||||
MACHINE_END
|
||||
|
|
Loading…
Reference in New Issue