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perf list: Update documentation about raw event setup 

It was missing that only certain bit fields are passed to the config
value which confused users. Updating it.

Signed-off-by: Robert Richter <robert.richter@amd.com>
Cc: Ingo Molnar <mingo@kernel.org>
Link: http://lkml.kernel.org/r/1344361396-7237-6-git-send-email-robert.richter@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Robert Richter 2012-08-07 19:43:15 +02:00 committed by Arnaldo Carvalho de Melo
parent 0cf260131c
commit 75bc5ca898
1 changed files with 6 additions and 0 deletions
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6
tools/perf/Documentation/perf-list.txt
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@ -15,6 +15,7 @@ DESCRIPTION
This command displays the symbolic event types which can be selected in the
various perf commands with the -e option.
[[EVENT_MODIFIERS]]
EVENT MODIFIERS
---------------
@ -44,6 +45,11 @@ layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Softwar
of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
Note: Only the following bit fields can be set in x86 counter
registers: event, umask, edge, inv, cmask. Esp. guest/host only and
OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
MODIFIERS>>.
Example:
If the Intel docs for a QM720 Core i7 describe an event as: