octeontx2-af: Install ucast and bcast pkt forwarding rules
Upon NIXLF_ALLOC install a unicast forwarding rule in NPC MCAM like below - Match pkt DMAC with NIXLF attached PF/VF's MAC address. - Ingress channel - Action is UCAST - Forward to PF_FUNC of this NIXLF And broadcast pkt forwarding rule as - Match L2B bit in MCAM search key - Ingress channel - Action is UCAST, for now, later it will be changed to MCAST. Only PFs can install this rule Upon NIXLF_FREE disable all MCAM entries in use by that NIXLF. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sunil Goutham
David S. Miller
parent
f5721f76a4
commit
7590014066
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@ -240,4 +240,23 @@ struct npc_kpu_pkind_cpi_def {
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u64 ena : 1;
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#endif
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};
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struct nix_rx_action {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u64 rsvd_63_61 :3;
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u64 flow_key_alg :5;
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u64 match_id :16;
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u64 index :20;
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u64 pf_func :16;
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u64 op :4;
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#else
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u64 op :4;
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u64 pf_func :16;
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u64 index :20;
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u64 match_id :16;
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u64 flow_key_alg :5;
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u64 rsvd_63_61 :3;
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#endif
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};
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#endif /* NPC_H */
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@ -347,4 +347,9 @@ int rvu_npc_init(struct rvu *rvu);
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void rvu_npc_freemem(struct rvu *rvu);
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int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
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void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
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void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
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int nixlf, u64 chan, u8 *mac_addr);
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void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
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int nixlf, u64 chan);
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void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
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#endif /* RVU_H */
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@ -151,13 +151,24 @@ static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf)
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break;
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}
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/* Add a UCAST forwarding rule in MCAM with this NIXLF attached
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* RVU PF/VF's MAC address.
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*/
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rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf,
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pfvf->rx_chan_base, pfvf->mac_addr);
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/* Add this PF_FUNC to bcast pkt replication list */
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err = nix_update_bcast_mce_list(rvu, pcifunc, true);
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if (err) {
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dev_err(rvu->dev,
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"Bcast list, failed to enable PF_FUNC 0x%x\n",
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pcifunc);
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return err;
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}
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rvu_npc_install_bcast_match_entry(rvu, pcifunc,
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nixlf, pfvf->rx_chan_base);
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return 0;
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}
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@ -172,6 +183,9 @@ static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf)
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"Bcast list, failed to disable PF_FUNC 0x%x\n",
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pcifunc);
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}
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/* Free and disable any MCAM entries used by this NIX LF */
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rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf);
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}
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static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr,
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@ -26,6 +26,14 @@
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#define NPC_PARSE_RESULT_DMAC_OFFSET 8
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struct mcam_entry {
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#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
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u64 kw[NPC_MAX_KWS_IN_KEY];
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u64 kw_mask[NPC_MAX_KWS_IN_KEY];
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u64 action;
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u64 vtag_action;
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};
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void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
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{
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int blkaddr;
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@ -54,6 +62,335 @@ int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
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return -1;
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}
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static int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
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u16 pcifunc, int nixlf, int type)
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{
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int pf = rvu_get_pf(pcifunc);
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int index;
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/* Check if this is for a PF */
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if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) {
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/* Reserved entries exclude PF0 */
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pf--;
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index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF);
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/* Broadcast address matching entry should be first so
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* that the packet can be replicated to all VFs.
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*/
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if (type == NIXLF_BCAST_ENTRY)
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return index;
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else if (type == NIXLF_PROMISC_ENTRY)
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return index + 1;
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}
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return (mcam->nixlf_offset + (nixlf * RSVD_MCAM_ENTRIES_PER_NIXLF));
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}
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static int npc_get_bank(struct npc_mcam *mcam, int index)
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{
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int bank = index / mcam->banksize;
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/* 0,1 & 2,3 banks are combined for this keysize */
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if (mcam->keysize == NPC_MCAM_KEY_X2)
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return bank ? 2 : 0;
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return bank;
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}
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static bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam,
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int blkaddr, int index)
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{
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int bank = npc_get_bank(mcam, index);
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u64 cfg;
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index &= (mcam->banksize - 1);
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cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
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return (cfg & 1);
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}
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static void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
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int blkaddr, int index, bool enable)
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{
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int bank = npc_get_bank(mcam, index);
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int actbank = bank;
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index &= (mcam->banksize - 1);
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for (; bank < (actbank + mcam->banks_per_entry); bank++) {
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rvu_write64(rvu, blkaddr,
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NPC_AF_MCAMEX_BANKX_CFG(index, bank),
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enable ? 1 : 0);
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}
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}
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static void npc_get_keyword(struct mcam_entry *entry, int idx,
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u64 *cam0, u64 *cam1)
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{
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u64 kw_mask = 0x00;
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#define CAM_MASK(n) (BIT_ULL(n) - 1)
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/* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and
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* 1, 3, 5, 7 indices refer to BANKX_CAMX_W1.
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*
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* Also, only 48 bits of BANKX_CAMX_W1 are valid.
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*/
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switch (idx) {
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case 0:
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/* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */
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*cam1 = entry->kw[0];
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kw_mask = entry->kw_mask[0];
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break;
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case 1:
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/* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */
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*cam1 = entry->kw[1] & CAM_MASK(48);
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kw_mask = entry->kw_mask[1] & CAM_MASK(48);
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break;
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case 2:
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/* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48>
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* BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0>
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*/
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*cam1 = (entry->kw[1] >> 48) & CAM_MASK(16);
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*cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16);
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kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16);
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kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16);
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break;
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case 3:
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/* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48>
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* BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0>
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*/
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*cam1 = (entry->kw[2] >> 48) & CAM_MASK(16);
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*cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16);
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kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16);
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kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16);
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break;
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case 4:
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/* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32>
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* BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0>
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*/
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*cam1 = (entry->kw[3] >> 32) & CAM_MASK(32);
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*cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32);
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kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32);
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kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32);
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break;
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case 5:
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/* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32>
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* BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0>
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*/
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*cam1 = (entry->kw[4] >> 32) & CAM_MASK(32);
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*cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32);
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kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32);
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kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32);
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break;
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case 6:
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/* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16>
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* BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0>
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*/
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*cam1 = (entry->kw[5] >> 16) & CAM_MASK(48);
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*cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48);
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kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48);
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kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48);
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break;
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case 7:
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/* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */
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*cam1 = (entry->kw[6] >> 16) & CAM_MASK(48);
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kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48);
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break;
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}
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*cam1 &= kw_mask;
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*cam0 = ~*cam1 & kw_mask;
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}
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static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
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int blkaddr, int index, u8 intf,
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struct mcam_entry *entry, bool enable)
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{
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int bank = npc_get_bank(mcam, index);
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int kw = 0, actbank, actindex;
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u64 cam0, cam1;
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actbank = bank; /* Save bank id, to set action later on */
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actindex = index;
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index &= (mcam->banksize - 1);
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/* CAM1 takes the comparison value and
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* CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
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* CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
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* CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1
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* CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare.
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*/
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for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
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/* Interface should be set in all banks */
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rvu_write64(rvu, blkaddr,
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NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
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intf);
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rvu_write64(rvu, blkaddr,
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NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
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~intf & 0x3);
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/* Set the match key */
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npc_get_keyword(entry, kw, &cam0, &cam1);
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rvu_write64(rvu, blkaddr,
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NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);
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rvu_write64(rvu, blkaddr,
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NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);
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npc_get_keyword(entry, kw + 1, &cam0, &cam1);
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rvu_write64(rvu, blkaddr,
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NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);
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rvu_write64(rvu, blkaddr,
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NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);
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}
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/* Set 'action' */
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rvu_write64(rvu, blkaddr,
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NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action);
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/* Set TAG 'action' */
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rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank),
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entry->vtag_action);
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/* Enable the entry */
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if (enable)
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npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
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else
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npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
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}
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static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
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int blkaddr, int index)
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{
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int bank = npc_get_bank(mcam, index);
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index &= (mcam->banksize - 1);
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return rvu_read64(rvu, blkaddr,
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NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
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}
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void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
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int nixlf, u64 chan, u8 *mac_addr)
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{
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struct npc_mcam *mcam = &rvu->hw->mcam;
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struct mcam_entry entry = { {0} };
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struct nix_rx_action action;
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int blkaddr, index, kwi;
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u64 mac = 0;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
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if (blkaddr < 0)
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return;
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for (index = ETH_ALEN - 1; index >= 0; index--)
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mac |= ((u64)*mac_addr++) << (8 * index);
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index = npc_get_nixlf_mcam_index(mcam, pcifunc,
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nixlf, NIXLF_UCAST_ENTRY);
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/* Match ingress channel and DMAC */
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entry.kw[0] = chan;
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entry.kw_mask[0] = 0xFFFULL;
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kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64);
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entry.kw[kwi] = mac;
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entry.kw_mask[kwi] = BIT_ULL(48) - 1;
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/* Don't change the action if entry is already enabled
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* Otherwise RSS action may get overwritten.
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*/
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if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
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*(u64 *)&action = npc_get_mcam_action(rvu, mcam,
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blkaddr, index);
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} else {
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*(u64 *)&action = 0x00;
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action.op = NIX_RX_ACTIONOP_UCAST;
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action.pf_func = pcifunc;
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}
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entry.action = *(u64 *)&action;
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npc_config_mcam_entry(rvu, mcam, blkaddr, index,
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NIX_INTF_RX, &entry, true);
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}
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void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
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int nixlf, u64 chan)
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{
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struct npc_mcam *mcam = &rvu->hw->mcam;
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struct mcam_entry entry = { {0} };
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struct nix_rx_action action;
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#ifdef MCAST_MCE
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struct rvu_pfvf *pfvf;
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#endif
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int blkaddr, index;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
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if (blkaddr < 0)
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return;
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/* Only PF can add a bcast match entry */
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if (pcifunc & RVU_PFVF_FUNC_MASK)
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return;
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#ifdef MCAST_MCE
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pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
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#endif
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index = npc_get_nixlf_mcam_index(mcam, pcifunc,
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nixlf, NIXLF_BCAST_ENTRY);
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/* Check for L2B bit and LMAC channel */
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entry.kw[0] = BIT_ULL(25) | chan;
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entry.kw_mask[0] = BIT_ULL(25) | 0xFFFULL;
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*(u64 *)&action = 0x00;
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#ifdef MCAST_MCE
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/* Early silicon doesn't support pkt replication,
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* so install entry with UCAST action, so that PF
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* receives all broadcast packets.
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*/
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action.op = NIX_RX_ACTIONOP_MCAST;
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action.pf_func = pcifunc;
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action.index = pfvf->bcast_mce_idx;
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#else
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action.op = NIX_RX_ACTIONOP_UCAST;
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action.pf_func = pcifunc;
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#endif
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entry.action = *(u64 *)&action;
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npc_config_mcam_entry(rvu, mcam, blkaddr, index,
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NIX_INTF_RX, &entry, true);
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}
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void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
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{
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struct npc_mcam *mcam = &rvu->hw->mcam;
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struct nix_rx_action action;
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int blkaddr, index, bank;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
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if (blkaddr < 0)
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return;
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/* Disable ucast MCAM match entry of this PF/VF */
|
||||
index = npc_get_nixlf_mcam_index(mcam, pcifunc,
|
||||
nixlf, NIXLF_UCAST_ENTRY);
|
||||
npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
|
||||
|
||||
/* For PF, disable promisc and bcast MCAM match entries */
|
||||
if (!(pcifunc & RVU_PFVF_FUNC_MASK)) {
|
||||
index = npc_get_nixlf_mcam_index(mcam, pcifunc,
|
||||
nixlf, NIXLF_BCAST_ENTRY);
|
||||
/* For bcast, disable only if it's action is not
|
||||
* packet replication, incase if action is replication
|
||||
* then this PF's nixlf is removed from bcast replication
|
||||
* list.
|
||||
*/
|
||||
bank = npc_get_bank(mcam, index);
|
||||
index &= (mcam->banksize - 1);
|
||||
*(u64 *)&action = rvu_read64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
|
||||
if (action.op != NIX_RX_ACTIONOP_MCAST)
|
||||
npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
|
||||
}
|
||||
}
|
||||
|
||||
#define LDATA_EXTRACT_CONFIG(intf, lid, ltype, ld, cfg) \
|
||||
rvu_write64(rvu, blkaddr, \
|
||||
NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
|
||||
|
|
|
|||
Loading…
Reference in New Issue