mmc: core: Enable MMC_CAP2_CACHE_CTRL as default
There are no reason to why the use of a non-volatile internal eMMC cache should be controlled by a host cap. Instead let's just enable it if the eMMC card supports it. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <chris@printf.net>
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@ -2562,12 +2562,8 @@ EXPORT_SYMBOL(mmc_power_restore_host);
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*/
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int mmc_flush_cache(struct mmc_card *card)
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{
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struct mmc_host *host = card->host;
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int err = 0;
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if (!(host->caps2 & MMC_CAP2_CACHE_CTRL))
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return err;
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if (mmc_card_mmc(card) &&
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(card->ext_csd.cache_size > 0) &&
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(card->ext_csd.cache_ctrl & 1)) {
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@ -1287,8 +1287,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
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* If cache size is higher than 0, this indicates
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* the existence of cache and it can be turned on.
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*/
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if ((host->caps2 & MMC_CAP2_CACHE_CTRL) &&
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card->ext_csd.cache_size > 0) {
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if (card->ext_csd.cache_size > 0) {
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err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
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EXT_CSD_CACHE_CTRL, 1,
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card->ext_csd.generic_cmd6_time);
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@ -264,7 +264,6 @@ struct mmc_host {
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u32 caps2; /* More host capabilities */
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#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
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#define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */
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#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */
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#define MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */
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#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */
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