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[CPUFREQ] S5PV210: Adjust udelay prior to voltage scaling down 

Voltage scaling accesses the MAX8998 regulators over bit-banged I2C
with lots of udelays.  In the case of decreasing CPU speed, the
number of loops per us for udelay needs to be adjusted prior to
decreasing voltage to avoid delaying for up to 10X too long.

Signed-off-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Dave Jones <davej@redhat.com>
This commit is contained in:
Todd Poynor 2011-06-24 16:04:17 +09:00 committed by Dave Jones
parent 5b02b7794b
commit 74df8e69e9
1 changed files with 2 additions and 2 deletions
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4
drivers/cpufreq/s5pv210-cpufreq.c
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@ -467,6 +467,8 @@ static int s5pv210_target(struct cpufreq_policy *policy,
}
}
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
if (freqs.new < freqs.old) {
regulator_set_voltage(int_regulator,
int_volt, int_volt_max);
@ -475,8 +477,6 @@ static int s5pv210_target(struct cpufreq_policy *policy,
arm_volt, arm_volt_max);
}
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
printk(KERN_DEBUG "Perf changed[L%d]\n", index);
exit: