ASoC: fsl_asrc: rename asrc_priv to asrc
In order to move common structure to fsl_asrc_common.h we change the name of asrc_priv to asrc, the asrc_priv will be used by new struct fsl_asrc_priv. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/722142c2e1b57a95f911db1d42d901b88fc283d6.1587038908.git.shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
parent
e48e83d15b
commit
7470704d8b
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@ -21,10 +21,10 @@
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#define IDEAL_RATIO_DECIMAL_DEPTH 26
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#define pair_err(fmt, ...) \
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dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
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dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
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#define pair_dbg(fmt, ...) \
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dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
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dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
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/* Corresponding to process_option */
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static unsigned int supported_asrc_rate[] = {
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@ -157,15 +157,15 @@ static void fsl_asrc_sel_proc(int inrate, int outrate,
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int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
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{
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enum asrc_pair_index index = ASRC_INVALID_PAIR;
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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struct device *dev = &asrc_priv->pdev->dev;
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struct fsl_asrc *asrc = pair->asrc;
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struct device *dev = &asrc->pdev->dev;
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unsigned long lock_flags;
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int i, ret = 0;
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spin_lock_irqsave(&asrc_priv->lock, lock_flags);
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spin_lock_irqsave(&asrc->lock, lock_flags);
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for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
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if (asrc_priv->pair[i] != NULL)
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if (asrc->pair[i] != NULL)
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continue;
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index = i;
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@ -177,17 +177,17 @@ int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
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if (index == ASRC_INVALID_PAIR) {
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dev_err(dev, "all pairs are busy now\n");
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ret = -EBUSY;
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} else if (asrc_priv->channel_avail < channels) {
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} else if (asrc->channel_avail < channels) {
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dev_err(dev, "can't afford required channels: %d\n", channels);
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ret = -EINVAL;
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} else {
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asrc_priv->channel_avail -= channels;
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asrc_priv->pair[index] = pair;
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asrc->channel_avail -= channels;
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asrc->pair[index] = pair;
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pair->channels = channels;
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pair->index = index;
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}
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spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
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spin_unlock_irqrestore(&asrc->lock, lock_flags);
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return ret;
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}
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@ -195,25 +195,25 @@ int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
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/**
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* Release ASRC pair
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*
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* It clears the resource from asrc_priv and releases the occupied channels.
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* It clears the resource from asrc and releases the occupied channels.
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*/
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void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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struct fsl_asrc *asrc = pair->asrc;
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enum asrc_pair_index index = pair->index;
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unsigned long lock_flags;
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/* Make sure the pair is disabled */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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regmap_update_bits(asrc->regmap, REG_ASRCTR,
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ASRCTR_ASRCEi_MASK(index), 0);
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spin_lock_irqsave(&asrc_priv->lock, lock_flags);
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spin_lock_irqsave(&asrc->lock, lock_flags);
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asrc_priv->channel_avail += pair->channels;
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asrc_priv->pair[index] = NULL;
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asrc->channel_avail += pair->channels;
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asrc->pair[index] = NULL;
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pair->error = 0;
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spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
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spin_unlock_irqrestore(&asrc->lock, lock_flags);
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}
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/**
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@ -221,10 +221,10 @@ void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
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*/
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static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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struct fsl_asrc *asrc = pair->asrc;
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enum asrc_pair_index index = pair->index;
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regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
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regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
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ASRMCRi_EXTTHRSHi_MASK |
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ASRMCRi_INFIFO_THRESHOLD_MASK |
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ASRMCRi_OUTFIFO_THRESHOLD_MASK,
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@ -257,7 +257,7 @@ static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
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static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
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int inrate, int outrate)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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struct fsl_asrc *asrc = pair->asrc;
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enum asrc_pair_index index = pair->index;
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unsigned long ratio;
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int i;
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@ -286,8 +286,8 @@ static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
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break;
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}
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regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
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regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
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regmap_write(asrc->regmap, REG_ASRIDRL(index), ratio);
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regmap_write(asrc->regmap, REG_ASRIDRH(index), ratio >> 24);
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return 0;
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}
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@ -309,7 +309,7 @@ static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
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static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
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{
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struct asrc_config *config = pair->config;
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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struct fsl_asrc *asrc = pair->asrc;
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enum asrc_pair_index index = pair->index;
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enum asrc_word_width input_word_width;
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enum asrc_word_width output_word_width;
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@ -392,11 +392,11 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
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}
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/* Validate input and output clock sources */
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clk_index[IN] = asrc_priv->clk_map[IN][config->inclk];
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clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk];
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clk_index[IN] = asrc->clk_map[IN][config->inclk];
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clk_index[OUT] = asrc->clk_map[OUT][config->outclk];
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/* We only have output clock for ideal ratio mode */
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clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
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clk = asrc->asrck_clk[clk_index[ideal ? OUT : IN]];
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clk_rate = clk_get_rate(clk);
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rem[IN] = do_div(clk_rate, inrate);
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@ -417,7 +417,7 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
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div[IN] = min_t(u32, 1024, div[IN]);
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clk = asrc_priv->asrck_clk[clk_index[OUT]];
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clk = asrc->asrck_clk[clk_index[OUT]];
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clk_rate = clk_get_rate(clk);
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if (ideal && use_ideal_rate)
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rem[OUT] = do_div(clk_rate, IDEAL_RATIO_RATE);
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@ -437,22 +437,22 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
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/* Set the channel number */
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channels = config->channel_num;
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if (asrc_priv->soc->channel_bits < 4)
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if (asrc->soc->channel_bits < 4)
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channels /= 2;
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/* Update channels for current pair */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
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ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits),
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ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits));
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regmap_update_bits(asrc->regmap, REG_ASRCNCR,
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ASRCNCR_ANCi_MASK(index, asrc->soc->channel_bits),
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ASRCNCR_ANCi(index, channels, asrc->soc->channel_bits));
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/* Default setting: Automatic selection for processing mode */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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regmap_update_bits(asrc->regmap, REG_ASRCTR,
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ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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regmap_update_bits(asrc->regmap, REG_ASRCTR,
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ASRCTR_USRi_MASK(index), 0);
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/* Set the input and output clock sources */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
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regmap_update_bits(asrc->regmap, REG_ASRCSR,
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ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
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ASRCSR_AICS(index, clk_index[IN]) |
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ASRCSR_AOCS(index, clk_index[OUT]));
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@ -462,19 +462,19 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
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outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
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/* Suppose indiv and outdiv includes prescaler, so add its MASK too */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
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regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
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ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
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ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
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ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
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/* Implement word_width configurations */
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regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
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regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
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ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
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ASRMCR1i_OW16(output_word_width) |
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ASRMCR1i_IWD(input_word_width));
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/* Enable BUFFER STALL */
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regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
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regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
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ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
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/* Set default thresholds for input and output FIFO */
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@ -486,18 +486,18 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
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return 0;
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/* Clear ASTSx bit to use Ideal Ratio mode */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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regmap_update_bits(asrc->regmap, REG_ASRCTR,
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ASRCTR_ATSi_MASK(index), 0);
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/* Enable Ideal Ratio mode */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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regmap_update_bits(asrc->regmap, REG_ASRCTR,
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ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
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ASRCTR_IDR(index) | ASRCTR_USR(index));
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fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
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/* Apply configurations for pre- and post-processing */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
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regmap_update_bits(asrc->regmap, REG_ASRCFG,
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ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
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ASRCFG_PREMOD(index, pre_proc) |
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ASRCFG_POSTMOD(index, post_proc));
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@ -512,28 +512,28 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
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*/
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static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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struct fsl_asrc *asrc = pair->asrc;
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enum asrc_pair_index index = pair->index;
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int reg, retry = 10, i;
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/* Enable the current pair */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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regmap_update_bits(asrc->regmap, REG_ASRCTR,
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ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
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/* Wait for status of initialization */
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do {
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udelay(5);
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regmap_read(asrc_priv->regmap, REG_ASRCFG, ®);
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regmap_read(asrc->regmap, REG_ASRCFG, ®);
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reg &= ASRCFG_INIRQi_MASK(index);
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} while (!reg && --retry);
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/* Make the input fifo to ASRC STALL level */
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regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®);
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regmap_read(asrc->regmap, REG_ASRCNCR, ®);
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for (i = 0; i < pair->channels * 4; i++)
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regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
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regmap_write(asrc->regmap, REG_ASRDI(index), 0);
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/* Enable overload interrupt */
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regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
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regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
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}
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/**
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@ -541,11 +541,11 @@ static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
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*/
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static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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struct fsl_asrc *asrc = pair->asrc;
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enum asrc_pair_index index = pair->index;
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/* Stop the current pair */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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regmap_update_bits(asrc->regmap, REG_ASRCTR,
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ASRCTR_ASRCEi_MASK(index), 0);
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}
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@ -554,23 +554,23 @@ static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
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*/
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struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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struct fsl_asrc *asrc = pair->asrc;
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enum asrc_pair_index index = pair->index;
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char name[4];
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sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
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return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
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return dma_request_slave_channel(&asrc->pdev->dev, name);
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}
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EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
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static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
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struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
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/* Odd channel number is not valid for older ASRC (channel_bits==3) */
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if (asrc_priv->soc->channel_bits == 3)
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if (asrc->soc->channel_bits == 3)
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snd_pcm_hw_constraint_step(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_CHANNELS, 2);
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@ -583,7 +583,7 @@ static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
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struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct fsl_asrc_pair *pair = runtime->private_data;
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unsigned int channels = params_channels(params);
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@ -600,7 +600,7 @@ static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
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pair->config = &config;
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if (asrc_priv->asrc_width == 16)
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if (asrc->asrc_width == 16)
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format = SNDRV_PCM_FORMAT_S16_LE;
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else
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format = SNDRV_PCM_FORMAT_S24_LE;
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@ -614,11 +614,11 @@ static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
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config.input_format = params_format(params);
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config.output_format = format;
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config.input_sample_rate = rate;
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config.output_sample_rate = asrc_priv->asrc_rate;
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config.output_sample_rate = asrc->asrc_rate;
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} else {
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config.input_format = format;
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config.output_format = params_format(params);
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config.input_sample_rate = asrc_priv->asrc_rate;
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config.input_sample_rate = asrc->asrc_rate;
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config.output_sample_rate = rate;
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}
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@ -676,10 +676,10 @@ static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
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static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
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{
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struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
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struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
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&asrc_priv->dma_params_rx);
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snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx,
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&asrc->dma_params_rx);
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return 0;
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}
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@ -858,30 +858,30 @@ static const struct regmap_config fsl_asrc_regmap_config = {
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|||
/**
|
||||
* Initialize ASRC registers with a default configurations
|
||||
*/
|
||||
static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
|
||||
static int fsl_asrc_init(struct fsl_asrc *asrc)
|
||||
{
|
||||
/* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
|
||||
regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
|
||||
regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
|
||||
|
||||
/* Disable interrupt by default */
|
||||
regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
|
||||
regmap_write(asrc->regmap, REG_ASRIER, 0x0);
|
||||
|
||||
/* Apply recommended settings for parameters from Reference Manual */
|
||||
regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
|
||||
regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
|
||||
regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
|
||||
regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
|
||||
regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
|
||||
regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
|
||||
regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
|
||||
regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
|
||||
regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
|
||||
regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
|
||||
|
||||
/* Base address for task queue FIFO. Set to 0x7C */
|
||||
regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
|
||||
regmap_update_bits(asrc->regmap, REG_ASRTFR1,
|
||||
ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
|
||||
|
||||
/* Set the processing clock for 76KHz to 133M */
|
||||
regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
|
||||
regmap_write(asrc->regmap, REG_ASR76K, 0x06D6);
|
||||
|
||||
/* Set the processing clock for 56KHz to 133M */
|
||||
return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
|
||||
return regmap_write(asrc->regmap, REG_ASR56K, 0x0947);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -889,15 +889,15 @@ static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
|
|||
*/
|
||||
static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
|
||||
struct device *dev = &asrc_priv->pdev->dev;
|
||||
struct fsl_asrc *asrc = (struct fsl_asrc *)dev_id;
|
||||
struct device *dev = &asrc->pdev->dev;
|
||||
enum asrc_pair_index index;
|
||||
u32 status;
|
||||
|
||||
regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
|
||||
regmap_read(asrc->regmap, REG_ASRSTR, &status);
|
||||
|
||||
/* Clean overload error */
|
||||
regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
|
||||
regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE);
|
||||
|
||||
/*
|
||||
* We here use dev_dbg() for all exceptions because ASRC itself does
|
||||
|
@ -905,31 +905,31 @@ static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
|
|||
* interrupt would result a ridged conversion.
|
||||
*/
|
||||
for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
|
||||
if (!asrc_priv->pair[index])
|
||||
if (!asrc->pair[index])
|
||||
continue;
|
||||
|
||||
if (status & ASRSTR_ATQOL) {
|
||||
asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
|
||||
asrc->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
|
||||
dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
|
||||
}
|
||||
|
||||
if (status & ASRSTR_AOOL(index)) {
|
||||
asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
|
||||
asrc->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
|
||||
pair_dbg("Output Task Overload\n");
|
||||
}
|
||||
|
||||
if (status & ASRSTR_AIOL(index)) {
|
||||
asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
|
||||
asrc->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
|
||||
pair_dbg("Input Task Overload\n");
|
||||
}
|
||||
|
||||
if (status & ASRSTR_AODO(index)) {
|
||||
asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
|
||||
asrc->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
|
||||
pair_dbg("Output Data Buffer has overflowed\n");
|
||||
}
|
||||
|
||||
if (status & ASRSTR_AIDU(index)) {
|
||||
asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
|
||||
asrc->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
|
||||
pair_dbg("Input Data Buffer has underflowed\n");
|
||||
}
|
||||
}
|
||||
|
@ -940,18 +940,18 @@ static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
|
|||
static int fsl_asrc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct fsl_asrc *asrc_priv;
|
||||
struct fsl_asrc *asrc;
|
||||
struct resource *res;
|
||||
void __iomem *regs;
|
||||
int irq, ret, i;
|
||||
u32 map_idx;
|
||||
char tmp[16];
|
||||
|
||||
asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
|
||||
if (!asrc_priv)
|
||||
asrc = devm_kzalloc(&pdev->dev, sizeof(*asrc), GFP_KERNEL);
|
||||
if (!asrc)
|
||||
return -ENOMEM;
|
||||
|
||||
asrc_priv->pdev = pdev;
|
||||
asrc->pdev = pdev;
|
||||
|
||||
/* Get the addresses and IRQ */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
@ -959,13 +959,13 @@ static int fsl_asrc_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(regs))
|
||||
return PTR_ERR(regs);
|
||||
|
||||
asrc_priv->paddr = res->start;
|
||||
asrc->paddr = res->start;
|
||||
|
||||
asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
|
||||
&fsl_asrc_regmap_config);
|
||||
if (IS_ERR(asrc_priv->regmap)) {
|
||||
asrc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
|
||||
&fsl_asrc_regmap_config);
|
||||
if (IS_ERR(asrc->regmap)) {
|
||||
dev_err(&pdev->dev, "failed to init regmap\n");
|
||||
return PTR_ERR(asrc_priv->regmap);
|
||||
return PTR_ERR(asrc->regmap);
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
|
@ -973,49 +973,49 @@ static int fsl_asrc_probe(struct platform_device *pdev)
|
|||
return irq;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
|
||||
dev_name(&pdev->dev), asrc_priv);
|
||||
dev_name(&pdev->dev), asrc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
|
||||
if (IS_ERR(asrc_priv->mem_clk)) {
|
||||
asrc->mem_clk = devm_clk_get(&pdev->dev, "mem");
|
||||
if (IS_ERR(asrc->mem_clk)) {
|
||||
dev_err(&pdev->dev, "failed to get mem clock\n");
|
||||
return PTR_ERR(asrc_priv->mem_clk);
|
||||
return PTR_ERR(asrc->mem_clk);
|
||||
}
|
||||
|
||||
asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
|
||||
if (IS_ERR(asrc_priv->ipg_clk)) {
|
||||
asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
|
||||
if (IS_ERR(asrc->ipg_clk)) {
|
||||
dev_err(&pdev->dev, "failed to get ipg clock\n");
|
||||
return PTR_ERR(asrc_priv->ipg_clk);
|
||||
return PTR_ERR(asrc->ipg_clk);
|
||||
}
|
||||
|
||||
asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
|
||||
if (IS_ERR(asrc_priv->spba_clk))
|
||||
asrc->spba_clk = devm_clk_get(&pdev->dev, "spba");
|
||||
if (IS_ERR(asrc->spba_clk))
|
||||
dev_warn(&pdev->dev, "failed to get spba clock\n");
|
||||
|
||||
for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
|
||||
sprintf(tmp, "asrck_%x", i);
|
||||
asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
|
||||
if (IS_ERR(asrc_priv->asrck_clk[i])) {
|
||||
asrc->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
|
||||
if (IS_ERR(asrc->asrck_clk[i])) {
|
||||
dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
|
||||
return PTR_ERR(asrc_priv->asrck_clk[i]);
|
||||
return PTR_ERR(asrc->asrck_clk[i]);
|
||||
}
|
||||
}
|
||||
|
||||
asrc_priv->soc = of_device_get_match_data(&pdev->dev);
|
||||
if (!asrc_priv->soc) {
|
||||
asrc->soc = of_device_get_match_data(&pdev->dev);
|
||||
if (!asrc->soc) {
|
||||
dev_err(&pdev->dev, "failed to get soc data\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
|
||||
asrc_priv->clk_map[IN] = input_clk_map_imx35;
|
||||
asrc_priv->clk_map[OUT] = output_clk_map_imx35;
|
||||
asrc->clk_map[IN] = input_clk_map_imx35;
|
||||
asrc->clk_map[OUT] = output_clk_map_imx35;
|
||||
} else if (of_device_is_compatible(np, "fsl,imx53-asrc")) {
|
||||
asrc_priv->clk_map[IN] = input_clk_map_imx53;
|
||||
asrc_priv->clk_map[OUT] = output_clk_map_imx53;
|
||||
asrc->clk_map[IN] = input_clk_map_imx53;
|
||||
asrc->clk_map[OUT] = output_clk_map_imx53;
|
||||
} else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") ||
|
||||
of_device_is_compatible(np, "fsl,imx8qxp-asrc")) {
|
||||
ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx);
|
||||
|
@ -1029,44 +1029,44 @@ static int fsl_asrc_probe(struct platform_device *pdev)
|
|||
return -EINVAL;
|
||||
}
|
||||
if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) {
|
||||
asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx];
|
||||
asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx];
|
||||
asrc->clk_map[IN] = clk_map_imx8qm[map_idx];
|
||||
asrc->clk_map[OUT] = clk_map_imx8qm[map_idx];
|
||||
} else {
|
||||
asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx];
|
||||
asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx];
|
||||
asrc->clk_map[IN] = clk_map_imx8qxp[map_idx];
|
||||
asrc->clk_map[OUT] = clk_map_imx8qxp[map_idx];
|
||||
}
|
||||
}
|
||||
|
||||
ret = fsl_asrc_init(asrc_priv);
|
||||
ret = fsl_asrc_init(asrc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
asrc_priv->channel_avail = 10;
|
||||
asrc->channel_avail = 10;
|
||||
|
||||
ret = of_property_read_u32(np, "fsl,asrc-rate",
|
||||
&asrc_priv->asrc_rate);
|
||||
&asrc->asrc_rate);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to get output rate\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(np, "fsl,asrc-width",
|
||||
&asrc_priv->asrc_width);
|
||||
&asrc->asrc_width);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to get output width\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
|
||||
if (asrc->asrc_width != 16 && asrc->asrc_width != 24) {
|
||||
dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
|
||||
asrc_priv->asrc_width = 24;
|
||||
asrc->asrc_width = 24;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, asrc_priv);
|
||||
platform_set_drvdata(pdev, asrc);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
spin_lock_init(&asrc_priv->lock);
|
||||
spin_lock_init(&asrc->lock);
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
|
||||
&fsl_asrc_dai, 1);
|
||||
|
@ -1081,22 +1081,22 @@ static int fsl_asrc_probe(struct platform_device *pdev)
|
|||
#ifdef CONFIG_PM
|
||||
static int fsl_asrc_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
|
||||
struct fsl_asrc *asrc = dev_get_drvdata(dev);
|
||||
int i, ret;
|
||||
|
||||
ret = clk_prepare_enable(asrc_priv->mem_clk);
|
||||
ret = clk_prepare_enable(asrc->mem_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = clk_prepare_enable(asrc_priv->ipg_clk);
|
||||
ret = clk_prepare_enable(asrc->ipg_clk);
|
||||
if (ret)
|
||||
goto disable_mem_clk;
|
||||
if (!IS_ERR(asrc_priv->spba_clk)) {
|
||||
ret = clk_prepare_enable(asrc_priv->spba_clk);
|
||||
if (!IS_ERR(asrc->spba_clk)) {
|
||||
ret = clk_prepare_enable(asrc->spba_clk);
|
||||
if (ret)
|
||||
goto disable_ipg_clk;
|
||||
}
|
||||
for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
|
||||
ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
|
||||
ret = clk_prepare_enable(asrc->asrck_clk[i]);
|
||||
if (ret)
|
||||
goto disable_asrck_clk;
|
||||
}
|
||||
|
@ -1105,27 +1105,27 @@ static int fsl_asrc_runtime_resume(struct device *dev)
|
|||
|
||||
disable_asrck_clk:
|
||||
for (i--; i >= 0; i--)
|
||||
clk_disable_unprepare(asrc_priv->asrck_clk[i]);
|
||||
if (!IS_ERR(asrc_priv->spba_clk))
|
||||
clk_disable_unprepare(asrc_priv->spba_clk);
|
||||
clk_disable_unprepare(asrc->asrck_clk[i]);
|
||||
if (!IS_ERR(asrc->spba_clk))
|
||||
clk_disable_unprepare(asrc->spba_clk);
|
||||
disable_ipg_clk:
|
||||
clk_disable_unprepare(asrc_priv->ipg_clk);
|
||||
clk_disable_unprepare(asrc->ipg_clk);
|
||||
disable_mem_clk:
|
||||
clk_disable_unprepare(asrc_priv->mem_clk);
|
||||
clk_disable_unprepare(asrc->mem_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fsl_asrc_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
|
||||
struct fsl_asrc *asrc = dev_get_drvdata(dev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
|
||||
clk_disable_unprepare(asrc_priv->asrck_clk[i]);
|
||||
if (!IS_ERR(asrc_priv->spba_clk))
|
||||
clk_disable_unprepare(asrc_priv->spba_clk);
|
||||
clk_disable_unprepare(asrc_priv->ipg_clk);
|
||||
clk_disable_unprepare(asrc_priv->mem_clk);
|
||||
clk_disable_unprepare(asrc->asrck_clk[i]);
|
||||
if (!IS_ERR(asrc->spba_clk))
|
||||
clk_disable_unprepare(asrc->spba_clk);
|
||||
clk_disable_unprepare(asrc->ipg_clk);
|
||||
clk_disable_unprepare(asrc->mem_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -1134,37 +1134,37 @@ static int fsl_asrc_runtime_suspend(struct device *dev)
|
|||
#ifdef CONFIG_PM_SLEEP
|
||||
static int fsl_asrc_suspend(struct device *dev)
|
||||
{
|
||||
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
|
||||
struct fsl_asrc *asrc = dev_get_drvdata(dev);
|
||||
|
||||
regmap_read(asrc_priv->regmap, REG_ASRCFG,
|
||||
&asrc_priv->regcache_cfg);
|
||||
regmap_read(asrc->regmap, REG_ASRCFG,
|
||||
&asrc->regcache_cfg);
|
||||
|
||||
regcache_cache_only(asrc_priv->regmap, true);
|
||||
regcache_mark_dirty(asrc_priv->regmap);
|
||||
regcache_cache_only(asrc->regmap, true);
|
||||
regcache_mark_dirty(asrc->regmap);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_asrc_resume(struct device *dev)
|
||||
{
|
||||
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
|
||||
struct fsl_asrc *asrc = dev_get_drvdata(dev);
|
||||
u32 asrctr;
|
||||
|
||||
/* Stop all pairs provisionally */
|
||||
regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
|
||||
regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
|
||||
regmap_read(asrc->regmap, REG_ASRCTR, &asrctr);
|
||||
regmap_update_bits(asrc->regmap, REG_ASRCTR,
|
||||
ASRCTR_ASRCEi_ALL_MASK, 0);
|
||||
|
||||
/* Restore all registers */
|
||||
regcache_cache_only(asrc_priv->regmap, false);
|
||||
regcache_sync(asrc_priv->regmap);
|
||||
regcache_cache_only(asrc->regmap, false);
|
||||
regcache_sync(asrc->regmap);
|
||||
|
||||
regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
|
||||
regmap_update_bits(asrc->regmap, REG_ASRCFG,
|
||||
ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
|
||||
ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
|
||||
ASRCFG_PREMODi_ALL_MASK, asrc->regcache_cfg);
|
||||
|
||||
/* Restart enabled pairs */
|
||||
regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
|
||||
regmap_update_bits(asrc->regmap, REG_ASRCTR,
|
||||
ASRCTR_ASRCEi_ALL_MASK, asrctr);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -448,7 +448,7 @@ struct fsl_asrc_soc_data {
|
|||
/**
|
||||
* fsl_asrc_pair: ASRC Pair private data
|
||||
*
|
||||
* @asrc_priv: pointer to its parent module
|
||||
* @asrc: pointer to its parent module
|
||||
* @config: configuration profile
|
||||
* @error: error record
|
||||
* @index: pair index (ASRC_PAIR_A, ASRC_PAIR_B, ASRC_PAIR_C)
|
||||
|
@ -460,7 +460,7 @@ struct fsl_asrc_soc_data {
|
|||
* @private: pair private area
|
||||
*/
|
||||
struct fsl_asrc_pair {
|
||||
struct fsl_asrc *asrc_priv;
|
||||
struct fsl_asrc *asrc;
|
||||
struct asrc_config *config;
|
||||
unsigned int error;
|
||||
|
||||
|
|
|
@ -135,7 +135,7 @@ static int fsl_asrc_dma_hw_params(struct snd_soc_component *component,
|
|||
struct snd_dmaengine_dai_dma_data *dma_params_be = NULL;
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct fsl_asrc_pair *pair = runtime->private_data;
|
||||
struct fsl_asrc *asrc_priv = pair->asrc_priv;
|
||||
struct fsl_asrc *asrc = pair->asrc;
|
||||
struct dma_slave_config config_fe, config_be;
|
||||
enum asrc_pair_index index = pair->index;
|
||||
struct device *dev = component->dev;
|
||||
|
@ -170,7 +170,7 @@ static int fsl_asrc_dma_hw_params(struct snd_soc_component *component,
|
|||
|
||||
/* Override dma_data of the Front-End and config its dmaengine */
|
||||
dma_params_fe = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
|
||||
dma_params_fe->addr = asrc_priv->paddr + REG_ASRDx(!dir, index);
|
||||
dma_params_fe->addr = asrc->paddr + REG_ASRDx(!dir, index);
|
||||
dma_params_fe->maxburst = dma_params_be->maxburst;
|
||||
|
||||
pair->dma_chan[!dir] = fsl_asrc_get_dma_channel(pair, !dir);
|
||||
|
@ -203,7 +203,7 @@ static int fsl_asrc_dma_hw_params(struct snd_soc_component *component,
|
|||
* need to configure dma_request and dma_request2, but get dma_chan via
|
||||
* dma_request_slave_channel directly with dma name of Front-End device
|
||||
*/
|
||||
if (!asrc_priv->soc->use_edma) {
|
||||
if (!asrc->soc->use_edma) {
|
||||
/* Get DMA request of Back-End */
|
||||
tmp_chan = dma_request_slave_channel(dev_be, tx ? "tx" : "rx");
|
||||
tmp_data = tmp_chan->private;
|
||||
|
@ -230,7 +230,7 @@ static int fsl_asrc_dma_hw_params(struct snd_soc_component *component,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (asrc_priv->asrc_width == 16)
|
||||
if (asrc->asrc_width == 16)
|
||||
buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
||||
else
|
||||
buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
|
@ -242,10 +242,10 @@ static int fsl_asrc_dma_hw_params(struct snd_soc_component *component,
|
|||
config_be.dst_maxburst = dma_params_be->maxburst;
|
||||
|
||||
if (tx) {
|
||||
config_be.src_addr = asrc_priv->paddr + REG_ASRDO(index);
|
||||
config_be.src_addr = asrc->paddr + REG_ASRDO(index);
|
||||
config_be.dst_addr = dma_params_be->addr;
|
||||
} else {
|
||||
config_be.dst_addr = asrc_priv->paddr + REG_ASRDI(index);
|
||||
config_be.dst_addr = asrc->paddr + REG_ASRDI(index);
|
||||
config_be.src_addr = dma_params_be->addr;
|
||||
}
|
||||
|
||||
|
@ -288,7 +288,7 @@ static int fsl_asrc_dma_startup(struct snd_soc_component *component,
|
|||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct snd_dmaengine_dai_dma_data *dma_data;
|
||||
struct device *dev = component->dev;
|
||||
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
|
||||
struct fsl_asrc *asrc = dev_get_drvdata(dev);
|
||||
struct fsl_asrc_pair *pair;
|
||||
struct dma_chan *tmp_chan = NULL;
|
||||
u8 dir = tx ? OUT : IN;
|
||||
|
@ -306,7 +306,7 @@ static int fsl_asrc_dma_startup(struct snd_soc_component *component,
|
|||
if (!pair)
|
||||
return -ENOMEM;
|
||||
|
||||
pair->asrc_priv = asrc_priv;
|
||||
pair->asrc = asrc;
|
||||
|
||||
runtime->private_data = pair;
|
||||
|
||||
|
@ -361,15 +361,15 @@ static int fsl_asrc_dma_shutdown(struct snd_soc_component *component,
|
|||
{
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct fsl_asrc_pair *pair = runtime->private_data;
|
||||
struct fsl_asrc *asrc_priv;
|
||||
struct fsl_asrc *asrc;
|
||||
|
||||
if (!pair)
|
||||
return 0;
|
||||
|
||||
asrc_priv = pair->asrc_priv;
|
||||
asrc = pair->asrc;
|
||||
|
||||
if (asrc_priv->pair[pair->index] == pair)
|
||||
asrc_priv->pair[pair->index] = NULL;
|
||||
if (asrc->pair[pair->index] == pair)
|
||||
asrc->pair[pair->index] = NULL;
|
||||
|
||||
kfree(pair);
|
||||
|
||||
|
|
Loading…
Reference in New Issue