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A lot more love for Veyron devices with cleanups in the display and wifi 

areas and also a 100ms speedup as a delay isn't needed anymore.
 New boards are Tiger and Fievel from the Veyron family and the Mecer Xtreme
 Mini S6, which I think is the first consumer-grade rk3229-based device in
 the kernel.
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Merge tag 'v5.4-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

A lot more love for Veyron devices with cleanups in the display and wifi
areas and also a 100ms speedup as a delay isn't needed anymore.
New boards are Tiger and Fievel from the Veyron family and the Mecer Xtreme
Mini S6, which I think is the first consumer-grade rk3229-based device in
the kernel.

* tag 'v5.4-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: add device tree for Mecer Xtreme Mini S6
  Revert "ARM: dts: rockchip: add startup delay to rk3288-veyron panel-regulators"
  ARM: dts: rockchip: Add pin names for rk3288-veyron fievel
  ARM: dts: rockchip: A few fixes for veyron-{fievel,tiger}
  ARM: dts: rockchip: Cleanup style around assignment operator
  ARM: dts: rockchip: add veyron-tiger board
  ARM: dts: rockchip: add veyron-fievel board
  dt-bindings: ARM: dts: rockchip: Add bindings for rk3288-veyron-{fievel,tiger}
  ARM: dts: rockchip: consolidate veyron panel and backlight settings
  ARM: dts: rockchip: move rk3288-veryon display settings into a separate file
  ARM: dts: rockchip: Limit WiFi TX power on rk3288-veyron-jerry
  ARM: dts: rockchip: Specify rk3288-veyron-minnie's display timings
  ARM: dts: rockchip: Specify rk3288-veyron-chromebook's display timings

Link: https://lore.kernel.org/r/1611583.rKl1eQBRh8@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-09-03 14:44:28 +02:00
parent 5ba78afff9 dd7c66ac77
commit 745d0c932b
17 changed files with 1328 additions and 331 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -128,6 +128,21 @@ properties:
- const: google,veyron
- const: rockchip,rk3288
- description: Google Fievel (AOPEN Chromebox Mini)
items:
- const: google,veyron-fievel-rev8
- const: google,veyron-fievel-rev7
- const: google,veyron-fievel-rev6
- const: google,veyron-fievel-rev5
- const: google,veyron-fievel-rev4
- const: google,veyron-fievel-rev3
- const: google,veyron-fievel-rev2
- const: google,veyron-fievel-rev1
- const: google,veyron-fievel-rev0
- const: google,veyron-fievel
- const: google,veyron
- const: rockchip,rk3288
- description: Google Gru (dev-board)
items:
- const: google,gru-rev15
@ -311,6 +326,21 @@ properties:
- const: google,veyron
- const: rockchip,rk3288
- description: Google Tiger (AOpen Chromebase Mini)
items:
- const: google,veyron-tiger-rev8
- const: google,veyron-tiger-rev7
- const: google,veyron-tiger-rev6
- const: google,veyron-tiger-rev5
- const: google,veyron-tiger-rev4
- const: google,veyron-tiger-rev3
- const: google,veyron-tiger-rev2
- const: google,veyron-tiger-rev1
- const: google,veyron-tiger-rev0
- const: google,veyron-tiger
- const: google,veyron
- const: rockchip,rk3288
- description: Haoyu MarsBoard RK3066
items:
- const: haoyu,marsboard-rk3066
@ -329,6 +359,11 @@ properties:
- khadas,edge-v
- const: rockchip,rk3399
- description: Mecer Xtreme Mini S6
items:
- const: mecer,xms6
- const: rockchip,rk3229
- description: mqmaker MiQi
items:
- const: mqmaker,miqi

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -549,6 +549,8 @@ patternProperties:
description: mCube
"^meas,.*":
description: Measurement Specialties
"^mecer,.*":
description: Mustek Limited
"^mediatek,.*":
description: MediaTek Inc.
"^megachips,.*":

3
arch/arm/boot/dts/Makefile
View File

@ -905,6 +905,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
rk3229-evb.dtb \
rk3229-xms6.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
rk3288-fennec.dtb \
@ -919,6 +920,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-tinker.dtb \
rk3288-tinker-s.dtb \
rk3288-veyron-brain.dtb \
rk3288-veyron-fievel.dtb \
rk3288-veyron-jaq.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
@ -926,6 +928,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \
rk3288-veyron-speedy.dtb \
rk3288-veyron-tiger.dtb \
rk3288-vyasa.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb

2
arch/arm/boot/dts/rk3036.dtsi
View File

@ -484,7 +484,7 @@
compatible = "rockchip,rockchip-spi";
reg = <0x20074000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
clock-names = "apb-pclk","spi_pclk";
dmas = <&pdma 8>, <&pdma 9>;
dma-names = "tx", "rx";

283
arch/arm/boot/dts/rk3229-xms6.dts Normal file
View File

@ -0,0 +1,283 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3229.dtsi"
/ {
model = "Mecer Xtreme Mini S6";
compatible = "mecer,xms6", "rockchip,rk3229";
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
dc_12v: dc-12v-regulator {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
ext_gmac: ext_gmac {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
#clock-cells = <0>;
};
power-led {
compatible = "gpio-leds";
blue {
gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc_phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vccio_1v8>;
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vccio_1v8: vccio-1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "vccio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vccio_3v3: vccio-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "vccio_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vdd_arm: vdd-arm-regulator {
compatible = "pwm-regulator";
pwms = <&pwm1 0 25000 1>;
pwm-supply = <&vcc_sys>;
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
vdd_log: vdd-log-regulator {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc_sys>;
regulator-name = "vdd_log";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&emmc {
cap-mmc-highspeed;
disable-wp;
non-removable;
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_MAC_SRC>;
assigned-clock-rates = <50000000>;
clock_in_out = "output";
phy-handle = <&phy>;
phy-mode = "rmii";
phy-supply = <&vcc_phy>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy: phy@0 {
compatible = "ethernet-phy-id1234.d400",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
clocks = <&cru SCLK_MAC_PHY>;
phy-is-integrated;
resets = <&cru SRST_MACPHY>;
};
};
};
&gpu {
mali-supply = <&vdd_log>;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_phy {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&io_domains {
status = "okay";
vccio1-supply = <&vccio_3v3>;
vccio2-supply = <&vccio_1v8>;
vccio4-supply = <&vccio_3v3>;
};
&pinctrl {
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&sdmmc {
cap-mmc-highspeed;
disable-wp;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <0>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_host: host-port {
phy-supply = <&vcc_host>;
status = "okay";
};
u2phy0_otg: otg-port {
phy-supply = <&vcc_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_host: host-port {
phy-supply = <&vcc_host>;
status = "okay";
};
u2phy1_otg: otg-port {
phy-supply = <&vcc_host>;
status = "okay";
};
};
&uart2 {
pinctrl-0 = <&uart21_xfer>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host2_ehci {
status = "okay";
};
&usb_host2_ohci {
status = "okay";
};
&usb_otg {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

2
arch/arm/boot/dts/rk3288-evb.dtsi
View File

@ -97,7 +97,7 @@
};
panel: panel {
compatible ="lg,lp079qx1-sp0v", "simple-panel";
compatible = "lg,lp079qx1-sp0v", "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&lcd_cs>;

12
arch/arm/boot/dts/rk3288-tinker.dtsi
View File

@ -47,13 +47,13 @@
compatible = "gpio-leds";
act-led {
gpios=<&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
linux,default-trigger="mmc0";
gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
heartbeat-led {
gpios=<&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
linux,default-trigger="heartbeat";
gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
pwr-led {
@ -443,7 +443,7 @@
&saradc {
vref-supply = <&vcc18_ldo1>;
status ="okay";
status = "okay";
};
&sdmmc {
@ -516,7 +516,7 @@
};
&usb_otg {
status= "okay";
status = "okay";
};
&vopb {

101
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/input/input.h>
#include "rk3288-veyron.dtsi"
#include "rk3288-veyron-analog-audio.dtsi"
#include "rk3288-veyron-edp.dtsi"
#include "rk3288-veyron-sdmmc.dtsi"
/ {
@ -18,50 +19,6 @@
i2c20 = &i2c_tunnel;
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 0>;
post-pwm-on-delay-ms = <10>;
pwm-off-delay-ms = <10>;
};
gpio-charger {
compatible = "gpio-charger";
charger-type = "mains";
@ -85,21 +42,6 @@
};
};
panel: panel {
compatible ="innolux,n116bge", "simple-panel";
status = "okay";
power-supply = <&vcc33_lcd>;
backlight = <&backlight>;
ports {
panel_in: port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
};
/* A non-regulated voltage from power supply or battery */
vccsys: vccsys {
compatible = "regulator-fixed";
@ -141,33 +83,6 @@
};
};
&edp {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
ports {
edp_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
edp_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_edp>;
};
};
};
};
&edp_phy {
status = "okay";
};
&pwm0 {
status = "okay";
};
&rk808 {
vcc11-supply = <&vcc_5v>;
@ -220,14 +135,6 @@
};
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&pinctrl {
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
@ -250,12 +157,6 @@
&bt_dev_wake_sleep
>;
backlight {
bl_en: bl-en {
rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
ap_lid_int_l: ap-lid-int-l {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;

172
arch/arm/boot/dts/rk3288-veyron-edp.dtsi Normal file
View File

@ -0,0 +1,172 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron (and derivatives) fragment for the edp displays
*
* Copyright 2019 Google LLC
*/
/ {
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
vin-supply = <&vcc33_sys>;
startup-delay-us = <15000>;
};
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
vin-supply = <&vcc33_sys>;
};
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc18_wl>;
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 0>;
post-pwm-on-delay-ms = <10>;
pwm-off-delay-ms = <10>;
power-supply = <&backlight_regulator>;
};
panel: panel {
compatible = "innolux,n116bge", "simple-panel";
status = "okay";
power-supply = <&panel_regulator>;
backlight = <&backlight>;
panel-timing {
clock-frequency = <74250000>;
hactive = <1366>;
hfront-porch = <136>;
hback-porch = <60>;
hsync-len = <30>;
hsync-active = <0>;
vactive = <768>;
vfront-porch = <8>;
vback-porch = <12>;
vsync-len = <12>;
vsync-active = <0>;
};
ports {
panel_in: port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
};
};
&edp {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
ports {
edp_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
edp_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_edp>;
};
};
};
};
&edp_phy {
status = "okay";
};
&pwm0 {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bl_en: bl-en {
rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcd_enable_h: lcd-en {
rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
avdd_1v8_disp_en: avdd-1v8-disp-en {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

522
arch/arm/boot/dts/rk3288-veyron-fievel.dts Normal file
View File

@ -0,0 +1,522 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron Fievel Rev 0+ board device tree source
*
* Copyright 2016 Google, Inc
*/
/dts-v1/;
#include "rk3288-veyron.dtsi"
#include "rk3288-veyron-analog-audio.dtsi"
/ {
model = "Google Fievel";
compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
"google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
"google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
"google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
"google,veyron-fievel-rev0", "google,veyron-fievel",
"google,veyron", "rockchip,rk3288";
/delete-node/ bt-activity;
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vccsys";
regulator-boot-on;
regulator-always-on;
};
/*
* vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys,
* enabled by vcc_18
*/
vcc33_io: vcc33-io {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_io";
};
vcc5_host1: vcc5-host1-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hub_usb1_pwr_en>;
regulator-name = "vcc5_host1";
regulator-always-on;
regulator-boot-on;
};
vcc5_host2: vcc5-host2-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hub_usb2_pwr_en>;
regulator-name = "vcc5_host2";
regulator-always-on;
regulator-boot-on;
};
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_otg_pwr_en>;
regulator-name = "vcc5_otg";
regulator-always-on;
regulator-boot-on;
};
ext_gmac: external-gmac-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
};
};
&gmac {
status = "okay";
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
clock_in_out = "input";
phy-handle = <&ethphy>;
phy-mode = "rgmii";
phy-supply = <&vcc33_lan>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
rx_delay = <0x10>;
tx_delay = <0x30>;
/*
* Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low)
* with a 30ms settling time.
*/
snps,reset-gpio = <&gpio4 RK_PB0 0>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
wakeup-source;
mdio0 {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@1 {
reg = <1>;
};
};
};
&rk808 {
dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
<&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
vcc6-supply = <&vcc33_sys>;
vcc10-supply = <&vcc33_sys>;
vcc11-supply = <&vcc_5v>;
vcc12-supply = <&vcc33_sys>;
regulators {
/delete-node/ LDO_REG1;
/*
* According to the schematic, vcc18_lcdt is for
* HDMI_AVDD_1V8
*/
vcc18_lcdt: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vdd18_lcdt";
regulator-state-mem {
regulator-off-in-suspend;
};
};
/*
* This is not a pwren anymore, but the real power supply,
* vdd10_lcd for HDMI_AVDD_1V0
*/
vdd10_lcd: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
/* for usb camera */
vcc33_ccd: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_ccd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc33_lan: SWITCH_REG2 {
regulator-name = "vcc33_lan";
};
};
};
&sdio0 {
#address-cells = <1>;
#size-cells = <0>;
btmrvl: btmrvl@2 {
compatible = "marvell,sd8897-bt";
reg = <2>;
interrupt-parent = <&gpio4>;
interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
marvell,wakeup-pin = /bits/ 16 <13>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>;
};
};
&vcc50_hdmi {
enable-active-high;
gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
&vcc_5v {
enable-active-high;
gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&gpio0 {
gpio-line-names = "PMIC_SLEEP_AP",
"DDRIO_PWROFF",
"DDRIO_RETEN",
"TS3A227E_INT_L",
"PMIC_INT_L",
"PWR_KEY_L",
"HUB_USB1_nFALUT",
"PHY_PMEB",
"PHY_INT",
"REC_MODE_L",
"OTP_OUT",
"",
"USB_OTG_POWER_EN",
"AP_WARM_RESET_H",
"USB_OTG_nFALUT",
"I2C0_SDA_PMIC",
"I2C0_SCL_PMIC",
"DEVMODE_L",
"USB_INT";
};
&gpio2 {
gpio-line-names = "CONFIG0",
"CONFIG1",
"CONFIG2",
"",
"",
"",
"",
"CONFIG3",
"",
"EMMC_RST_L",
"",
"",
"BL_PWR_EN",
"",
"TOUCH_INT",
"TOUCH_RST",
"I2C3_SCL_TP",
"I2C3_SDA_TP";
};
&gpio3 {
gpio-line-names = "FLASH0_D0",
"FLASH0_D1",
"FLASH0_D2",
"FLASH0_D3",
"FLASH0_D4",
"FLASH0_D5",
"FLASH0_D6",
"FLASH0_D7",
"VCC5V_GOOD_H",
"",
"",
"",
"",
"",
"",
"",
"FLASH0_CS2/EMMC_CMD",
"",
"FLASH0_DQS/EMMC_CLKO",
"",
"",
"",
"",
"",
"PHY_TXD2",
"PHY_TXD3",
"MAC_RXD2",
"MAC_RXD3",
"PHY_TXD0",
"PHY_TXD1",
"MAC_RXD0",
"MAC_RXD1";
};
&gpio4 {
gpio-line-names = "MAC_MDC",
"MAC_RXDV",
"MAC_RXER",
"MAC_CLK",
"PHY_TXEN",
"MAC_MDIO",
"MAC_RXCLK",
"",
"PHY_RST",
"PHY_TXCLK",
"",
"",
"",
"",
"",
"",
"UART0_RXD",
"UART0_TXD",
"UART0_CTS_L",
"UART0_RTS_L",
"SDIO0_D0",
"SDIO0_D1",
"SDIO0_D2",
"SDIO0_D3",
"SDIO0_CMD",
"SDIO0_CLK",
"BT_DEV_WAKE",
"",
"WIFI_ENABLE_H",
"BT_ENABLE_L",
"WIFI_HOST_WAKE",
"BT_HOST_WAKE";
};
&gpio5 {
gpio-line-names = "",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"USB_OTG_CTL1",
"HUB_USB2_CTL1",
"HUB_USB2_PWR_EN",
"HUB_USB_ILIM_SEL",
"USB_OTG_STATUS_L",
"HUB_USB1_CTL1",
"HUB_USB1_PWR_EN",
"VCC50_HDMI_EN";
};
&gpio6 {
gpio-line-names = "I2S0_SCLK",
"I2S0_LRCK_RX",
"I2S0_LRCK_TX",
"I2S0_SDI",
"I2S0_SDO0",
"HP_DET_H",
"",
"INT_CODEC",
"I2S0_CLK",
"I2C2_SDA",
"I2C2_SCL",
"MICDET",
"",
"",
"",
"",
"HUB_USB2_nFALUT",
"USB_OTG_ILIM_SEL";
};
&gpio7 {
gpio-line-names = "LCD_BL_PWM",
"PWM_LOG",
"BL_EN",
"PWR_LED1",
"TPM_INT_H",
"SPK_ON",
"FW_WP_AP",
"",
"CPU_NMI",
"DVSOK",
"",
"EDP_HPD",
"DVS1",
"",
"LCD_EN",
"DVS2",
"HDMI_CEC",
"I2C4_SDA",
"I2C4_SCL",
"I2C5_SDA_HDMI",
"I2C5_SCL_HDMI",
"5V_DRV",
"UART2_RXD",
"UART2_TXD";
};
&gpio8 {
gpio-line-names = "RAM_ID0",
"RAM_ID1",
"RAM_ID2",
"RAM_ID3",
"I2C1_SDA_TPM",
"I2C1_SCL_TPM",
"SPI2_CLK",
"SPI2_CS0",
"SPI2_RXD",
"SPI2_TXD";
};
&pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* For usb bc1.2 */
&usb_otg_ilim_sel
&usb_usb_ilim_sel
/* Wake only */
&bt_dev_wake_awake
&pwr_led1_on
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* For usb bc1.2 */
&usb_otg_ilim_sel
&usb_usb_ilim_sel
/* Sleep only */
&bt_dev_wake_sleep
&pwr_led1_blink
>;
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gmac {
phy_rst: phy-rst {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
};
phy_pmeb: phy-pmeb {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_int: phy-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
pwr_led1_on: pwr-led1-on {
rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>;
};
pwr_led1_blink: pwr-led1-blink {
rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
};
};
pmic {
dvs_1: dvs-1 {
rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
dvs_2: dvs-2 {
rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb-bc12 {
usb_otg_ilim_sel: usb-otg-ilim-sel {
rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
};
usb_usb_ilim_sel: usb-usb-ilim-sel {
rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
};
};
usb-host {
hub_usb1_pwr_en: hub_usb1_pwr_en {
rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
hub_usb2_pwr_en: hub_usb2_pwr_en {
rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb_otg_pwr_en: usb_otg_pwr_en {
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

55
arch/arm/boot/dts/rk3288-veyron-jaq.dts
View File

@ -16,40 +16,6 @@
"google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
"google,veyron-jaq-rev1", "google,veyron-jaq",
"google,veyron", "rockchip,rk3288";
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc18_wl>;
};
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
vin-supply = <&vcc33_sys>;
startup-delay-us = <15000>;
};
};
&backlight {
@ -87,11 +53,6 @@
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
power-supply = <&backlight_regulator>;
};
&panel {
power-supply = <&panel_regulator>;
};
&rk808 {
@ -343,12 +304,6 @@
};
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
@ -361,16 +316,6 @@
};
};
lcd {
lcd_enable_h: lcd-en {
rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
avdd_1v8_disp_en: avdd-1v8-disp-en {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dvs_1: dvs-1 {
rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;

207
arch/arm/boot/dts/rk3288-veyron-jerry.dts
View File

@ -18,48 +18,6 @@
"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
"google,veyron-jerry-rev3", "google,veyron-jerry",
"google,veyron", "rockchip,rk3288";
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc18_wl>;
};
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
vin-supply = <&vcc33_sys>;
startup-delay-us = <15000>;
};
};
&backlight {
power-supply = <&backlight_regulator>;
};
&panel {
power-supply= <&panel_regulator>;
};
&rk808 {
@ -82,6 +40,155 @@
};
};
&sdio0 {
#address-cells = <1>;
#size-cells = <0>;
mwifiex: wifi@1 {
compatible = "marvell,sd8897";
reg = <1>;
marvell,caldata-txpwrlimit-2g = /bits/ 8 <
0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09>;
marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 <
0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01
0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c
0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c
0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c
0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 <
0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01
0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c
0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c
0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c
0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01
0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 <
0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01
0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a
0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08
0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a
0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1
0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08
0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04
0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05
0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b
0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08
0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04
0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05
0x1a 0x05 0x1b 0x05>;
};
};
&sdmmc {
disable-wp;
pinctrl-names = "default";
@ -311,12 +418,6 @@
};
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
@ -329,16 +430,6 @@
};
};
lcd {
lcd_enable_h: lcd-en {
rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
avdd_1v8_disp_en: avdd-1v8-disp-en {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dvs_1: dvs-1 {
rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;

66
arch/arm/boot/dts/rk3288-veyron-minnie.dts
View File

@ -15,40 +15,6 @@
"google,veyron-minnie-rev0", "google,veyron-minnie",
"google,veyron", "rockchip,rk3288";
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
vin-supply = <&vcc33_sys>;
startup-delay-us = <15000>;
};
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc18_wl>;
};
volume_buttons: volume-buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
@ -105,7 +71,6 @@
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
power-supply = <&backlight_regulator>;
};
&i2c_tunnel {
@ -137,7 +102,20 @@
&panel {
compatible = "auo,b101ean01", "simple-panel";
power-supply= <&panel_regulator>;
/delete-node/ panel-timing;
panel-timing {
clock-frequency = <66666667>;
hactive = <1280>;
hfront-porch = <18>;
hback-porch = <21>;
hsync-len = <32>;
vactive = <800>;
vfront-porch = <4>;
vback-porch = <8>;
vsync-len = <18>;
};
};
&rk808 {
@ -397,12 +375,6 @@
};
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
@ -425,16 +397,6 @@
};
};
lcd {
lcd_enable_h: lcd-en {
rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
avdd_1v8_disp_en: avdd-1v8-disp-en {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dvs_1: dvs-1 {
rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;

17
arch/arm/boot/dts/rk3288-veyron-pinky.dts
View File

@ -14,7 +14,14 @@
compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
"google,veyron", "rockchip,rk3288";
/delete-node/backlight-regulator;
/delete-node/panel-regulator;
/delete-node/emmc-pwrseq;
/delete-node/vcc18-lcd;
};
&backlight {
/delete-property/power-supply;
};
&emmc {
@ -52,7 +59,17 @@
i2c-scl-rising-time-ns = <300>;
};
&panel {
power-supply = <&vcc33_lcd>;
};
&pinctrl {
/delete-node/ lcd;
backlight {
/delete-node/ bl_pwr_en;
};
buttons {
pwr_key_h: pwr-key-h {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;

58
arch/arm/boot/dts/rk3288-veyron-speedy.dts
View File

@ -16,44 +16,6 @@
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc18_wl>;
};
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
vin-supply = <&vcc33_sys>;
startup-delay-us = <15000>;
};
};
&backlight {
power-supply = <&backlight_regulator>;
};
&cpu_alert0 {
@ -83,10 +45,6 @@
temperature = <90000>;
};
&panel {
power-supply= <&panel_regulator>;
};
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
@ -321,12 +279,6 @@
};
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
@ -339,16 +291,6 @@
};
};
lcd {
lcd_enable_h: lcd-en {
rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
avdd_1v8_disp_en: avdd-1v8-disp-en {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dvs_1: dvs-1 {
rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;

118
arch/arm/boot/dts/rk3288-veyron-tiger.dts Normal file
View File

@ -0,0 +1,118 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron Tiger Rev 0+ board device tree source
*
* Copyright 2016 Google, Inc
*/
/dts-v1/;
#include "rk3288-veyron-fievel.dts"
#include "rk3288-veyron-edp.dtsi"
/ {
model = "Google Tiger";
compatible = "google,veyron-tiger-rev8", "google,veyron-tiger-rev7",
"google,veyron-tiger-rev6", "google,veyron-tiger-rev5",
"google,veyron-tiger-rev4", "google,veyron-tiger-rev3",
"google,veyron-tiger-rev2", "google,veyron-tiger-rev1",
"google,veyron-tiger-rev0", "google,veyron-tiger",
"google,veyron", "rockchip,rk3288";
/delete-node/ vcc18-lcd;
};
&backlight {
/* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */
brightness-levels = <
0 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
};
&backlight_regulator {
vin-supply = <&vccsys>;
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <300>;
touchscreen@10 {
compatible = "elan,ekth3500";
reg = <0x10>;
interrupt-parent = <&gpio2>;
interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int &touch_rst>;
reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
vcc33-supply = <&vcc33_io>;
vccio-supply = <&vcc33_io>;
wakeup-source;
};
};
&panel {
compatible = "auo,b101ean01", "simple-panel";
/delete-node/ panel-timing;
panel-timing {
clock-frequency = <66666667>;
hactive = <1280>;
hfront-porch = <18>;
hback-porch = <21>;
hsync-len = <32>;
vactive = <800>;
vfront-porch = <4>;
vback-porch = <8>;
vsync-len = <18>;
};
};
&pinctrl {
lcd {
/delete-node/ avdd-1v8-disp-en;
};
touchscreen {
touch_int: touch-int {
rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
touch_rst: touch-rst {
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

4
arch/arm/boot/dts/rk3288-veyron.dtsi
View File

@ -586,6 +586,10 @@
rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
};
/*
* We run sdio0 at max speed; bump up drive strength.
* We also have external pulls, so disable the internal ones.