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[ARM] 3829/1: iop3xx: optimise irq entry macros 

Squeeze three instructions out of the iop32x irq demuxer, and nine
out of the iop33x irq demuxer by using the hardware vector generator.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Lennert Buytenhek 2006-09-18 23:24:10 +01:00 committed by Russell King
parent d7d214e974
commit 7412b10f79
3 changed files with 24 additions and 24 deletions
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16
arch/arm/mach-iop33x/irq.c
View File

@ -57,6 +57,20 @@ static inline void intstr_write1(u32 val)
iop3xx_cp6_disable(); iop3xx_cp6_disable();
} }
static inline void intbase_write(u32 val)
{
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
}
static inline void intsize_write(u32 val)
{
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
}
static void static void
iop331_irq_mask1 (unsigned int irq) iop331_irq_mask1 (unsigned int irq)
{ {
@ -107,6 +121,8 @@ void __init iop331_init_irq(void)
intctl_write1(0); intctl_write1(0);
intstr_write0(0); // treat all as IRQ intstr_write0(0); // treat all as IRQ
intstr_write1(0); intstr_write1(0);
intbase_write(0);
intsize_write(1);
if(machine_is_iq80331()) // all interrupts are inputs to chip if(machine_is_iq80331()) // all interrupts are inputs to chip
*IOP3XX_PCIIRSR = 0x0f; *IOP3XX_PCIIRSR = 0x0f;

10
include/asm-arm/arch-iop32x/entry-macro.S
View File

@ -16,13 +16,9 @@
* Note: only deal with normal interrupts, not FIQ * Note: only deal with normal interrupts, not FIQ
*/ */
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
ldr \base, =IOP3XX_REG_ADDR(0x07D8) ldr \base, =IOP3XX_REG_ADDR(0x07D8)
ldr \irqstat, [\base] @ Read IINTSRC ldr \irqstat, [\base] @ Read IINTSRC
cmp \irqstat, #0 cmp \irqstat, #0
beq 1001f clzne \irqnr, \irqstat
clz \irqnr, \irqstat rsbne \irqnr, \irqnr, #31
mov \base, #31
subs \irqnr,\base,\irqnr
1001:
.endm .endm

22
include/asm-arm/arch-iop33x/entry-macro.S
View File

@ -12,23 +12,11 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
/*
* Note: only deal with normal interrupts, not FIQ
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0 ldr \base, =IOP3XX_REG_ADDR(0x07C8)
ldr \base, =IOP3XX_REG_ADDR(0x7A0) ldr \irqstat, [\base] @ Read IINTVEC
ldr \irqstat, [\base] @ Read IINTSRC0
cmp \irqstat, #0
bne 1002f
ldr \irqstat, [\base, #4] @ Read IINTSRC1
cmp \irqstat, #0 cmp \irqstat, #0
beq 1001f ldreq \irqstat, [\base] @ erratum 63 workaround
clz \irqnr, \irqstat adds \irqnr, \irqstat, #1
rsbs \irqnr,\irqnr,#31 @ recommend by RMK movne \irqnr, \irqstat, lsr #2
add \irqnr,\irqnr,#IRQ_IOP331_XINT8
b 1001f
1002: clz \irqnr, \irqstat
rsbs \irqnr,\irqnr,#31 @ recommend by RMK
1001:
.endm .endm