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SoC-level changes for tegra and omap 

This adds support for the new tegra30 SoC, as well as small
 changes to support minor variations of existing omap SoCs.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIVAwUATwtVn2CrR//JCVInAQKJZBAAud0Ug5o0+PsOsyH4y8N4OYBQyfkB6aVh
 5ClZkc83jMQRA+chjI/wFzYR+3BGz0nlzuVOe7r+YI8YQPAZjJgvMmgIAycfRdq9
 bNKEqd6i08RMqx9S7vxWaUzK4WOCTvbl9yvpCNp9EkbbDi2xsBWbv6X75hRNWLJB
 8uDlCCC9gfoo29kp+XjE0auqGlhUu8fPRHiviJlRUBYBeGuH03CZEHVn12joJMnK
 zDh+gSb3EuxI8Hd2vHJ6bwt7DexEXaHdsbQwF4SdtRjt5mMmu/xY7rvMGdK3lFJz
 /oR6OoKseJEJ+Tdx0OA6vXn+BOkIWEeHbMGfrpjnitATJCmXqeGk5vSSR7NDYmHC
 4qtqQ6NwcIIBBLiYhksuHv2bIkIbaB94mCge3Yf0s8NSHGZJTozTIrB1gtO0v8AX
 9cpBorIDbg9mIOiWCBR2wVgYOw6cCCUPAbF0JJ+/GMdkjetxITHjqEDzUYzlgPDD
 T+63U1HSRJyYzgMXEfW4WbshXILuFJSrHzHpPLWBJuCH3xdlmnKV1g/6lvia7V2f
 NMGwCvreWrOBa9FbGvtVamEoLFEyKCXZbFEvuN0kIJ6czCkcRq6EIsaXJL9s4iPk
 27mwCpCJvfc8c+ocCsVcWl/fWHtCXmeMeotmzdLA7/L6YIx8YdvY8RpgAXDv9jA7
 +dt4jW+tjEE=
 =hp8k
 -----END PGP SIGNATURE-----

Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

SoC-level changes for tegra and omap

This adds support for the new tegra30 SoC, as well as small
changes to support minor variations of existing omap SoCs.

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
  arm/tegra: Compile tegra_dt_init_irq only when CONFIG_OF
  arm/tegra: Make MACH_TEGRA_DT depend on ARCH_TEGRA_2x_SOC
  arm/tegra: Delete tegra_init_clock()
  arm/tegra: Fix section mismatch errors in tegra30 pinmux
  arm/tegra: Fix section mismatch errors in tegra20 pinmux
  arm/tegra: refresh defconfig for tegra30
  arm/tegra: add support for tegra30 based board cardhu
  arm/tegra: implement support for tegra30
  arm/tegra: pinmux tables and definitions for tegra30
  arm/tegra: add new fields to struct tegra_pingroup_desc
  arm/tegra: prepare pinmux code for multiple tegra variants
  arm/tegra: rename tegra20 pinmux files
  arm/tegra: generalize L2 cache initialization
  arm/tegra: use PMC reset
  arm/tegra: rename board-dt.c to board-dt-tegra20.c
  arm/tegra: prepare early init for multiple tegra variants
  arm/tegra: don't export clk_measure_input_freq
  arm/tegra: prepare clock code for multiple tegra variants
  arm/tegra: cleanup tegra20 support
  arm/tegra: clk_get should not be fatal
  ...

Fix up trivial conflict in arch/arm/mach-tegra/board-dt-tegra20.c
This commit is contained in:
Linus Torvalds 2012-01-09 14:33:17 -08:00
parent 190a44e65b 23c4c1c7b0
commit 7400c12eb0
54 changed files with 1399 additions and 250 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
arch/arm/boot/dts/tegra-cardhu.dts Normal file
View File

@ -0,0 +1,36 @@
/dts-v1/;
/include/ "tegra30.dtsi"
/ {
model = "NVIDIA Tegra30 Cardhu evaluation board";
compatible = "nvidia,cardhu", "nvidia,tegra30";
memory {
reg = < 0x80000000 0x40000000 >;
};
serial@70006000 {
clock-frequency = < 408000000 >;
};
i2c@7000c000 {
clock-frequency = <100000>;
};
i2c@7000c400 {
clock-frequency = <100000>;
};
i2c@7000c500 {
clock-frequency = <100000>;
};
i2c@7000c700 {
clock-frequency = <100000>;
};
i2c@7000d000 {
clock-frequency = <100000>;
};
};

9
arch/arm/configs/tegra_defconfig
View File

@ -9,9 +9,8 @@ CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
@ -20,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_TEGRA_2x_SOC=y
CONFIG_ARCH_TEGRA_3x_SOC=y
CONFIG_MACH_HARMONY=y
CONFIG_MACH_KAEN=y
CONFIG_MACH_PAZ00=y
@ -78,14 +79,12 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_NET_ETHERNET=y
CONFIG_R8169=y
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
CONFIG_USB_PEGASUS=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC75XX=y
CONFIG_USB_NET_SMSC95XX=y
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set

11
arch/arm/mach-omap2/Kconfig
View File

@ -78,8 +78,13 @@ config SOC_OMAP3430
default y
select ARCH_OMAP_OTG
config SOC_OMAPTI816X
bool "TI816X support"
config SOC_OMAPTI81XX
bool "TI81XX support"
depends on ARCH_OMAP3
default y
config SOC_OMAPAM33XX
bool "AM33XX support"
depends on ARCH_OMAP3
default y
@ -316,7 +321,7 @@ config MACH_OMAP_3630SDP
config MACH_TI8168EVM
bool "TI8168 Evaluation Module"
depends on SOC_OMAPTI816X
depends on SOC_OMAPTI81XX
default y
config MACH_OMAP_4430SDP

11
arch/arm/mach-omap2/board-ti8168evm.c
View File

@ -35,17 +35,12 @@ static void __init ti8168_evm_init(void)
omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
}
static void __init ti8168_evm_map_io(void)
{
omapti816x_map_common_io();
}
MACHINE_START(TI8168EVM, "ti8168evm")
/* Maintainer: Texas Instruments */
.atag_offset = 0x100,
.map_io = ti8168_evm_map_io,
.init_early = ti816x_init_early,
.init_irq = ti816x_init_irq,
.map_io = ti81xx_map_io,
.init_early = ti81xx_init_early,
.init_irq = ti81xx_init_irq,
.timer = &omap3_timer,
.init_machine = ti8168_evm_init,
.restart = omap_prcm_restart,

2
arch/arm/mach-omap2/clock.c
View File

@ -35,7 +35,7 @@
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
u8 cpu_mask;
u16 cpu_mask;
/*
* clkdm_control: if true, then when a clock is enabled in the

2
arch/arm/mach-omap2/clock.h
View File

@ -132,7 +132,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
const char *core_ck_name,
const char *mpu_ck_name);
extern u8 cpu_mask;
extern u16 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_dummy;

6
arch/arm/mach-omap2/clock3xxx_data.c
View File

@ -3517,6 +3517,10 @@ int __init omap3xxx_clk_init(void)
} else if (cpu_is_ti816x()) {
cpu_mask = RATE_IN_TI816X;
cpu_clkflg = CK_TI816X;
} else if (cpu_is_am33xx()) {
cpu_mask = RATE_IN_AM33XX;
} else if (cpu_is_ti814x()) {
cpu_mask = RATE_IN_TI814X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
@ -3600,7 +3604,7 @@ int __init omap3xxx_clk_init(void)
* Lock DPLL5 -- here only until other device init code can
* handle this
*/
if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */

48
arch/arm/mach-omap2/common.c
View File

@ -110,23 +110,49 @@ void __init omap3_map_io(void)
/*
* Adjust TAP register base such that omap3_check_revision accesses the correct
* TI816X register for checking device ID (it adds 0x204 to tap base while
* TI816X DEVICE ID register is at offset 0x600 from control base).
* TI81XX register for checking device ID (it adds 0x204 to tap base while
* TI81XX DEVICE ID register is at offset 0x600 from control base).
*/
#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \
TI816X_CONTROL_DEVICE_ID - 0x204)
#define TI81XX_TAP_BASE (TI81XX_CTRL_BASE + \
TI81XX_CONTROL_DEVICE_ID - 0x204)
static struct omap_globals ti816x_globals = {
static struct omap_globals ti81xx_globals = {
.class = OMAP343X_CLASS,
.tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
.ctrl = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
.prm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
.cm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
.tap = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
.ctrl = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
.prm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
.cm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
};
void __init omap2_set_globals_ti816x(void)
void __init omap2_set_globals_ti81xx(void)
{
__omap2_set_globals(&ti816x_globals);
__omap2_set_globals(&ti81xx_globals);
}
void __init ti81xx_map_io(void)
{
omapti81xx_map_common_io();
}
#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + \
TI81XX_CONTROL_DEVICE_ID - 0x204)
static struct omap_globals am33xx_globals = {
.class = AM335X_CLASS,
.tap = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
.ctrl = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
.prm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
.cm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
};
void __init omap2_set_globals_am33xx(void)
{
__omap2_set_globals(&am33xx_globals);
}
void __init am33xx_map_io(void)
{
omapam33xx_map_common_io();
}
#endif

23
arch/arm/mach-omap2/common.h
View File

@ -52,10 +52,18 @@ static inline void omap34xx_map_common_io(void)
}
#endif
#ifdef CONFIG_SOC_OMAPTI816X
extern void omapti816x_map_common_io(void);
#ifdef CONFIG_SOC_OMAPTI81XX
extern void omapti81xx_map_common_io(void);
#else
static inline void omapti816x_map_common_io(void)
static inline void omapti81xx_map_common_io(void)
{
}
#endif
#ifdef CONFIG_SOC_OMAPAM33XX
extern void omapam33xx_map_common_io(void);
#else
static inline void omapam33xx_map_common_io(void)
{
}
#endif
@ -82,7 +90,7 @@ void omap35xx_init_early(void);
void omap3630_init_early(void);
void omap3_init_early(void); /* Do not use this one */
void am35xx_init_early(void);
void ti816x_init_early(void);
void ti81xx_init_early(void);
void omap4430_init_early(void);
void omap_prcm_restart(char, const char *);
@ -107,7 +115,8 @@ void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_3xxx(void);
void omap2_set_globals_443x(void);
void omap2_set_globals_ti816x(void);
void omap2_set_globals_ti81xx(void);
void omap2_set_globals_am33xx(void);
/* These get called from omap2_set_globals_xxxx(), do not call these */
void omap2_set_globals_tap(struct omap_globals *);
@ -118,7 +127,9 @@ void omap2_set_globals_prcm(struct omap_globals *);
void omap242x_map_io(void);
void omap243x_map_io(void);
void omap3_map_io(void);
void am33xx_map_io(void);
void omap4_map_io(void);
void ti81xx_map_io(void);
/**
* omap_test_timeout - busy-loop, testing a condition
@ -147,7 +158,7 @@ extern struct device *omap4_get_dsp_device(void);
void omap2_init_irq(void);
void omap3_init_irq(void);
void ti816x_init_irq(void);
void ti81xx_init_irq(void);
extern int omap_irq_pending(void);
void omap_intc_save_context(void);
void omap_intc_restore_context(void);

8
arch/arm/mach-omap2/control.h
View File

@ -52,8 +52,8 @@
#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
/* TI816X spefic control submodules */
#define TI816X_CONTROL_DEVCONF 0x600
/* TI81XX spefic control submodules */
#define TI81XX_CONTROL_DEVCONF 0x600
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
@ -244,8 +244,8 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
/* TI816X CONTROL_DEVCONF register offsets */
#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000)
/* TI81XX CONTROL_DEVCONF register offsets */
#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
/*
* REVISIT: This list of registers is not comprehensive - there are more

52
arch/arm/mach-omap2/id.c
View File

@ -226,7 +226,7 @@ static void __init omap4_check_features(void)
}
}
static void __init ti816x_check_features(void)
static void __init ti81xx_check_features(void)
{
omap_features = OMAP3_HAS_NEON;
}
@ -340,6 +340,29 @@ static void __init omap3_check_revision(const char **cpu_rev)
break;
}
break;
case 0xb944:
omap_revision = AM335X_REV_ES1_0;
*cpu_rev = "1.0";
case 0xb8f2:
switch (rev) {
case 0:
/* FALLTHROUGH */
case 1:
omap_revision = TI8148_REV_ES1_0;
*cpu_rev = "1.0";
break;
case 2:
omap_revision = TI8148_REV_ES2_0;
*cpu_rev = "2.0";
break;
case 3:
/* FALLTHROUGH */
default:
omap_revision = TI8148_REV_ES2_1;
*cpu_rev = "2.1";
break;
}
break;
default:
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP3630_REV_ES1_2;
@ -367,7 +390,7 @@ static void __init omap4_check_revision(void)
* Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
* Use ARM register to detect the correct ES version
*/
if (!rev && (hawkeye != 0xb94e)) {
if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
idcode = read_cpuid(CPUID_ID);
rev = (idcode & 0xf) - 1;
}
@ -389,8 +412,11 @@ static void __init omap4_check_revision(void)
omap_revision = OMAP4430_REV_ES2_1;
break;
case 4:
default:
omap_revision = OMAP4430_REV_ES2_2;
break;
case 6:
default:
omap_revision = OMAP4430_REV_ES2_3;
}
break;
case 0xb94e:
@ -401,9 +427,17 @@ static void __init omap4_check_revision(void)
break;
}
break;
case 0xb975:
switch (rev) {
case 0:
default:
omap_revision = OMAP4470_REV_ES1_0;
break;
}
break;
default:
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP4430_REV_ES2_2;
omap_revision = OMAP4430_REV_ES2_3;
}
pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@ -432,6 +466,10 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
} else if (cpu_is_ti816x()) {
cpu_name = "TI816X";
} else if (cpu_is_am335x()) {
cpu_name = "AM335X";
} else if (cpu_is_ti814x()) {
cpu_name = "TI814X";
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
cpu_name = "OMAP3430/3530";
@ -472,11 +510,11 @@ void __init omap2_check_revision(void)
} else if (cpu_is_omap34xx()) {
omap3_check_revision(&cpu_rev);
/* TI816X doesn't have feature register */
if (!cpu_is_ti816x())
/* TI81XX doesn't have feature register */
if (!cpu_is_ti81xx())
omap3_check_features();
else
ti816x_check_features();
ti81xx_check_features();
omap3_cpuinfo(cpu_rev);
return;

12
arch/arm/mach-omap2/include/mach/debug-macro.S
View File

@ -66,11 +66,11 @@ omap_uart_lsr: .word 0
beq 34f @ configure OMAP3UART4
cmp \rp, #OMAP4UART4 @ only on 44xx
beq 44f @ configure OMAP4UART4
cmp \rp, #TI816XUART1 @ ti816x UART offsets different
cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
beq 81f @ configure UART1
cmp \rp, #TI816XUART2 @ ti816x UART offsets different
cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
beq 82f @ configure UART2
cmp \rp, #TI816XUART3 @ ti816x UART offsets different
cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
beq 83f @ configure UART3
cmp \rp, #ZOOM_UART @ only on zoom2/3
beq 95f @ configure ZOOM_UART
@ -94,11 +94,11 @@ omap_uart_lsr: .word 0
b 98f
44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
b 98f
81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE)
81: mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
b 98f
82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE)
82: mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
b 98f
83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
b 98f
95: ldr \rp, =ZOOM_UART_BASE

38
arch/arm/mach-omap2/io.c
View File

@ -176,14 +176,31 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
};
#endif
#ifdef CONFIG_SOC_OMAPTI816X
static struct map_desc omapti816x_io_desc[] __initdata = {
#ifdef CONFIG_SOC_OMAPTI81XX
static struct map_desc omapti81xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
}
};
#endif
#ifdef CONFIG_SOC_OMAPAM33XX
static struct map_desc omapam33xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_WK_AM33XX_VIRT,
.pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
.length = L4_WK_AM33XX_SIZE,
.type = MT_DEVICE
}
};
#endif
@ -263,10 +280,17 @@ void __init omap34xx_map_common_io(void)
}
#endif
#ifdef CONFIG_SOC_OMAPTI816X
void __init omapti816x_map_common_io(void)
#ifdef CONFIG_SOC_OMAPTI81XX
void __init omapti81xx_map_common_io(void)
{
iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
}
#endif
#ifdef CONFIG_SOC_OMAPAM33XX
void __init omapam33xx_map_common_io(void)
{
iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
}
#endif
@ -418,9 +442,9 @@ void __init am35xx_init_early(void)
omap3_init_early();
}
void __init ti816x_init_early(void)
void __init ti81xx_init_early(void)
{
omap2_set_globals_ti816x();
omap2_set_globals_ti81xx();
omap_common_init_early();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();

2
arch/arm/mach-omap2/irq.c
View File

@ -193,7 +193,7 @@ void __init omap3_init_irq(void)
omap_init_irq(OMAP34XX_IC_BASE, 96);
}
void __init ti816x_init_irq(void)
void __init ti81xx_init_irq(void)
{
omap_init_irq(OMAP34XX_IC_BASE, 128);
}

2
arch/arm/mach-omap2/opp2xxx.h
View File

@ -51,7 +51,7 @@ struct prcm_config {
unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
unsigned long base_sdrc_rfr; /* base refresh timing for a set */
unsigned char flags;
unsigned short flags;
};

6
arch/arm/mach-omap2/serial.c
View File

@ -464,7 +464,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
mod_timer(&uart->timer, jiffies + uart->timeout);
omap_uart_smart_idle_enable(uart, 0);
if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx())) {
u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
u32 wk_mask = 0;
u32 padconf = 0;
@ -746,7 +746,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
*/
uart->regshift = p->regshift;
uart->membase = p->membase;
if (cpu_is_omap44xx() || cpu_is_ti816x())
if (cpu_is_omap44xx() || cpu_is_ti81xx())
uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
@ -828,7 +828,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
}
/* Enable the MDR1 errata for OMAP3 */
if (cpu_is_omap34xx() && !cpu_is_ti816x())
if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx()))
uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
}

31
arch/arm/mach-tegra/Kconfig
View File

@ -2,11 +2,8 @@ if ARCH_TEGRA
comment "NVIDIA Tegra options"
choice
prompt "Select Tegra processor family for target system"
config ARCH_TEGRA_2x_SOC
bool "Tegra 2 family"
bool "Enable support for Tegra20 family"
select CPU_V7
select ARM_GIC
select ARCH_REQUIRE_GPIOLIB
@ -17,22 +14,36 @@ config ARCH_TEGRA_2x_SOC
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
endchoice
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
select CPU_V7
select ARM_GIC
select ARCH_REQUIRE_GPIOLIB
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_SUPPORT
select USB_ULPI_VIEWPORT if USB_SUPPORT
select USE_OF
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config TEGRA_PCI
bool "PCI Express support"
depends on ARCH_TEGRA_2x_SOC
select PCI
comment "Tegra board type"
config MACH_HARMONY
bool "Harmony board"
depends on ARCH_TEGRA_2x_SOC
select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
help
Support for nVidia Harmony development platform
config MACH_KAEN
bool "Kaen board"
depends on ARCH_TEGRA_2x_SOC
select MACH_SEABOARD
select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
help
@ -40,11 +51,13 @@ config MACH_KAEN
config MACH_PAZ00
bool "Paz00 board"
depends on ARCH_TEGRA_2x_SOC
help
Support for the Toshiba AC100/Dynabook AZ netbook
config MACH_SEABOARD
bool "Seaboard board"
depends on ARCH_TEGRA_2x_SOC
select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
help
Support for nVidia Seaboard development platform. It will
@ -52,25 +65,29 @@ config MACH_SEABOARD
have large similarities with the seaboard design.
config MACH_TEGRA_DT
bool "Generic Tegra board (FDT support)"
bool "Generic Tegra20 board (FDT support)"
depends on ARCH_TEGRA_2x_SOC
select USE_OF
help
Support for generic nVidia Tegra boards using Flattened Device Tree
Support for generic NVIDIA Tegra20 boards using Flattened Device Tree
config MACH_TRIMSLICE
bool "TrimSlice board"
depends on ARCH_TEGRA_2x_SOC
select TEGRA_PCI
help
Support for CompuLab TrimSlice platform
config MACH_WARIO
bool "Wario board"
depends on ARCH_TEGRA_2x_SOC
select MACH_SEABOARD
help
Support for the Wario version of Seaboard
config MACH_VENTANA
bool "Ventana board"
depends on ARCH_TEGRA_2x_SOC
select MACH_TEGRA_DT
help
Support for the nVidia Ventana development platform

9
arch/arm/mach-tegra/Makefile
View File

@ -5,12 +5,13 @@ obj-y += irq.o
obj-y += clock.o
obj-y += timer.o
obj-y += pinmux.o
obj-y += powergate.o
obj-y += fuse.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o
@ -29,7 +30,7 @@ obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o
obj-$(CONFIG_MACH_SEABOARD) += board-seaboard.o
obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o
obj-$(CONFIG_MACH_TEGRA_DT) += board-dt.o
obj-$(CONFIG_MACH_TEGRA_DT) += board-dt-tegra20.o
obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o
obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o
obj-$(CONFIG_MACH_TEGRA_DT) += board-paz00-pinmux.o

1
arch/arm/mach-tegra/Makefile.boot
View File

@ -7,3 +7,4 @@ dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb
dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb
dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb

19
arch/arm/mach-tegra/board-dt.c → arch/arm/mach-tegra/board-dt-tegra20.c
View File

@ -53,17 +53,6 @@ void seaboard_pinmux_init(void);
void trimslice_pinmux_init(void);
void ventana_pinmux_init(void);
static const struct of_device_id tegra_dt_irq_match[] __initconst = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
{ }
};
void __init tegra_dt_init_irq(void)
{
tegra_init_irq();
of_irq_init(tegra_dt_irq_match);
}
struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
@ -139,7 +128,7 @@ static void __init tegra_dt_init(void)
"Unknown platform! Pinmuxing not initialized\n");
}
static const char * tegra_dt_board_compat[] = {
static const char *tegra20_dt_board_compat[] = {
"compulab,trimslice",
"nvidia,harmony",
"compal,paz00",
@ -148,13 +137,13 @@ static const char * tegra_dt_board_compat[] = {
NULL
};
DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,
.init_early = tegra20_init_early,
.init_irq = tegra_dt_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,
.init_machine = tegra_dt_init,
.restart = tegra_assert_system_reset,
.dt_compat = tegra_dt_board_compat,
.dt_compat = tegra20_dt_board_compat,
MACHINE_END

63
arch/arm/mach-tegra/board-dt-tegra30.c Normal file
View File

@ -0,0 +1,63 @@
/*
* arch/arm/mach-tegra/board-dt-tegra30.c
*
* NVIDIA Tegra30 device tree board support
*
* Copyright (C) 2011 NVIDIA Corporation
*
* Derived from:
*
* arch/arm/mach-tegra/board-dt-tegra20.c
*
* Copyright (C) 2010 Secret Lab Technologies, Ltd.
* Copyright (C) 2010 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include "board.h"
static struct of_device_id tegra_dt_match_table[] __initdata = {
{ .compatible = "simple-bus", },
{}
};
static void __init tegra30_dt_init(void)
{
of_platform_populate(NULL, tegra_dt_match_table,
NULL, NULL);
}
static const char *tegra30_dt_board_compat[] = {
"nvidia,cardhu",
NULL
};
DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
.map_io = tegra_map_common_io,
.init_early = tegra30_init_early,
.init_irq = tegra_dt_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,
.init_machine = tegra30_dt_init,
.restart = tegra_assert_system_reset,
.dt_compat = tegra30_dt_board_compat,
MACHINE_END

1
arch/arm/mach-tegra/board-harmony-pcie.c
View File

@ -23,6 +23,7 @@
#include <asm/mach-types.h>
#include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include "board.h"
#include "board-harmony.h"

1
arch/arm/mach-tegra/board-harmony-pinmux.c
View File

@ -19,6 +19,7 @@
#include <linux/of.h>
#include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include "gpio-names.h"
#include "board-harmony.h"

2
arch/arm/mach-tegra/board-harmony.c
View File

@ -186,7 +186,7 @@ MACHINE_START(HARMONY, "harmony")
.atag_offset = 0x100,
.fixup = tegra_harmony_fixup,
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,
.init_early = tegra20_init_early,
.init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,

1
arch/arm/mach-tegra/board-paz00-pinmux.c
View File

@ -19,6 +19,7 @@
#include <linux/of.h>
#include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include "gpio-names.h"
#include "board-paz00.h"

2
arch/arm/mach-tegra/board-paz00.c
View File

@ -189,7 +189,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
.atag_offset = 0x100,
.fixup = tegra_paz00_fixup,
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,
.init_early = tegra20_init_early,
.init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,

2
arch/arm/mach-tegra/board-seaboard-pinmux.c
View File

@ -19,7 +19,7 @@
#include <linux/of.h>
#include <mach/pinmux.h>
#include <mach/pinmux-t2.h>
#include <mach/pinmux-tegra20.h>
#include "gpio-names.h"
#include "board-seaboard.h"

6
arch/arm/mach-tegra/board-seaboard.c
View File

@ -283,7 +283,7 @@ static void __init tegra_wario_init(void)
MACHINE_START(SEABOARD, "seaboard")
.atag_offset = 0x100,
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,
.init_early = tegra20_init_early,
.init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,
@ -294,7 +294,7 @@ MACHINE_END
MACHINE_START(KAEN, "kaen")
.atag_offset = 0x100,
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,
.init_early = tegra20_init_early,
.init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,
@ -305,7 +305,7 @@ MACHINE_END
MACHINE_START(WARIO, "wario")
.atag_offset = 0x100,
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,
.init_early = tegra20_init_early,
.init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,

1
arch/arm/mach-tegra/board-trimslice-pinmux.c
View File

@ -19,6 +19,7 @@
#include <linux/of.h>
#include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include "gpio-names.h"
#include "board-trimslice.h"

2
arch/arm/mach-tegra/board-trimslice.c
View File

@ -175,7 +175,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
.atag_offset = 0x100,
.fixup = tegra_trimslice_fixup,
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,
.init_early = tegra20_init_early,
.init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,

5
arch/arm/mach-tegra/board.h
View File

@ -25,10 +25,11 @@
void tegra_assert_system_reset(char mode, const char *cmd);
void __init tegra_init_early(void);
void __init tegra20_init_early(void);
void __init tegra30_init_early(void);
void __init tegra_map_common_io(void);
void __init tegra_init_irq(void);
void __init tegra_init_clock(void);
void __init tegra_dt_init_irq(void);
int __init tegra_pcie_init(bool init_port0, bool init_port1);
extern struct sys_timer tegra_timer;

25
arch/arm/mach-tegra/clock.c
View File

@ -387,35 +387,18 @@ EXPORT_SYMBOL(tegra_clk_init_from_table);
void tegra_periph_reset_deassert(struct clk *c)
{
tegra2_periph_reset_deassert(c);
BUG_ON(!c->ops->reset);
c->ops->reset(c, false);
}
EXPORT_SYMBOL(tegra_periph_reset_deassert);
void tegra_periph_reset_assert(struct clk *c)
{
tegra2_periph_reset_assert(c);
BUG_ON(!c->ops->reset);
c->ops->reset(c, true);
}
EXPORT_SYMBOL(tegra_periph_reset_assert);
void __init tegra_init_clock(void)
{
tegra2_init_clocks();
}
/*
* The SDMMC controllers have extra bits in the clock source register that
* adjust the delay between the clock and data to compenstate for delays
* on the PCB.
*/
void tegra_sdmmc_tap_delay(struct clk *c, int delay)
{
unsigned long flags;
spin_lock_irqsave(&c->spinlock, flags);
tegra2_sdmmc_tap_delay(c, delay);
spin_unlock_irqrestore(&c->spinlock, flags);
}
#ifdef CONFIG_DEBUG_FS
static int __clk_lock_all_spinlocks(void)

4
arch/arm/mach-tegra/clock.h
View File

@ -146,15 +146,11 @@ struct tegra_clk_init_table {
};
void tegra2_init_clocks(void);
void tegra2_periph_reset_deassert(struct clk *c);
void tegra2_periph_reset_assert(struct clk *c);
void clk_init(struct clk *clk);
struct clk *tegra_get_clock_by_name(const char *name);
unsigned long clk_measure_input_freq(void);
int clk_reparent(struct clk *c, struct clk *parent);
void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
unsigned long clk_get_rate_locked(struct clk *c);
int clk_set_rate_locked(struct clk *c, unsigned long rate);
void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
#endif

55
arch/arm/mach-tegra/common.c
View File

@ -1,5 +1,5 @@
/*
* arch/arm/mach-tegra/board-harmony.c
* arch/arm/mach-tegra/common.c
*
* Copyright (C) 2010 Google, Inc.
*
@ -21,8 +21,10 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of_irq.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <mach/iomap.h>
#include <mach/system.h>
@ -31,18 +33,31 @@
#include "clock.h"
#include "fuse.h"
#ifdef CONFIG_OF
static const struct of_device_id tegra_dt_irq_match[] __initconst = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
{ }
};
void __init tegra_dt_init_irq(void)
{
tegra_init_irq();
of_irq_init(tegra_dt_irq_match);
}
#endif
void tegra_assert_system_reset(char mode, const char *cmd)
{
void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
u32 reg;
/* use *_related to avoid spinlock since caches are off */
reg = readl_relaxed(reset);
reg |= 0x04;
reg |= 0x10;
writel_relaxed(reg, reset);
}
static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
/* name parent rate enabled */
{ "clk_m", NULL, 0, true },
{ "pll_p", "clk_m", 216000000, true },
@ -58,24 +73,38 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ "cpu", NULL, 0, true },
{ NULL, NULL, 0, 0},
};
#endif
static void __init tegra_init_cache(void)
static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
{
#ifdef CONFIG_CACHE_L2X0
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
u32 aux_ctrl, cache_type;
writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
l2x0_init(p, 0x6C080001, 0x8200c3fe);
cache_type = readl(p + L2X0_CACHE_TYPE);
aux_ctrl = (cache_type & 0x700) << (17-8);
aux_ctrl |= 0x6C000001;
l2x0_init(p, aux_ctrl, 0x8200c3fe);
#endif
}
void __init tegra_init_early(void)
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
void __init tegra20_init_early(void)
{
tegra_init_fuse();
tegra_init_clock();
tegra_clk_init_from_table(common_clk_init_table);
tegra_init_cache();
tegra2_init_clocks();
tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache(0x331, 0x441);
}
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
void __init tegra30_init_early(void)
{
tegra_init_cache(0x441, 0x551);
}
#endif

2
arch/arm/mach-tegra/include/mach/clk.h
View File

@ -26,6 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c);
void tegra_periph_reset_assert(struct clk *c);
unsigned long clk_get_rate_all_locked(struct clk *c);
void tegra_sdmmc_tap_delay(struct clk *c, int delay);
void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
#endif

2
arch/arm/mach-tegra/include/mach/irqs.h
View File

@ -25,7 +25,6 @@
#define IRQ_LOCALTIMER 29
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
/* Primary Interrupt Controller */
#define INT_PRI_BASE (INT_GIC_BASE + 32)
#define INT_TMR1 (INT_PRI_BASE + 0)
@ -178,6 +177,5 @@
#define NR_BOARD_IRQS 32
#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS)
#endif
#endif

6
arch/arm/mach-tegra/include/mach/pinmux-t2.h → arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h
* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
*
* Copyright (C) 2010 Google, Inc.
*
@ -14,8 +14,8 @@
*
*/
#ifndef __MACH_TEGRA_PINMUX_T2_H
#define __MACH_TEGRA_PINMUX_T2_H
#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
#define __MACH_TEGRA_PINMUX_TEGRA20_H
enum tegra_pingroup {
TEGRA_PINGROUP_ATA = 0,

320
arch/arm/mach-tegra/include/mach/pinmux-tegra30.h Normal file
View File

@ -0,0 +1,320 @@
/*
* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
*
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010,2011 Nvidia, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
#define __MACH_TEGRA_PINMUX_TEGRA30_H
enum tegra_pingroup {
TEGRA_PINGROUP_ULPI_DATA0 = 0,
TEGRA_PINGROUP_ULPI_DATA1,
TEGRA_PINGROUP_ULPI_DATA2,
TEGRA_PINGROUP_ULPI_DATA3,
TEGRA_PINGROUP_ULPI_DATA4,
TEGRA_PINGROUP_ULPI_DATA5,
TEGRA_PINGROUP_ULPI_DATA6,
TEGRA_PINGROUP_ULPI_DATA7,
TEGRA_PINGROUP_ULPI_CLK,
TEGRA_PINGROUP_ULPI_DIR,
TEGRA_PINGROUP_ULPI_NXT,
TEGRA_PINGROUP_ULPI_STP,
TEGRA_PINGROUP_DAP3_FS,
TEGRA_PINGROUP_DAP3_DIN,
TEGRA_PINGROUP_DAP3_DOUT,
TEGRA_PINGROUP_DAP3_SCLK,
TEGRA_PINGROUP_GPIO_PV0,
TEGRA_PINGROUP_GPIO_PV1,
TEGRA_PINGROUP_SDMMC1_CLK,
TEGRA_PINGROUP_SDMMC1_CMD,
TEGRA_PINGROUP_SDMMC1_DAT3,
TEGRA_PINGROUP_SDMMC1_DAT2,
TEGRA_PINGROUP_SDMMC1_DAT1,
TEGRA_PINGROUP_SDMMC1_DAT0,
TEGRA_PINGROUP_GPIO_PV2,
TEGRA_PINGROUP_GPIO_PV3,
TEGRA_PINGROUP_CLK2_OUT,
TEGRA_PINGROUP_CLK2_REQ,
TEGRA_PINGROUP_LCD_PWR1,
TEGRA_PINGROUP_LCD_PWR2,
TEGRA_PINGROUP_LCD_SDIN,
TEGRA_PINGROUP_LCD_SDOUT,
TEGRA_PINGROUP_LCD_WR_N,
TEGRA_PINGROUP_LCD_CS0_N,
TEGRA_PINGROUP_LCD_DC0,
TEGRA_PINGROUP_LCD_SCK,
TEGRA_PINGROUP_LCD_PWR0,
TEGRA_PINGROUP_LCD_PCLK,
TEGRA_PINGROUP_LCD_DE,
TEGRA_PINGROUP_LCD_HSYNC,
TEGRA_PINGROUP_LCD_VSYNC,
TEGRA_PINGROUP_LCD_D0,
TEGRA_PINGROUP_LCD_D1,
TEGRA_PINGROUP_LCD_D2,
TEGRA_PINGROUP_LCD_D3,
TEGRA_PINGROUP_LCD_D4,
TEGRA_PINGROUP_LCD_D5,
TEGRA_PINGROUP_LCD_D6,
TEGRA_PINGROUP_LCD_D7,
TEGRA_PINGROUP_LCD_D8,
TEGRA_PINGROUP_LCD_D9,
TEGRA_PINGROUP_LCD_D10,
TEGRA_PINGROUP_LCD_D11,
TEGRA_PINGROUP_LCD_D12,
TEGRA_PINGROUP_LCD_D13,
TEGRA_PINGROUP_LCD_D14,
TEGRA_PINGROUP_LCD_D15,
TEGRA_PINGROUP_LCD_D16,
TEGRA_PINGROUP_LCD_D17,
TEGRA_PINGROUP_LCD_D18,
TEGRA_PINGROUP_LCD_D19,
TEGRA_PINGROUP_LCD_D20,
TEGRA_PINGROUP_LCD_D21,
TEGRA_PINGROUP_LCD_D22,
TEGRA_PINGROUP_LCD_D23,
TEGRA_PINGROUP_LCD_CS1_N,
TEGRA_PINGROUP_LCD_M1,
TEGRA_PINGROUP_LCD_DC1,
TEGRA_PINGROUP_HDMI_INT,
TEGRA_PINGROUP_DDC_SCL,
TEGRA_PINGROUP_DDC_SDA,
TEGRA_PINGROUP_CRT_HSYNC,
TEGRA_PINGROUP_CRT_VSYNC,
TEGRA_PINGROUP_VI_D0,
TEGRA_PINGROUP_VI_D1,
TEGRA_PINGROUP_VI_D2,
TEGRA_PINGROUP_VI_D3,
TEGRA_PINGROUP_VI_D4,
TEGRA_PINGROUP_VI_D5,
TEGRA_PINGROUP_VI_D6,
TEGRA_PINGROUP_VI_D7,
TEGRA_PINGROUP_VI_D8,
TEGRA_PINGROUP_VI_D9,
TEGRA_PINGROUP_VI_D10,
TEGRA_PINGROUP_VI_D11,
TEGRA_PINGROUP_VI_PCLK,
TEGRA_PINGROUP_VI_MCLK,
TEGRA_PINGROUP_VI_VSYNC,
TEGRA_PINGROUP_VI_HSYNC,
TEGRA_PINGROUP_UART2_RXD,
TEGRA_PINGROUP_UART2_TXD,
TEGRA_PINGROUP_UART2_RTS_N,
TEGRA_PINGROUP_UART2_CTS_N,
TEGRA_PINGROUP_UART3_TXD,
TEGRA_PINGROUP_UART3_RXD,
TEGRA_PINGROUP_UART3_CTS_N,
TEGRA_PINGROUP_UART3_RTS_N,
TEGRA_PINGROUP_GPIO_PU0,
TEGRA_PINGROUP_GPIO_PU1,
TEGRA_PINGROUP_GPIO_PU2,
TEGRA_PINGROUP_GPIO_PU3,
TEGRA_PINGROUP_GPIO_PU4,
TEGRA_PINGROUP_GPIO_PU5,
TEGRA_PINGROUP_GPIO_PU6,
TEGRA_PINGROUP_GEN1_I2C_SDA,
TEGRA_PINGROUP_GEN1_I2C_SCL,
TEGRA_PINGROUP_DAP4_FS,
TEGRA_PINGROUP_DAP4_DIN,
TEGRA_PINGROUP_DAP4_DOUT,
TEGRA_PINGROUP_DAP4_SCLK,
TEGRA_PINGROUP_CLK3_OUT,
TEGRA_PINGROUP_CLK3_REQ,
TEGRA_PINGROUP_GMI_WP_N,
TEGRA_PINGROUP_GMI_IORDY,
TEGRA_PINGROUP_GMI_WAIT,
TEGRA_PINGROUP_GMI_ADV_N,
TEGRA_PINGROUP_GMI_CLK,
TEGRA_PINGROUP_GMI_CS0_N,
TEGRA_PINGROUP_GMI_CS1_N,
TEGRA_PINGROUP_GMI_CS2_N,
TEGRA_PINGROUP_GMI_CS3_N,
TEGRA_PINGROUP_GMI_CS4_N,
TEGRA_PINGROUP_GMI_CS6_N,
TEGRA_PINGROUP_GMI_CS7_N,
TEGRA_PINGROUP_GMI_AD0,
TEGRA_PINGROUP_GMI_AD1,
TEGRA_PINGROUP_GMI_AD2,
TEGRA_PINGROUP_GMI_AD3,
TEGRA_PINGROUP_GMI_AD4,
TEGRA_PINGROUP_GMI_AD5,
TEGRA_PINGROUP_GMI_AD6,
TEGRA_PINGROUP_GMI_AD7,
TEGRA_PINGROUP_GMI_AD8,
TEGRA_PINGROUP_GMI_AD9,
TEGRA_PINGROUP_GMI_AD10,
TEGRA_PINGROUP_GMI_AD11,
TEGRA_PINGROUP_GMI_AD12,
TEGRA_PINGROUP_GMI_AD13,
TEGRA_PINGROUP_GMI_AD14,
TEGRA_PINGROUP_GMI_AD15,
TEGRA_PINGROUP_GMI_A16,
TEGRA_PINGROUP_GMI_A17,
TEGRA_PINGROUP_GMI_A18,
TEGRA_PINGROUP_GMI_A19,
TEGRA_PINGROUP_GMI_WR_N,
TEGRA_PINGROUP_GMI_OE_N,
TEGRA_PINGROUP_GMI_DQS,
TEGRA_PINGROUP_GMI_RST_N,
TEGRA_PINGROUP_GEN2_I2C_SCL,
TEGRA_PINGROUP_GEN2_I2C_SDA,
TEGRA_PINGROUP_SDMMC4_CLK,
TEGRA_PINGROUP_SDMMC4_CMD,
TEGRA_PINGROUP_SDMMC4_DAT0,
TEGRA_PINGROUP_SDMMC4_DAT1,
TEGRA_PINGROUP_SDMMC4_DAT2,
TEGRA_PINGROUP_SDMMC4_DAT3,
TEGRA_PINGROUP_SDMMC4_DAT4,
TEGRA_PINGROUP_SDMMC4_DAT5,
TEGRA_PINGROUP_SDMMC4_DAT6,
TEGRA_PINGROUP_SDMMC4_DAT7,
TEGRA_PINGROUP_SDMMC4_RST_N,
TEGRA_PINGROUP_CAM_MCLK,
TEGRA_PINGROUP_GPIO_PCC1,
TEGRA_PINGROUP_GPIO_PBB0,
TEGRA_PINGROUP_CAM_I2C_SCL,
TEGRA_PINGROUP_CAM_I2C_SDA,
TEGRA_PINGROUP_GPIO_PBB3,
TEGRA_PINGROUP_GPIO_PBB4,
TEGRA_PINGROUP_GPIO_PBB5,
TEGRA_PINGROUP_GPIO_PBB6,
TEGRA_PINGROUP_GPIO_PBB7,
TEGRA_PINGROUP_GPIO_PCC2,
TEGRA_PINGROUP_JTAG_RTCK,
TEGRA_PINGROUP_PWR_I2C_SCL,
TEGRA_PINGROUP_PWR_I2C_SDA,
TEGRA_PINGROUP_KB_ROW0,
TEGRA_PINGROUP_KB_ROW1,
TEGRA_PINGROUP_KB_ROW2,
TEGRA_PINGROUP_KB_ROW3,
TEGRA_PINGROUP_KB_ROW4,
TEGRA_PINGROUP_KB_ROW5,
TEGRA_PINGROUP_KB_ROW6,
TEGRA_PINGROUP_KB_ROW7,
TEGRA_PINGROUP_KB_ROW8,
TEGRA_PINGROUP_KB_ROW9,
TEGRA_PINGROUP_KB_ROW10,
TEGRA_PINGROUP_KB_ROW11,
TEGRA_PINGROUP_KB_ROW12,
TEGRA_PINGROUP_KB_ROW13,
TEGRA_PINGROUP_KB_ROW14,
TEGRA_PINGROUP_KB_ROW15,
TEGRA_PINGROUP_KB_COL0,
TEGRA_PINGROUP_KB_COL1,
TEGRA_PINGROUP_KB_COL2,
TEGRA_PINGROUP_KB_COL3,
TEGRA_PINGROUP_KB_COL4,
TEGRA_PINGROUP_KB_COL5,
TEGRA_PINGROUP_KB_COL6,
TEGRA_PINGROUP_KB_COL7,
TEGRA_PINGROUP_CLK_32K_OUT,
TEGRA_PINGROUP_SYS_CLK_REQ,
TEGRA_PINGROUP_CORE_PWR_REQ,
TEGRA_PINGROUP_CPU_PWR_REQ,
TEGRA_PINGROUP_PWR_INT_N,
TEGRA_PINGROUP_CLK_32K_IN,
TEGRA_PINGROUP_OWR,
TEGRA_PINGROUP_DAP1_FS,
TEGRA_PINGROUP_DAP1_DIN,
TEGRA_PINGROUP_DAP1_DOUT,
TEGRA_PINGROUP_DAP1_SCLK,
TEGRA_PINGROUP_CLK1_REQ,
TEGRA_PINGROUP_CLK1_OUT,
TEGRA_PINGROUP_SPDIF_IN,
TEGRA_PINGROUP_SPDIF_OUT,
TEGRA_PINGROUP_DAP2_FS,
TEGRA_PINGROUP_DAP2_DIN,
TEGRA_PINGROUP_DAP2_DOUT,
TEGRA_PINGROUP_DAP2_SCLK,
TEGRA_PINGROUP_SPI2_MOSI,
TEGRA_PINGROUP_SPI2_MISO,
TEGRA_PINGROUP_SPI2_CS0_N,
TEGRA_PINGROUP_SPI2_SCK,
TEGRA_PINGROUP_SPI1_MOSI,
TEGRA_PINGROUP_SPI1_SCK,
TEGRA_PINGROUP_SPI1_CS0_N,
TEGRA_PINGROUP_SPI1_MISO,
TEGRA_PINGROUP_SPI2_CS1_N,
TEGRA_PINGROUP_SPI2_CS2_N,
TEGRA_PINGROUP_SDMMC3_CLK,
TEGRA_PINGROUP_SDMMC3_CMD,
TEGRA_PINGROUP_SDMMC3_DAT0,
TEGRA_PINGROUP_SDMMC3_DAT1,
TEGRA_PINGROUP_SDMMC3_DAT2,
TEGRA_PINGROUP_SDMMC3_DAT3,
TEGRA_PINGROUP_SDMMC3_DAT4,
TEGRA_PINGROUP_SDMMC3_DAT5,
TEGRA_PINGROUP_SDMMC3_DAT6,
TEGRA_PINGROUP_SDMMC3_DAT7,
TEGRA_PINGROUP_PEX_L0_PRSNT_N,
TEGRA_PINGROUP_PEX_L0_RST_N,
TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
TEGRA_PINGROUP_PEX_WAKE_N,
TEGRA_PINGROUP_PEX_L1_PRSNT_N,
TEGRA_PINGROUP_PEX_L1_RST_N,
TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
TEGRA_PINGROUP_PEX_L2_PRSNT_N,
TEGRA_PINGROUP_PEX_L2_RST_N,
TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
TEGRA_PINGROUP_HDMI_CEC,
TEGRA_MAX_PINGROUP,
};
enum tegra_drive_pingroup {
TEGRA_DRIVE_PINGROUP_AO1 = 0,
TEGRA_DRIVE_PINGROUP_AO2,
TEGRA_DRIVE_PINGROUP_AT1,
TEGRA_DRIVE_PINGROUP_AT2,
TEGRA_DRIVE_PINGROUP_AT3,
TEGRA_DRIVE_PINGROUP_AT4,
TEGRA_DRIVE_PINGROUP_AT5,
TEGRA_DRIVE_PINGROUP_CDEV1,
TEGRA_DRIVE_PINGROUP_CDEV2,
TEGRA_DRIVE_PINGROUP_CSUS,
TEGRA_DRIVE_PINGROUP_DAP1,
TEGRA_DRIVE_PINGROUP_DAP2,
TEGRA_DRIVE_PINGROUP_DAP3,
TEGRA_DRIVE_PINGROUP_DAP4,
TEGRA_DRIVE_PINGROUP_DBG,
TEGRA_DRIVE_PINGROUP_LCD1,
TEGRA_DRIVE_PINGROUP_LCD2,
TEGRA_DRIVE_PINGROUP_SDIO2,
TEGRA_DRIVE_PINGROUP_SDIO3,
TEGRA_DRIVE_PINGROUP_SPI,
TEGRA_DRIVE_PINGROUP_UAA,
TEGRA_DRIVE_PINGROUP_UAB,
TEGRA_DRIVE_PINGROUP_UART2,
TEGRA_DRIVE_PINGROUP_UART3,
TEGRA_DRIVE_PINGROUP_VI1,
TEGRA_DRIVE_PINGROUP_SDIO1,
TEGRA_DRIVE_PINGROUP_CRT,
TEGRA_DRIVE_PINGROUP_DDC,
TEGRA_DRIVE_PINGROUP_GMA,
TEGRA_DRIVE_PINGROUP_GMB,
TEGRA_DRIVE_PINGROUP_GMC,
TEGRA_DRIVE_PINGROUP_GMD,
TEGRA_DRIVE_PINGROUP_GME,
TEGRA_DRIVE_PINGROUP_GMF,
TEGRA_DRIVE_PINGROUP_GMG,
TEGRA_DRIVE_PINGROUP_GMH,
TEGRA_DRIVE_PINGROUP_OWR,
TEGRA_DRIVE_PINGROUP_UAD,
TEGRA_DRIVE_PINGROUP_GPV,
TEGRA_DRIVE_PINGROUP_DEV3,
TEGRA_DRIVE_PINGROUP_CEC,
TEGRA_MAX_DRIVE_PINGROUP,
};
#endif

88
arch/arm/mach-tegra/include/mach/pinmux.h
View File

@ -2,6 +2,7 @@
* linux/arch/arm/mach-tegra/include/mach/pinmux.h
*
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010,2011 Nvidia, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@ -17,18 +18,13 @@
#ifndef __MACH_TEGRA_PINMUX_H
#define __MACH_TEGRA_PINMUX_H
#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
#include "pinmux-t2.h"
#else
#error "Undefined Tegra architecture"
#endif
enum tegra_mux_func {
TEGRA_MUX_RSVD = 0x8000,
TEGRA_MUX_RSVD1 = 0x8000,
TEGRA_MUX_RSVD2 = 0x8001,
TEGRA_MUX_RSVD3 = 0x8002,
TEGRA_MUX_RSVD4 = 0x8003,
TEGRA_MUX_INVALID = 0x4000,
TEGRA_MUX_NONE = -1,
TEGRA_MUX_AHB_CLK,
TEGRA_MUX_APB_CLK,
@ -90,6 +86,49 @@ enum tegra_mux_func {
TEGRA_MUX_VI,
TEGRA_MUX_VI_SENSOR_CLK,
TEGRA_MUX_XIO,
TEGRA_MUX_BLINK,
TEGRA_MUX_CEC,
TEGRA_MUX_CLK12,
TEGRA_MUX_DAP,
TEGRA_MUX_DAPSDMMC2,
TEGRA_MUX_DDR,
TEGRA_MUX_DEV3,
TEGRA_MUX_DTV,
TEGRA_MUX_VI_ALT1,
TEGRA_MUX_VI_ALT2,
TEGRA_MUX_VI_ALT3,
TEGRA_MUX_EMC_DLL,
TEGRA_MUX_EXTPERIPH1,
TEGRA_MUX_EXTPERIPH2,
TEGRA_MUX_EXTPERIPH3,
TEGRA_MUX_GMI_ALT,
TEGRA_MUX_HDA,
TEGRA_MUX_HSI,
TEGRA_MUX_I2C4,
TEGRA_MUX_I2C5,
TEGRA_MUX_I2CPWR,
TEGRA_MUX_I2S0,
TEGRA_MUX_I2S1,
TEGRA_MUX_I2S2,
TEGRA_MUX_I2S3,
TEGRA_MUX_I2S4,
TEGRA_MUX_NAND_ALT,
TEGRA_MUX_POPSDIO4,
TEGRA_MUX_POPSDMMC4,
TEGRA_MUX_PWM0,
TEGRA_MUX_PWM1,
TEGRA_MUX_PWM2,
TEGRA_MUX_PWM3,
TEGRA_MUX_SATA,
TEGRA_MUX_SPI5,
TEGRA_MUX_SPI6,
TEGRA_MUX_SYSCLK,
TEGRA_MUX_VGP1,
TEGRA_MUX_VGP2,
TEGRA_MUX_VGP3,
TEGRA_MUX_VGP4,
TEGRA_MUX_VGP5,
TEGRA_MUX_VGP6,
TEGRA_MUX_SAFE,
TEGRA_MAX_MUX,
};
@ -105,6 +144,11 @@ enum tegra_tristate {
TEGRA_TRI_TRISTATE = 1,
};
enum tegra_pin_io {
TEGRA_PIN_OUTPUT = 0,
TEGRA_PIN_INPUT = 1,
};
enum tegra_vddio {
TEGRA_VDDIO_BB = 0,
TEGRA_VDDIO_LCD,
@ -115,10 +159,16 @@ enum tegra_vddio {
TEGRA_VDDIO_SYS,
TEGRA_VDDIO_AUDIO,
TEGRA_VDDIO_SD,
TEGRA_VDDIO_CAM,
TEGRA_VDDIO_GMI,
TEGRA_VDDIO_PEXCTL,
TEGRA_VDDIO_SDMMC1,
TEGRA_VDDIO_SDMMC3,
TEGRA_VDDIO_SDMMC4,
};
struct tegra_pingroup_config {
enum tegra_pingroup pingroup;
int pingroup;
enum tegra_mux_func func;
enum tegra_pullupdown pupd;
enum tegra_tristate tristate;
@ -187,7 +237,7 @@ enum tegra_schmitt {
};
struct tegra_drive_pingroup_config {
enum tegra_drive_pingroup pingroup;
int pingroup;
enum tegra_hsm hsm;
enum tegra_schmitt schmitt;
enum tegra_drive drive;
@ -208,6 +258,7 @@ struct tegra_pingroup_desc {
int funcs[4];
int func_safe;
int vddio;
enum tegra_pin_io io_default;
s16 tri_bank; /* Register bank the tri_reg exists within */
s16 mux_bank; /* Register bank the mux_reg exists within */
s16 pupd_bank; /* Register bank the pupd_reg exists within */
@ -217,15 +268,23 @@ struct tegra_pingroup_desc {
s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
s8 lock_bit; /* offset of the LOCK bit into mux register bit */
s8 od_bit; /* offset of the OD bit into mux register bit */
s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
};
extern const struct tegra_pingroup_desc tegra_soc_pingroups[];
extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[];
typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
int *pgdrive_max);
int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
enum tegra_tristate tristate);
int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
enum tegra_pullupdown pupd);
void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
int len);
@ -241,4 +300,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
int len, enum tegra_pullupdown pupd);
#endif

24
arch/arm/mach-tegra/pinmux-t2-tables.c → arch/arm/mach-tegra/pinmux-tegra20-tables.c
View File

@ -1,7 +1,7 @@
/*
* linux/arch/arm/mach-tegra/pinmux-t2-tables.c
* linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
*
* Common pinmux configurations for Tegra 2 SoCs
* Common pinmux configurations for Tegra20 SoCs
*
* Copyright (C) 2010 NVIDIA Corporation
*
@ -29,6 +29,7 @@
#include <mach/iomap.h>
#include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include <mach/suspend.h>
#define TRISTATE_REG_A 0x14
@ -43,7 +44,7 @@
.reg = ((r) - PINGROUP_REG_A) \
}
const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
DRIVE_PINGROUP(AO1, 0x868),
DRIVE_PINGROUP(AO2, 0x86c),
DRIVE_PINGROUP(AT1, 0x870),
@ -105,9 +106,13 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
.pupd_bank = 2, \
.pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
.pupd_bit = pupd_b, \
.lock_bit = -1, \
.od_bit = -1, \
.ioreset_bit = -1, \
.io_default = -1, \
}
const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
@ -226,3 +231,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
};
void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
int *pgdrive_max)
{
*pg = tegra_soc_pingroups;
*pg_max = TEGRA_MAX_PINGROUP;
*pgdrive = tegra_soc_drive_pingroups;
*pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
}

376
arch/arm/mach-tegra/pinmux-tegra30-tables.c Normal file
View File

@ -0,0 +1,376 @@
/*
* linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
*
* Common pinmux configurations for Tegra30 SoCs
*
* Copyright (C) 2010,2011 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/string.h>
#include <mach/iomap.h>
#include <mach/pinmux.h>
#include <mach/pinmux-tegra30.h>
#include <mach/suspend.h>
#define PINGROUP_REG_A 0x868
#define MUXCTL_REG_A 0x3000
#define DRIVE_PINGROUP(pg_name, r) \
[TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
.name = #pg_name, \
.reg_bank = 0, \
.reg = ((r) - PINGROUP_REG_A) \
}
static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
DRIVE_PINGROUP(AO1, 0x868),
DRIVE_PINGROUP(AO2, 0x86c),
DRIVE_PINGROUP(AT1, 0x870),
DRIVE_PINGROUP(AT2, 0x874),
DRIVE_PINGROUP(AT3, 0x878),
DRIVE_PINGROUP(AT4, 0x87c),
DRIVE_PINGROUP(AT5, 0x880),
DRIVE_PINGROUP(CDEV1, 0x884),
DRIVE_PINGROUP(CDEV2, 0x888),
DRIVE_PINGROUP(CSUS, 0x88c),
DRIVE_PINGROUP(DAP1, 0x890),
DRIVE_PINGROUP(DAP2, 0x894),
DRIVE_PINGROUP(DAP3, 0x898),
DRIVE_PINGROUP(DAP4, 0x89c),
DRIVE_PINGROUP(DBG, 0x8a0),
DRIVE_PINGROUP(LCD1, 0x8a4),
DRIVE_PINGROUP(LCD2, 0x8a8),
DRIVE_PINGROUP(SDIO2, 0x8ac),
DRIVE_PINGROUP(SDIO3, 0x8b0),
DRIVE_PINGROUP(SPI, 0x8b4),
DRIVE_PINGROUP(UAA, 0x8b8),
DRIVE_PINGROUP(UAB, 0x8bc),
DRIVE_PINGROUP(UART2, 0x8c0),
DRIVE_PINGROUP(UART3, 0x8c4),
DRIVE_PINGROUP(VI1, 0x8c8),
DRIVE_PINGROUP(SDIO1, 0x8ec),
DRIVE_PINGROUP(CRT, 0x8f8),
DRIVE_PINGROUP(DDC, 0x8fc),
DRIVE_PINGROUP(GMA, 0x900),
DRIVE_PINGROUP(GMB, 0x904),
DRIVE_PINGROUP(GMC, 0x908),
DRIVE_PINGROUP(GMD, 0x90c),
DRIVE_PINGROUP(GME, 0x910),
DRIVE_PINGROUP(GMF, 0x914),
DRIVE_PINGROUP(GMG, 0x918),
DRIVE_PINGROUP(GMH, 0x91c),
DRIVE_PINGROUP(OWR, 0x920),
DRIVE_PINGROUP(UAD, 0x924),
DRIVE_PINGROUP(GPV, 0x928),
DRIVE_PINGROUP(DEV3, 0x92c),
DRIVE_PINGROUP(CEC, 0x938),
};
#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \
[TEGRA_PINGROUP_ ## pg_name] = { \
.name = #pg_name, \
.vddio = TEGRA_VDDIO_ ## vdd, \
.funcs = { \
TEGRA_MUX_ ## f0, \
TEGRA_MUX_ ## f1, \
TEGRA_MUX_ ## f2, \
TEGRA_MUX_ ## f3, \
}, \
.func_safe = TEGRA_MUX_ ## fs, \
.tri_bank = 1, \
.tri_reg = ((reg) - MUXCTL_REG_A), \
.tri_bit = 4, \
.mux_bank = 1, \
.mux_reg = ((reg) - MUXCTL_REG_A), \
.mux_bit = 0, \
.pupd_bank = 1, \
.pupd_reg = ((reg) - MUXCTL_REG_A), \
.pupd_bit = 2, \
.io_default = TEGRA_PIN_ ## iod, \
.od_bit = 6, \
.lock_bit = 7, \
.ioreset_bit = 8, \
}
static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
/* NAME VDD f0 f1 f2 f3 fSafe io reg */
PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000),
PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004),
PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008),
PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c),
PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010),
PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014),
PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018),
PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c),
PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020),
PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024),
PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028),
PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c),
PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030),
PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034),
PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038),
PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c),
PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040),
PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044),
PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048),
PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c),
PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050),
PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054),
PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058),
PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c),
PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060),
PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064),
PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068),
PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c),
PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070),
PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074),
PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078),
PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c),
PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080),
PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084),
PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088),
PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c),
PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090),
PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094),
PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098),
PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c),
PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0),
PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4),
PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8),
PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac),
PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0),
PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4),
PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8),
PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc),
PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0),
PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4),
PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8),
PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc),
PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0),
PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4),
PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8),
PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc),
PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0),
PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4),
PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8),
PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec),
PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0),
PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4),
PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8),
PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc),
PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100),
PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104),
PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108),
PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c),
PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110),
PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114),
PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118),
PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c),
PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120),
PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124),
PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128),
PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c),
PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130),
PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134),
PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138),
PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c),
PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140),
PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144),
PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148),
PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c),
PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150),
PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154),
PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158),
PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c),
PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160),
PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164),
PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168),
PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c),
PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170),
PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174),
PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178),
PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c),
PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180),
PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184),
PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188),
PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c),
PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190),
PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194),
PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198),
PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c),
PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0),
PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4),
PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8),
PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac),
PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0),
PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4),
PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8),
PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc),
PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0),
PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4),
PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8),
PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc),
PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0),
PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4),
PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8),
PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc),
PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0),
PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4),
PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8),
PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec),
PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0),
PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4),
PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8),
PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc),
PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200),
PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204),
PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208),
PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c),
PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210),
PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214),
PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218),
PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c),
PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220),
PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224),
PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228),
PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c),
PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230),
PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234),
PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238),
PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c),
PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240),
PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244),
PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248),
PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c),
PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250),
PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254),
PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258),
PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c),
PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260),
PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264),
PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268),
PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c),
PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270),
PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274),
PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278),
PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c),
PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280),
PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284),
PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288),
PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c),
PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290),
PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294),
PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298),
PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c),
PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),
PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),
PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),
PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac),
PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0),
PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4),
PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8),
PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc),
PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0),
PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4),
PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8),
PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc),
PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0),
PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4),
PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8),
PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc),
PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0),
PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4),
PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8),
PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec),
PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0),
PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4),
PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8),
PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc),
PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300),
PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304),
PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308),
PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c),
PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310),
PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314),
PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318),
PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c),
PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320),
PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324),
PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328),
PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c),
PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330),
PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334),
PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338),
PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c),
PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340),
PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344),
PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348),
PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c),
PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350),
PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354),
PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358),
PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c),
PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360),
PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364),
PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368),
PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c),
PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370),
PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374),
PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378),
PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c),
PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380),
PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384),
PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388),
PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c),
PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390),
PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394),
PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398),
PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c),
PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0),
PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4),
PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8),
PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac),
PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0),
PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4),
PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8),
PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc),
PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0),
PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4),
PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8),
PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc),
PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0),
PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4),
PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8),
PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc),
PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0),
};
void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
int *pgdrive_max)
{
*pg = tegra_soc_pingroups;
*pg_max = TEGRA_MAX_PINGROUP;
*pgdrive = tegra_soc_drive_pingroups;
*pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
}

153
arch/arm/mach-tegra/pinmux.c
View File

@ -21,6 +21,7 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <mach/iomap.h>
#include <mach/pinmux.h>
@ -33,8 +34,10 @@
#define SLWR(reg) (((reg) >> 28) & 0x3)
#define SLWF(reg) (((reg) >> 30) & 0x3)
static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
static const struct tegra_pingroup_desc *pingroups;
static const struct tegra_drive_pingroup_desc *drive_pingroups;
static int pingroup_max;
static int drive_max;
static char *tegra_mux_names[TEGRA_MAX_MUX] = {
[TEGRA_MUX_AHB_CLK] = "AHB_CLK",
@ -97,6 +100,49 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = {
[TEGRA_MUX_VI] = "VI",
[TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
[TEGRA_MUX_XIO] = "XIO",
[TEGRA_MUX_BLINK] = "BLINK",
[TEGRA_MUX_CEC] = "CEC",
[TEGRA_MUX_CLK12] = "CLK12",
[TEGRA_MUX_DAP] = "DAP",
[TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
[TEGRA_MUX_DDR] = "DDR",
[TEGRA_MUX_DEV3] = "DEV3",
[TEGRA_MUX_DTV] = "DTV",
[TEGRA_MUX_VI_ALT1] = "VI_ALT1",
[TEGRA_MUX_VI_ALT2] = "VI_ALT2",
[TEGRA_MUX_VI_ALT3] = "VI_ALT3",
[TEGRA_MUX_EMC_DLL] = "EMC_DLL",
[TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
[TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
[TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
[TEGRA_MUX_GMI_ALT] = "GMI_ALT",
[TEGRA_MUX_HDA] = "HDA",
[TEGRA_MUX_HSI] = "HSI",
[TEGRA_MUX_I2C4] = "I2C4",
[TEGRA_MUX_I2C5] = "I2C5",
[TEGRA_MUX_I2CPWR] = "I2CPWR",
[TEGRA_MUX_I2S0] = "I2S0",
[TEGRA_MUX_I2S1] = "I2S1",
[TEGRA_MUX_I2S2] = "I2S2",
[TEGRA_MUX_I2S3] = "I2S3",
[TEGRA_MUX_I2S4] = "I2S4",
[TEGRA_MUX_NAND_ALT] = "NAND_ALT",
[TEGRA_MUX_POPSDIO4] = "POPSDIO4",
[TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
[TEGRA_MUX_PWM0] = "PWM0",
[TEGRA_MUX_PWM1] = "PWM2",
[TEGRA_MUX_PWM2] = "PWM2",
[TEGRA_MUX_PWM3] = "PWM3",
[TEGRA_MUX_SATA] = "SATA",
[TEGRA_MUX_SPI5] = "SPI5",
[TEGRA_MUX_SPI6] = "SPI6",
[TEGRA_MUX_SYSCLK] = "SYSCLK",
[TEGRA_MUX_VGP1] = "VGP1",
[TEGRA_MUX_VGP2] = "VGP2",
[TEGRA_MUX_VGP3] = "VGP3",
[TEGRA_MUX_VGP4] = "VGP4",
[TEGRA_MUX_VGP5] = "VGP5",
[TEGRA_MUX_VGP6] = "VGP6",
[TEGRA_MUX_SAFE] = "<safe>",
};
@ -116,9 +162,9 @@ static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
static DEFINE_SPINLOCK(mux_lock);
static const char *pingroup_name(enum tegra_pingroup pg)
static const char *pingroup_name(int pg)
{
if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
if (pg < 0 || pg >= pingroup_max)
return "<UNKNOWN>";
return pingroups[pg].name;
@ -189,10 +235,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
int i;
unsigned long reg;
unsigned long flags;
enum tegra_pingroup pg = config->pingroup;
int pg = config->pingroup;
enum tegra_mux_func func = config->func;
if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
if (pg < 0 || pg >= pingroup_max)
return -ERANGE;
if (pingroups[pg].mux_reg < 0)
@ -230,13 +276,12 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
return 0;
}
int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
enum tegra_tristate tristate)
int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
{
unsigned long reg;
unsigned long flags;
if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
if (pg < 0 || pg >= pingroup_max)
return -ERANGE;
if (pingroups[pg].tri_reg < 0)
@ -255,13 +300,12 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
return 0;
}
int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
enum tegra_pullupdown pupd)
int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
{
unsigned long reg;
unsigned long flags;
if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
if (pg < 0 || pg >= pingroup_max)
return -ERANGE;
if (pingroups[pg].pupd_reg < 0)
@ -287,7 +331,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
{
enum tegra_pingroup pingroup = config->pingroup;
int pingroup = config->pingroup;
enum tegra_mux_func func = config->func;
enum tegra_pullupdown pupd = config->pupd;
enum tegra_tristate tristate = config->tristate;
@ -323,9 +367,9 @@ void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int l
tegra_pinmux_config_pingroup(&config[i]);
}
static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
static const char *drive_pinmux_name(int pg)
{
if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
if (pg < 0 || pg >= drive_max)
return "<UNKNOWN>";
return drive_pingroups[pg].name;
@ -352,12 +396,11 @@ static const char *slew_name(unsigned long val)
return tegra_slew_names[val];
}
static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
enum tegra_hsm hsm)
static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
{
unsigned long flags;
u32 reg;
if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
if (pg < 0 || pg >= drive_max)
return -ERANGE;
if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
@ -377,12 +420,11 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
return 0;
}
static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
enum tegra_schmitt schmitt)
static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
{
unsigned long flags;
u32 reg;
if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
if (pg < 0 || pg >= drive_max)
return -ERANGE;
if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
@ -402,12 +444,11 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
return 0;
}
static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
enum tegra_drive drive)
static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
{
unsigned long flags;
u32 reg;
if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
if (pg < 0 || pg >= drive_max)
return -ERANGE;
if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
@ -425,12 +466,12 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
return 0;
}
static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
static int tegra_drive_pinmux_set_pull_down(int pg,
enum tegra_pull_strength pull_down)
{
unsigned long flags;
u32 reg;
if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
if (pg < 0 || pg >= drive_max)
return -ERANGE;
if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
@ -448,12 +489,12 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
return 0;
}
static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
static int tegra_drive_pinmux_set_pull_up(int pg,
enum tegra_pull_strength pull_up)
{
unsigned long flags;
u32 reg;
if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
if (pg < 0 || pg >= drive_max)
return -ERANGE;
if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
@ -471,12 +512,12 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
return 0;
}
static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
static int tegra_drive_pinmux_set_slew_rising(int pg,
enum tegra_slew slew_rising)
{
unsigned long flags;
u32 reg;
if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
if (pg < 0 || pg >= drive_max)
return -ERANGE;
if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
@ -494,12 +535,12 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
return 0;
}
static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
static int tegra_drive_pinmux_set_slew_falling(int pg,
enum tegra_slew slew_falling)
{
unsigned long flags;
u32 reg;
if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP)
if (pg < 0 || pg >= drive_max)
return -ERANGE;
if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
@ -517,7 +558,7 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
return 0;
}
static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
static void tegra_drive_pinmux_config_pingroup(int pingroup,
enum tegra_hsm hsm,
enum tegra_schmitt schmitt,
enum tegra_drive drive,
@ -596,7 +637,7 @@ void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *conf
for (i = 0; i < len; i++) {
int err;
c = config[i];
if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
WARN_ON(1);
continue;
}
@ -617,7 +658,7 @@ void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config
for (i = 0; i < len; i++) {
int err;
if (config[i].pingroup < 0 ||
config[i].pingroup >= TEGRA_MAX_PINGROUP) {
config[i].pingroup >= pingroup_max) {
WARN_ON(1);
continue;
}
@ -635,7 +676,7 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
{
int i;
int err;
enum tegra_pingroup pingroup;
int pingroup;
for (i = 0; i < len; i++) {
pingroup = config[i].pingroup;
@ -654,7 +695,7 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
{
int i;
int err;
enum tegra_pingroup pingroup;
int pingroup;
for (i = 0; i < len; i++) {
pingroup = config[i].pingroup;
@ -668,11 +709,36 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
}
}
static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
{ .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
{ .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
#endif
{ },
};
static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
{
struct resource *res;
int i;
int config_bad = 0;
const struct of_device_id *match;
match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
if (match)
((pinmux_init)(match->data))(&pingroups, &pingroup_max,
&drive_pingroups, &drive_max);
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
else
/* no device tree available, so we must be on tegra20 */
tegra20_pinmux_init(&pingroups, &pingroup_max,
&drive_pingroups, &drive_max);
#else
pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
#endif
for (i = 0; ; i++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
@ -681,7 +747,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
}
nbanks = i;
for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
for (i = 0; i < pingroup_max; i++) {
if (pingroups[i].tri_bank >= nbanks) {
dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
config_bad = 1;
@ -698,7 +764,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
}
}
for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
for (i = 0; i < drive_max; i++) {
if (drive_pingroups[i].reg_bank >= nbanks) {
dev_err(&pdev->dev,
"drive pingroup %d: bad reg_bank\n", i);
@ -741,11 +807,6 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
return 0;
}
static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
{ .compatible = "nvidia,tegra20-pinmux", },
{ },
};
static struct platform_driver tegra_pinmux_driver = {
.driver = {
.name = "tegra-pinmux",
@ -779,7 +840,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
int i;
int len;
for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
for (i = 0; i < pingroup_max; i++) {
unsigned long reg;
unsigned long tri;
unsigned long mux;
@ -850,7 +911,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
int i;
int len;
for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
for (i = 0; i < drive_max; i++) {
u32 reg;
seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",

19
arch/arm/mach-tegra/tegra2_clocks.c
View File

@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32];
#define pmc_readl(reg) \
__raw_readl(reg_pmc_base + (reg))
unsigned long clk_measure_input_freq(void)
static unsigned long clk_measure_input_freq(void)
{
u32 clock_autodetect;
clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = {
.disable = tegra2_clk_m_disable,
};
void tegra2_periph_reset_assert(struct clk *c)
{
BUG_ON(!c->ops->reset);
c->ops->reset(c, true);
}
void tegra2_periph_reset_deassert(struct clk *c)
{
BUG_ON(!c->ops->reset);
c->ops->reset(c, false);
}
/* super clock functions */
/* "super clocks" on tegra have two-stage muxes and a clock skipping
* super divider. We will ignore the clock skipping divider, since we
@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = {
void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
{
u32 reg;
unsigned long flags;
spin_lock_irqsave(&c->spinlock, flags);
delay = clamp(delay, 0, 15);
reg = clk_readl(c->reg);
@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
reg |= SDMMC_CLK_INT_FB_SEL;
reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
clk_writel(reg, c->reg);
spin_unlock_irqrestore(&c->spinlock, flags);
}
/* External memory controller clock ops */

18
arch/arm/mach-tegra/timer.c
View File

@ -165,20 +165,28 @@ static struct irqaction tegra_timer_irq = {
static void __init tegra_init_timer(void)
{
struct clk *clk;
unsigned long rate = clk_measure_input_freq();
unsigned long rate;
int ret;
clk = clk_get_sys("timer", NULL);
BUG_ON(IS_ERR(clk));
clk_enable(clk);
if (IS_ERR(clk)) {
pr_warn("Unable to get timer clock."
" Assuming 12Mhz input clock.\n");
rate = 12000000;
} else {
clk_enable(clk);
rate = clk_get_rate(clk);
}
/*
* rtc registers are used by read_persistent_clock, keep the rtc clock
* enabled
*/
clk = clk_get_sys("rtc-tegra", NULL);
BUG_ON(IS_ERR(clk));
clk_enable(clk);
if (IS_ERR(clk))
pr_warn("Unable to get rtc-tegra clock\n");
else
clk_enable(clk);
#ifdef CONFIG_HAVE_ARM_TWD
twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);

1
arch/arm/plat-omap/Makefile
View File

@ -19,7 +19,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o

25
arch/arm/plat-omap/include/plat/am33xx.h Normal file
View File

@ -0,0 +1,25 @@
/*
* This file contains the address info for various AM33XX modules.
*
* Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_AM33XX_H
#define __ASM_ARCH_AM33XX_H
#define L4_SLOW_AM33XX_BASE 0x48000000
#define AM33XX_SCM_BASE 0x44E10000
#define AM33XX_CTRL_BASE AM33XX_SCM_BASE
#define AM33XX_PRCM_BASE 0x44E00000
#endif /* __ASM_ARCH_AM33XX_H */

4
arch/arm/plat-omap/include/plat/clock.h
View File

@ -59,6 +59,8 @@ struct clkops {
#define RATE_IN_4430 (1 << 5)
#define RATE_IN_TI816X (1 << 6)
#define RATE_IN_4460 (1 << 7)
#define RATE_IN_AM33XX (1 << 8)
#define RATE_IN_TI814X (1 << 9)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@ -84,7 +86,7 @@ struct clkops {
struct clksel_rate {
u32 val;
u8 div;
u8 flags;
u16 flags;
};
/**

56
arch/arm/plat-omap/include/plat/cpu.h
View File

@ -69,6 +69,7 @@ unsigned int omap_rev(void);
* cpu_is_omap343x(): True for OMAP3430
* cpu_is_omap443x(): True for OMAP4430
* cpu_is_omap446x(): True for OMAP4460
* cpu_is_omap447x(): True for OMAP4470
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
@ -78,6 +79,22 @@ static inline int is_omap ##class (void) \
return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
}
#define GET_AM_CLASS ((omap_rev() >> 24) & 0xff)
#define IS_AM_CLASS(class, id) \
static inline int is_am ##class (void) \
{ \
return (GET_AM_CLASS == (id)) ? 1 : 0; \
}
#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff)
#define IS_TI_CLASS(class, id) \
static inline int is_ti ##class (void) \
{ \
return (GET_TI_CLASS == (id)) ? 1 : 0; \
}
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
#define IS_OMAP_SUBCLASS(subclass, id) \
@ -92,12 +109,21 @@ static inline int is_ti ##subclass (void) \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
#define IS_AM_SUBCLASS(subclass, id) \
static inline int is_am ##subclass (void) \
{ \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
IS_OMAP_CLASS(7xx, 0x07)
IS_OMAP_CLASS(15xx, 0x15)
IS_OMAP_CLASS(16xx, 0x16)
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
IS_AM_CLASS(33xx, 0x33)
IS_TI_CLASS(81xx, 0x81)
IS_OMAP_SUBCLASS(242x, 0x242)
IS_OMAP_SUBCLASS(243x, 0x243)
@ -105,8 +131,11 @@ IS_OMAP_SUBCLASS(343x, 0x343)
IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
IS_OMAP_SUBCLASS(446x, 0x446)
IS_OMAP_SUBCLASS(447x, 0x447)
IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
#define cpu_is_omap7xx() 0
#define cpu_is_omap15xx() 0
@ -116,10 +145,15 @@ IS_TI_SUBCLASS(816x, 0x816)
#define cpu_is_omap243x() 0
#define cpu_is_omap34xx() 0
#define cpu_is_omap343x() 0
#define cpu_is_ti81xx() 0
#define cpu_is_ti816x() 0
#define cpu_is_ti814x() 0
#define cpu_is_am33xx() 0
#define cpu_is_am335x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
#define cpu_is_omap446x() 0
#define cpu_is_omap447x() 0
#if defined(MULTI_OMAP1)
# if defined(CONFIG_ARCH_OMAP730)
@ -322,7 +356,11 @@ IS_OMAP_TYPE(3517, 0x3517)
# undef cpu_is_omap3530
# undef cpu_is_omap3505
# undef cpu_is_omap3517
# undef cpu_is_ti81xx
# undef cpu_is_ti816x
# undef cpu_is_ti814x
# undef cpu_is_am33xx
# undef cpu_is_am335x
# define cpu_is_omap3430() is_omap3430()
# define cpu_is_omap3503() (cpu_is_omap3430() && \
(!omap3_has_iva()) && \
@ -339,16 +377,22 @@ IS_OMAP_TYPE(3517, 0x3517)
!omap3_has_sgx())
# undef cpu_is_omap3630
# define cpu_is_omap3630() is_omap363x()
# define cpu_is_ti81xx() is_ti81xx()
# define cpu_is_ti816x() is_ti816x()
# define cpu_is_ti814x() is_ti814x()
# define cpu_is_am33xx() is_am33xx()
# define cpu_is_am335x() is_am335x()
#endif
# if defined(CONFIG_ARCH_OMAP4)
# undef cpu_is_omap44xx
# undef cpu_is_omap443x
# undef cpu_is_omap446x
# undef cpu_is_omap447x
# define cpu_is_omap44xx() is_omap44xx()
# define cpu_is_omap443x() is_omap443x()
# define cpu_is_omap446x() is_omap446x()
# define cpu_is_omap447x() is_omap447x()
# endif
/* Macros to detect if we have OMAP1 or OMAP2 */
@ -386,15 +430,27 @@ IS_OMAP_TYPE(3517, 0x3517)
#define TI8168_REV_ES1_0 TI816X_CLASS
#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
#define TI814X_CLASS 0x81400034
#define TI8148_REV_ES1_0 TI814X_CLASS
#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
#define AM335X_CLASS 0x33500034
#define AM335X_REV_ES1_0 AM335X_CLASS
#define OMAP443X_CLASS 0x44300044
#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
#define OMAP4430_REV_ES2_3 (OMAP443X_CLASS | (0x23 << 8))
#define OMAP446X_CLASS 0x44600044
#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
#define OMAP447X_CLASS 0x44700044
#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
void omap2_check_revision(void);
/*

3
arch/arm/plat-omap/include/plat/hardware.h
View File

@ -286,6 +286,7 @@
#include <plat/omap24xx.h>
#include <plat/omap34xx.h>
#include <plat/omap44xx.h>
#include <plat/ti816x.h>
#include <plat/ti81xx.h>
#include <plat/am33xx.h>
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */

12
arch/arm/plat-omap/include/plat/io.h
View File

@ -73,6 +73,9 @@
#define OMAP4_L3_IO_OFFSET 0xb4000000
#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
#define AM33XX_L4_WK_IO_OFFSET 0xb5000000
#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
@ -153,6 +156,15 @@
#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
/*
* ----------------------------------------------------------------------------
* AM33XX specific IO mapping
* ----------------------------------------------------------------------------
*/
#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE
#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
/*
* Need to look at the Size 4M for L4.
* VPOM3430 was not working for Int controller

2
arch/arm/plat-omap/include/plat/omap34xx.h
View File

@ -35,6 +35,8 @@
#define L4_EMU_34XX_BASE 0x54000000
#define L3_34XX_BASE 0x68000000
#define L4_WK_AM33XX_BASE 0x44C00000
#define OMAP3430_32KSYNCT_BASE 0x48320000
#define OMAP3430_CM_BASE 0x48004800
#define OMAP3430_PRM_BASE 0x48306800

14
arch/arm/plat-omap/include/plat/serial.h
View File

@ -51,10 +51,10 @@
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
/* TI816X serial ports */
#define TI816X_UART1_BASE 0x48020000
#define TI816X_UART2_BASE 0x48022000
#define TI816X_UART3_BASE 0x48024000
/* TI81XX serial ports */
#define TI81XX_UART1_BASE 0x48020000
#define TI81XX_UART2_BASE 0x48022000
#define TI81XX_UART3_BASE 0x48024000
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
@ -89,9 +89,9 @@
#define OMAP4UART2 OMAP2UART2
#define OMAP4UART3 43
#define OMAP4UART4 44
#define TI816XUART1 81
#define TI816XUART2 82
#define TI816XUART3 83
#define TI81XXUART1 81
#define TI81XXUART2 82
#define TI81XXUART3 83
#define ZOOM_UART 95 /* Only on zoom2/3 */
/* This is only used by 8250.c for omap1510 */

18
arch/arm/plat-omap/include/plat/ti816x.h → arch/arm/plat-omap/include/plat/ti81xx.h
View File

@ -1,5 +1,5 @@
/*
* This file contains the address data for various TI816X modules.
* This file contains the address data for various TI81XX modules.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
*
@ -13,15 +13,15 @@
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_TI816X_H
#define __ASM_ARCH_TI816X_H
#ifndef __ASM_ARCH_TI81XX_H
#define __ASM_ARCH_TI81XX_H
#define L4_SLOW_TI816X_BASE 0x48000000
#define L4_SLOW_TI81XX_BASE 0x48000000
#define TI816X_SCM_BASE 0x48140000
#define TI816X_CTRL_BASE TI816X_SCM_BASE
#define TI816X_PRCM_BASE 0x48180000
#define TI81XX_SCM_BASE 0x48140000
#define TI81XX_CTRL_BASE TI81XX_SCM_BASE
#define TI81XX_PRCM_BASE 0x48180000
#define TI816X_ARM_INTC_BASE 0x48200000
#define TI81XX_ARM_INTC_BASE 0x48200000
#endif /* __ASM_ARCH_TI816X_H */
#endif /* __ASM_ARCH_TI81XX_H */

8
arch/arm/plat-omap/include/plat/uncompress.h
View File

@ -99,9 +99,9 @@ static inline void flush(void)
#define DEBUG_LL_ZOOM(mach) \
_DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
#define DEBUG_LL_TI816X(p, mach) \
_DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \
TI816XUART##p)
#define DEBUG_LL_TI81XX(p, mach) \
_DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
TI81XXUART##p)
static inline void __arch_decomp_setup(unsigned long arch_id)
{
@ -177,7 +177,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_ZOOM(omap_zoom3);
/* TI8168 base boards using UART3 */
DEBUG_LL_TI816X(3, ti8168evm);
DEBUG_LL_TI81XX(3, ti8168evm);
} while (0);
}