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spi: fsl-espi: fix support for all available clock rates 

According to NXP ESPI datasheet, the SPI clock rate is:

    spi_clk = System_Clock / ( 2 * DIV16 * ( 1 + PM ) )

Where System_Clock is the platform clock divided by 2,
DIV16 may be 1 or 16, and PM is a 4 bits integer (0 to 15).

Isolating PM on the expression, we get:

    PM = (System_Clock / ( 2 * DIV16 * spi_clk ) ) - 1

Where System_Clock = mpc8xxx_spi->spibrg / 2, spi_clk = hz,
and DIV16 = 1 or DIV16 = 16. So,

    PM = (mpc8xxx_spi->spibrg / ( 4 * hz) ) - 1
or
    PM = (mpc8xxx_spi->spibrg / ( 16 * 4 * hz) ) - 1

Current spi-fsl-espi driver can't configure the HW for all
supported clock rates. It filters out clock rates for PM = 0
and PM = 1.

This patch allows all range of supported clock rates to be
configured on the ESPI controller.

Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Paulo Zaneti 2016-10-29 11:02:19 +02:00 committed by Mark Brown
parent 66b8053e24
commit 73aaf15849
1 changed files with 12 additions and 16 deletions
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28
drivers/spi/spi-fsl-espi.c
View File

@ -247,8 +247,7 @@ static void fsl_espi_setup_transfer(struct spi_device *spi,
{
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
u32 hz = t ? t->speed_hz : spi->max_speed_hz;
u8 pm;
u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
struct spi_mpc8xxx_cs *cs = spi->controller_state;
/* mask out bits we are going to set */
@ -256,22 +255,19 @@ static void fsl_espi_setup_transfer(struct spi_device *spi,
cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
if ((mpc8xxx_spi->spibrg / hz) > 64) {
cs->hw_mode |= CSMODE_DIV16;
pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4) - 1;
WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
"Will use %d Hz instead.\n", dev_name(&spi->dev),
hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
if (pm > 33)
pm = 33;
} else {
pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
if (pm > 15) {
cs->hw_mode |= CSMODE_DIV16;
pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4) - 1;
WARN_ONCE(pm > 15,
"%s: Requested speed is too low: %u Hz. Will use %u Hz instead.\n",
dev_name(&spi->dev), hz,
mpc8xxx_spi->spibrg / (4 * 16 * (15 + 1)));
if (pm > 15)
pm = 15;
}
if (pm)
pm--;
if (pm < 2)
pm = 2;
cs->hw_mode |= CSMODE_PM(pm);