drivers/clk: common clock framework
This branch contains patches from Mike Turquette adding a common clock framework to be shared across platforms. This is part of the work towards building a common zImage for several ARM platforms. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPcp6BAAoJEIwa5zzehBx3xR0P/1p3AhjocYIG+2jP7KyxDS6u 4o0hbnO7783SP3fStgbHrMYwfzAP2X8hBUpzcGkFCGJC6jJ2/oI/Vp+eoOV0KvfW IAeQB6PsSP3kNv6VRjnhvnLC3HDlKfgraNb3BC/Fep9DfswHRWa413qver9MQcW8 20Z6deu26i4Ia26NbNJ/NjU7hINbLdE1guw0rydUlZ4R1n0DUPSSuHwNmUsE+OoO m/hzhY2vYBc+F48MtOjX9VOGX6VjnEZOq1MUtdrJn73iXRhE6/nI8142XfsjXh5V pa7HZHHWXTybG8xs0G9oQEKah+OsyOFUtq68wlIntXnHeuzL61P0TZg/4hH4bxYX Lgn+xQABKkK0grKxr65Zvd58+e2mxYTZzj/uC9gq+DlWY9y7C5ShZ1RflUNIQ1dk tBjjV/Ux8flxlMtkwLJDQvP5pp6kzbHGf3jCD1rMLOGAq8SWpFgd8eRzE29O9XsW y1a1fpAB5JNpiSArmqsm0kXqgdoJocGFVN8AIxUYkBDDpRxI6rFlBCwlL6HZVRB9 iStFqaRsYyUiJb+KX1/etVuvxx89Af4QbK/4LXRRjb+Zg3PzBzQEiLltInONHqag G0W9kWfW/8n6wQXf1jdf2/oqji7GyLKjlFFXpSxDBHSxlW43nrtdWz+4MdrCD6CO T5+eV03WZ5UwGFjXd4Ff =9jfA -----END PGP SIGNATURE----- Merge tag 'common-clk-api' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull "drivers/clk: common clock framework" from Olof Johansson: "This branch contains patches from Mike Turquette adding a common clock framework to be shared across platforms. This is part of the work towards building a common zImage for several ARM platforms." * tag 'common-clk-api' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: clk: make CONFIG_COMMON_CLK invisible clk: basic clock hardware types clk: introduce the common clock framework Documentation: common clk API
This commit is contained in:
Linus Torvalds
commit
735e941caa
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@ -0,0 +1,233 @@
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The Common Clk Framework
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Mike Turquette <mturquette@ti.com>
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This document endeavours to explain the common clk framework details,
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and how to port a platform over to this framework. It is not yet a
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detailed explanation of the clock api in include/linux/clk.h, but
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perhaps someday it will include that information.
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Part 1 - introduction and interface split
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The common clk framework is an interface to control the clock nodes
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available on various devices today. This may come in the form of clock
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gating, rate adjustment, muxing or other operations. This framework is
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enabled with the CONFIG_COMMON_CLK option.
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The interface itself is divided into two halves, each shielded from the
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details of its counterpart. First is the common definition of struct
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clk which unifies the framework-level accounting and infrastructure that
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has traditionally been duplicated across a variety of platforms. Second
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is a common implementation of the clk.h api, defined in
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drivers/clk/clk.c. Finally there is struct clk_ops, whose operations
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are invoked by the clk api implementation.
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The second half of the interface is comprised of the hardware-specific
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callbacks registered with struct clk_ops and the corresponding
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hardware-specific structures needed to model a particular clock. For
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the remainder of this document any reference to a callback in struct
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clk_ops, such as .enable or .set_rate, implies the hardware-specific
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implementation of that code. Likewise, references to struct clk_foo
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serve as a convenient shorthand for the implementation of the
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hardware-specific bits for the hypothetical "foo" hardware.
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Tying the two halves of this interface together is struct clk_hw, which
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is defined in struct clk_foo and pointed to within struct clk. This
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allows easy for navigation between the two discrete halves of the common
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clock interface.
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Part 2 - common data structures and api
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Below is the common struct clk definition from
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include/linux/clk-private.h, modified for brevity:
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struct clk {
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const char *name;
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const struct clk_ops *ops;
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struct clk_hw *hw;
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char **parent_names;
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struct clk **parents;
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struct clk *parent;
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struct hlist_head children;
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struct hlist_node child_node;
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...
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};
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The members above make up the core of the clk tree topology. The clk
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api itself defines several driver-facing functions which operate on
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struct clk. That api is documented in include/linux/clk.h.
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Platforms and devices utilizing the common struct clk use the struct
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clk_ops pointer in struct clk to perform the hardware-specific parts of
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the operations defined in clk.h:
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struct clk_ops {
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int (*prepare)(struct clk_hw *hw);
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void (*unprepare)(struct clk_hw *hw);
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int (*enable)(struct clk_hw *hw);
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void (*disable)(struct clk_hw *hw);
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int (*is_enabled)(struct clk_hw *hw);
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unsigned long (*recalc_rate)(struct clk_hw *hw,
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unsigned long parent_rate);
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long (*round_rate)(struct clk_hw *hw, unsigned long,
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unsigned long *);
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int (*set_parent)(struct clk_hw *hw, u8 index);
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u8 (*get_parent)(struct clk_hw *hw);
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int (*set_rate)(struct clk_hw *hw, unsigned long);
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void (*init)(struct clk_hw *hw);
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};
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Part 3 - hardware clk implementations
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The strength of the common struct clk comes from its .ops and .hw pointers
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which abstract the details of struct clk from the hardware-specific bits, and
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vice versa. To illustrate consider the simple gateable clk implementation in
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drivers/clk/clk-gate.c:
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struct clk_gate {
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struct clk_hw hw;
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void __iomem *reg;
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u8 bit_idx;
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...
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};
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struct clk_gate contains struct clk_hw hw as well as hardware-specific
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knowledge about which register and bit controls this clk's gating.
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Nothing about clock topology or accounting, such as enable_count or
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notifier_count, is needed here. That is all handled by the common
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framework code and struct clk.
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Let's walk through enabling this clk from driver code:
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struct clk *clk;
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clk = clk_get(NULL, "my_gateable_clk");
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clk_prepare(clk);
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clk_enable(clk);
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The call graph for clk_enable is very simple:
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clk_enable(clk);
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clk->ops->enable(clk->hw);
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[resolves to...]
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clk_gate_enable(hw);
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[resolves struct clk gate with to_clk_gate(hw)]
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clk_gate_set_bit(gate);
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And the definition of clk_gate_set_bit:
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static void clk_gate_set_bit(struct clk_gate *gate)
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{
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u32 reg;
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reg = __raw_readl(gate->reg);
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reg |= BIT(gate->bit_idx);
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writel(reg, gate->reg);
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}
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Note that to_clk_gate is defined as:
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#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, clk)
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This pattern of abstraction is used for every clock hardware
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representation.
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Part 4 - supporting your own clk hardware
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When implementing support for a new type of clock it only necessary to
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include the following header:
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#include <linux/clk-provider.h>
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include/linux/clk.h is included within that header and clk-private.h
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must never be included from the code which implements the operations for
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a clock. More on that below in Part 5.
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To construct a clk hardware structure for your platform you must define
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the following:
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struct clk_foo {
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struct clk_hw hw;
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... hardware specific data goes here ...
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};
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To take advantage of your data you'll need to support valid operations
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for your clk:
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struct clk_ops clk_foo_ops {
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.enable = &clk_foo_enable;
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.disable = &clk_foo_disable;
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};
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Implement the above functions using container_of:
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#define to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw)
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int clk_foo_enable(struct clk_hw *hw)
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{
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struct clk_foo *foo;
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foo = to_clk_foo(hw);
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... perform magic on foo ...
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return 0;
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};
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Below is a matrix detailing which clk_ops are mandatory based upon the
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hardware capbilities of that clock. A cell marked as "y" means
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mandatory, a cell marked as "n" implies that either including that
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callback is invalid or otherwise uneccesary. Empty cells are either
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optional or must be evaluated on a case-by-case basis.
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clock hardware characteristics
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-----------------------------------------------------------
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| gate | change rate | single parent | multiplexer | root |
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|------|-------------|---------------|-------------|------|
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.prepare | | | | | |
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.unprepare | | | | | |
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| | | | | |
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.enable | y | | | | |
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.disable | y | | | | |
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.is_enabled | y | | | | |
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| | | | | |
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.recalc_rate | | y | | | |
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.round_rate | | y | | | |
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.set_rate | | y | | | |
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| | | | | |
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.set_parent | | | n | y | n |
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.get_parent | | | n | y | n |
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| | | | | |
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.init | | | | | |
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-----------------------------------------------------------
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Finally, register your clock at run-time with a hardware-specific
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registration function. This function simply populates struct clk_foo's
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data and then passes the common struct clk parameters to the framework
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with a call to:
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clk_register(...)
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See the basic clock types in drivers/clk/clk-*.c for examples.
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Part 5 - static initialization of clock data
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For platforms with many clocks (often numbering into the hundreds) it
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may be desirable to statically initialize some clock data. This
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presents a problem since the definition of struct clk should be hidden
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from everyone except for the clock core in drivers/clk/clk.c.
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To get around this problem struct clk's definition is exposed in
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include/linux/clk-private.h along with some macros for more easily
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initializing instances of the basic clock types. These clocks must
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still be initialized with the common clock framework via a call to
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__clk_init.
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clk-private.h must NEVER be included by code which implements struct
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clk_ops callbacks, nor must it be included by any logic which pokes
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around inside of struct clk at run-time. To do so is a layering
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violation.
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To better enforce this policy, always follow this simple rule: any
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statically initialized clock data MUST be defined in a separate file
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from the logic that implements its ops. Basically separate the logic
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from the data and all is well.
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@ -8,3 +8,40 @@ config HAVE_CLK_PREPARE
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config HAVE_MACH_CLKDEV
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bool
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config COMMON_CLK
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bool
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select HAVE_CLK_PREPARE
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---help---
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The common clock framework is a single definition of struct
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clk, useful across many platforms, as well as an
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implementation of the clock API in include/linux/clk.h.
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Architectures utilizing the common struct clk should select
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this option.
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menu "Common Clock Framework"
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depends on COMMON_CLK
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config COMMON_CLK_DISABLE_UNUSED
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bool "Disabled unused clocks at boot"
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depends on COMMON_CLK
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---help---
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Traverses the entire clock tree and disables any clocks that are
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enabled in hardware but have not been enabled by any device drivers.
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This saves power and keeps the software model of the clock in line
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with reality.
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If in doubt, say "N".
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config COMMON_CLK_DEBUG
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bool "DebugFS representation of clock tree"
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depends on COMMON_CLK
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select DEBUG_FS
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---help---
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Creates a directory hierchy in debugfs for visualizing the clk
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tree structure. Each directory contains read-only members
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that export information specific to that clk node: clk_rate,
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clk_flags, clk_prepare_count, clk_enable_count &
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clk_notifier_count.
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endmenu
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@ -1,2 +1,4 @@
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obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
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obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
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clk-mux.o clk-divider.o
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@ -0,0 +1,200 @@
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/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable divider clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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/*
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* DOC: basic adjustable divider clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is adjustable. clk->rate = parent->rate / divisor
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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#define div_mask(d) ((1 << (d->width)) - 1)
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static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div;
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div = readl(divider->reg) >> divider->shift;
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div &= div_mask(divider);
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if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
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div++;
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return parent_rate / div;
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}
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EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
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/*
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* The reverse of DIV_ROUND_UP: The maximum number which
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* divided by m is r
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*/
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#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
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static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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int i, bestdiv = 0;
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unsigned long parent_rate, best = 0, now, maxdiv;
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if (!rate)
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rate = 1;
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maxdiv = (1 << divider->width);
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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maxdiv--;
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if (!best_parent_rate) {
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parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
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bestdiv = DIV_ROUND_UP(parent_rate, rate);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
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return bestdiv;
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}
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/*
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* The maximum divider we can use without overflowing
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* unsigned long in rate * i below
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*/
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 1; i <= maxdiv; i++) {
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parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
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MULT_ROUND_UP(rate, i));
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now = parent_rate / i;
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if (now <= rate && now > best) {
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bestdiv = i;
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best = now;
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*best_parent_rate = parent_rate;
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}
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}
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if (!bestdiv) {
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bestdiv = (1 << divider->width);
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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bestdiv--;
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*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
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}
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return bestdiv;
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}
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static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int div;
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div = clk_divider_bestdiv(hw, rate, prate);
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|
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if (prate)
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return *prate / div;
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else {
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unsigned long r;
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r = __clk_get_rate(__clk_get_parent(hw->clk));
|
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return r / div;
|
||||
}
|
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}
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EXPORT_SYMBOL_GPL(clk_divider_round_rate);
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static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
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{
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
unsigned int div;
|
||||
unsigned long flags = 0;
|
||||
u32 val;
|
||||
|
||||
div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;
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||||
|
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if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
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div--;
|
||||
|
||||
if (div > div_mask(divider))
|
||||
div = div_mask(divider);
|
||||
|
||||
if (divider->lock)
|
||||
spin_lock_irqsave(divider->lock, flags);
|
||||
|
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val = readl(divider->reg);
|
||||
val &= ~(div_mask(divider) << divider->shift);
|
||||
val |= div << divider->shift;
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writel(val, divider->reg);
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|
||||
if (divider->lock)
|
||||
spin_unlock_irqrestore(divider->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_divider_set_rate);
|
||||
|
||||
struct clk_ops clk_divider_ops = {
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||||
.recalc_rate = clk_divider_recalc_rate,
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.round_rate = clk_divider_round_rate,
|
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.set_rate = clk_divider_set_rate,
|
||||
};
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||||
EXPORT_SYMBOL_GPL(clk_divider_ops);
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||||
struct clk *clk_register_divider(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags, spinlock_t *lock)
|
||||
{
|
||||
struct clk_divider *div;
|
||||
struct clk *clk;
|
||||
|
||||
div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
|
||||
|
||||
if (!div) {
|
||||
pr_err("%s: could not allocate divider clk\n", __func__);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* struct clk_divider assignments */
|
||||
div->reg = reg;
|
||||
div->shift = shift;
|
||||
div->width = width;
|
||||
div->flags = clk_divider_flags;
|
||||
div->lock = lock;
|
||||
|
||||
if (parent_name) {
|
||||
div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
|
||||
if (!div->parent[0])
|
||||
goto out;
|
||||
}
|
||||
|
||||
clk = clk_register(dev, name,
|
||||
&clk_divider_ops, &div->hw,
|
||||
div->parent,
|
||||
(parent_name ? 1 : 0),
|
||||
flags);
|
||||
if (clk)
|
||||
return clk;
|
||||
|
||||
out:
|
||||
kfree(div->parent[0]);
|
||||
kfree(div);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
|
||||
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Fixed rate clock implementation
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
/*
|
||||
* DOC: basic fixed-rate clock that cannot gate
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_(un)prepare only ensures parents are prepared
|
||||
* enable - clk_enable only ensures parents are enabled
|
||||
* rate - rate is always a fixed value. No clk_set_rate support
|
||||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
|
||||
|
||||
static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
return to_clk_fixed_rate(hw)->fixed_rate;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
|
||||
|
||||
struct clk_ops clk_fixed_rate_ops = {
|
||||
.recalc_rate = clk_fixed_rate_recalc_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
|
||||
|
||||
struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
unsigned long fixed_rate)
|
||||
{
|
||||
struct clk_fixed_rate *fixed;
|
||||
char **parent_names = NULL;
|
||||
u8 len;
|
||||
|
||||
fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
|
||||
|
||||
if (!fixed) {
|
||||
pr_err("%s: could not allocate fixed clk\n", __func__);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
/* struct clk_fixed_rate assignments */
|
||||
fixed->fixed_rate = fixed_rate;
|
||||
|
||||
if (parent_name) {
|
||||
parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
|
||||
|
||||
if (! parent_names)
|
||||
goto out;
|
||||
|
||||
len = sizeof(char) * strlen(parent_name);
|
||||
|
||||
parent_names[0] = kmalloc(len, GFP_KERNEL);
|
||||
|
||||
if (!parent_names[0])
|
||||
goto out;
|
||||
|
||||
strncpy(parent_names[0], parent_name, len);
|
||||
}
|
||||
|
||||
out:
|
||||
return clk_register(dev, name,
|
||||
&clk_fixed_rate_ops, &fixed->hw,
|
||||
parent_names,
|
||||
(parent_name ? 1 : 0),
|
||||
flags);
|
||||
}
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
|
||||
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Gated clock implementation
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
/**
|
||||
* DOC: basic gatable clock which can gate and ungate it's ouput
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_(un)prepare only ensures parent is (un)prepared
|
||||
* enable - clk_enable and clk_disable are functional & control gating
|
||||
* rate - inherits rate from parent. No clk_set_rate support
|
||||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
static void clk_gate_set_bit(struct clk_gate *gate)
|
||||
{
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (gate->lock)
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
reg = readl(gate->reg);
|
||||
reg |= BIT(gate->bit_idx);
|
||||
writel(reg, gate->reg);
|
||||
|
||||
if (gate->lock)
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
}
|
||||
|
||||
static void clk_gate_clear_bit(struct clk_gate *gate)
|
||||
{
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (gate->lock)
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
reg = readl(gate->reg);
|
||||
reg &= ~BIT(gate->bit_idx);
|
||||
writel(reg, gate->reg);
|
||||
|
||||
if (gate->lock)
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
}
|
||||
|
||||
static int clk_gate_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate *gate = to_clk_gate(hw);
|
||||
|
||||
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
|
||||
clk_gate_clear_bit(gate);
|
||||
else
|
||||
clk_gate_set_bit(gate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_gate_enable);
|
||||
|
||||
static void clk_gate_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate *gate = to_clk_gate(hw);
|
||||
|
||||
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
|
||||
clk_gate_set_bit(gate);
|
||||
else
|
||||
clk_gate_clear_bit(gate);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_gate_disable);
|
||||
|
||||
static int clk_gate_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
u32 reg;
|
||||
struct clk_gate *gate = to_clk_gate(hw);
|
||||
|
||||
reg = readl(gate->reg);
|
||||
|
||||
/* if a set bit disables this clk, flip it before masking */
|
||||
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
|
||||
reg ^= BIT(gate->bit_idx);
|
||||
|
||||
reg &= BIT(gate->bit_idx);
|
||||
|
||||
return reg ? 1 : 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
|
||||
|
||||
struct clk_ops clk_gate_ops = {
|
||||
.enable = clk_gate_enable,
|
||||
.disable = clk_gate_disable,
|
||||
.is_enabled = clk_gate_is_enabled,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_gate_ops);
|
||||
|
||||
struct clk *clk_register_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock)
|
||||
{
|
||||
struct clk_gate *gate;
|
||||
struct clk *clk;
|
||||
|
||||
gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
|
||||
|
||||
if (!gate) {
|
||||
pr_err("%s: could not allocate gated clk\n", __func__);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* struct clk_gate assignments */
|
||||
gate->reg = reg;
|
||||
gate->bit_idx = bit_idx;
|
||||
gate->flags = clk_gate_flags;
|
||||
gate->lock = lock;
|
||||
|
||||
if (parent_name) {
|
||||
gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
|
||||
if (!gate->parent[0])
|
||||
goto out;
|
||||
}
|
||||
|
||||
clk = clk_register(dev, name,
|
||||
&clk_gate_ops, &gate->hw,
|
||||
gate->parent,
|
||||
(parent_name ? 1 : 0),
|
||||
flags);
|
||||
if (clk)
|
||||
return clk;
|
||||
out:
|
||||
kfree(gate->parent[0]);
|
||||
kfree(gate);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
|
||||
* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
|
||||
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Simple multiplexer clock implementation
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
/*
|
||||
* DOC: basic adjustable multiplexer clock that cannot gate
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_prepare only ensures that parents are prepared
|
||||
* enable - clk_enable only ensures that parents are enabled
|
||||
* rate - rate is only affected by parent switching. No clk_set_rate support
|
||||
* parent - parent is adjustable through clk_set_parent
|
||||
*/
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
static u8 clk_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* FIXME need a mux-specific flag to determine if val is bitwise or numeric
|
||||
* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
|
||||
* to 0x7 (index starts at one)
|
||||
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
|
||||
* val = 0x4 really means "bit 2, index starts at bit 0"
|
||||
*/
|
||||
val = readl(mux->reg) >> mux->shift;
|
||||
val &= (1 << mux->width) - 1;
|
||||
|
||||
if (val && (mux->flags & CLK_MUX_INDEX_BIT))
|
||||
val = ffs(val) - 1;
|
||||
|
||||
if (val && (mux->flags & CLK_MUX_INDEX_ONE))
|
||||
val--;
|
||||
|
||||
if (val >= __clk_get_num_parents(hw->clk))
|
||||
return -EINVAL;
|
||||
|
||||
return val;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_mux_get_parent);
|
||||
|
||||
static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
u32 val;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (mux->flags & CLK_MUX_INDEX_BIT)
|
||||
index = (1 << ffs(index));
|
||||
|
||||
if (mux->flags & CLK_MUX_INDEX_ONE)
|
||||
index++;
|
||||
|
||||
if (mux->lock)
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
|
||||
val = readl(mux->reg);
|
||||
val &= ~(((1 << mux->width) - 1) << mux->shift);
|
||||
val |= index << mux->shift;
|
||||
writel(val, mux->reg);
|
||||
|
||||
if (mux->lock)
|
||||
spin_unlock_irqrestore(mux->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_mux_set_parent);
|
||||
|
||||
struct clk_ops clk_mux_ops = {
|
||||
.get_parent = clk_mux_get_parent,
|
||||
.set_parent = clk_mux_set_parent,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_mux_ops);
|
||||
|
||||
struct clk *clk_register_mux(struct device *dev, const char *name,
|
||||
char **parent_names, u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_mux_flags, spinlock_t *lock)
|
||||
{
|
||||
struct clk_mux *mux;
|
||||
|
||||
mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
|
||||
|
||||
if (!mux) {
|
||||
pr_err("%s: could not allocate mux clk\n", __func__);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
/* struct clk_mux assignments */
|
||||
mux->reg = reg;
|
||||
mux->shift = shift;
|
||||
mux->width = width;
|
||||
mux->flags = clk_mux_flags;
|
||||
mux->lock = lock;
|
||||
|
||||
return clk_register(dev, name, &clk_mux_ops, &mux->hw,
|
||||
parent_names, num_parents, flags);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* linux/include/linux/clk-private.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
|
||||
* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __LINUX_CLK_PRIVATE_H
|
||||
#define __LINUX_CLK_PRIVATE_H
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
/*
|
||||
* WARNING: Do not include clk-private.h from any file that implements struct
|
||||
* clk_ops. Doing so is a layering violation!
|
||||
*
|
||||
* This header exists only to allow for statically initialized clock data. Any
|
||||
* static clock data must be defined in a separate file from the logic that
|
||||
* implements the clock operations for that same data.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
|
||||
struct clk {
|
||||
const char *name;
|
||||
const struct clk_ops *ops;
|
||||
struct clk_hw *hw;
|
||||
struct clk *parent;
|
||||
char **parent_names;
|
||||
struct clk **parents;
|
||||
u8 num_parents;
|
||||
unsigned long rate;
|
||||
unsigned long new_rate;
|
||||
unsigned long flags;
|
||||
unsigned int enable_count;
|
||||
unsigned int prepare_count;
|
||||
struct hlist_head children;
|
||||
struct hlist_node child_node;
|
||||
unsigned int notifier_count;
|
||||
#ifdef CONFIG_COMMON_CLK_DEBUG
|
||||
struct dentry *dentry;
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* DOC: Basic clock implementations common to many platforms
|
||||
*
|
||||
* Each basic clock hardware type is comprised of a structure describing the
|
||||
* clock hardware, implementations of the relevant callbacks in struct clk_ops,
|
||||
* unique flags for that hardware type, a registration function and an
|
||||
* alternative macro for static initialization
|
||||
*/
|
||||
|
||||
extern struct clk_ops clk_fixed_rate_ops;
|
||||
|
||||
#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
|
||||
_fixed_rate_flags) \
|
||||
static struct clk _name; \
|
||||
static char *_name##_parent_names[] = {}; \
|
||||
static struct clk_fixed_rate _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.fixed_rate = _rate, \
|
||||
.flags = _fixed_rate_flags, \
|
||||
}; \
|
||||
static struct clk _name = { \
|
||||
.name = #_name, \
|
||||
.ops = &clk_fixed_rate_ops, \
|
||||
.hw = &_name##_hw.hw, \
|
||||
.parent_names = _name##_parent_names, \
|
||||
.num_parents = \
|
||||
ARRAY_SIZE(_name##_parent_names), \
|
||||
.flags = _flags, \
|
||||
};
|
||||
|
||||
extern struct clk_ops clk_gate_ops;
|
||||
|
||||
#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \
|
||||
_flags, _reg, _bit_idx, \
|
||||
_gate_flags, _lock) \
|
||||
static struct clk _name; \
|
||||
static char *_name##_parent_names[] = { \
|
||||
_parent_name, \
|
||||
}; \
|
||||
static struct clk *_name##_parents[] = { \
|
||||
_parent_ptr, \
|
||||
}; \
|
||||
static struct clk_gate _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.reg = _reg, \
|
||||
.bit_idx = _bit_idx, \
|
||||
.flags = _gate_flags, \
|
||||
.lock = _lock, \
|
||||
}; \
|
||||
static struct clk _name = { \
|
||||
.name = #_name, \
|
||||
.ops = &clk_gate_ops, \
|
||||
.hw = &_name##_hw.hw, \
|
||||
.parent_names = _name##_parent_names, \
|
||||
.num_parents = \
|
||||
ARRAY_SIZE(_name##_parent_names), \
|
||||
.parents = _name##_parents, \
|
||||
.flags = _flags, \
|
||||
};
|
||||
|
||||
extern struct clk_ops clk_divider_ops;
|
||||
|
||||
#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
|
||||
_flags, _reg, _shift, _width, \
|
||||
_divider_flags, _lock) \
|
||||
static struct clk _name; \
|
||||
static char *_name##_parent_names[] = { \
|
||||
_parent_name, \
|
||||
}; \
|
||||
static struct clk *_name##_parents[] = { \
|
||||
_parent_ptr, \
|
||||
}; \
|
||||
static struct clk_divider _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.flags = _divider_flags, \
|
||||
.lock = _lock, \
|
||||
}; \
|
||||
static struct clk _name = { \
|
||||
.name = #_name, \
|
||||
.ops = &clk_divider_ops, \
|
||||
.hw = &_name##_hw.hw, \
|
||||
.parent_names = _name##_parent_names, \
|
||||
.num_parents = \
|
||||
ARRAY_SIZE(_name##_parent_names), \
|
||||
.parents = _name##_parents, \
|
||||
.flags = _flags, \
|
||||
};
|
||||
|
||||
extern struct clk_ops clk_mux_ops;
|
||||
|
||||
#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
|
||||
_reg, _shift, _width, \
|
||||
_mux_flags, _lock) \
|
||||
static struct clk _name; \
|
||||
static struct clk_mux _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.flags = _mux_flags, \
|
||||
.lock = _lock, \
|
||||
}; \
|
||||
static struct clk _name = { \
|
||||
.name = #_name, \
|
||||
.ops = &clk_mux_ops, \
|
||||
.hw = &_name##_hw.hw, \
|
||||
.parent_names = _parent_names, \
|
||||
.num_parents = \
|
||||
ARRAY_SIZE(_parent_names), \
|
||||
.parents = _parents, \
|
||||
.flags = _flags, \
|
||||
};
|
||||
|
||||
/**
|
||||
* __clk_init - initialize the data structures in a struct clk
|
||||
* @dev: device initializing this clk, placeholder for now
|
||||
* @clk: clk being initialized
|
||||
*
|
||||
* Initializes the lists in struct clk, queries the hardware for the
|
||||
* parent and rate and sets them both.
|
||||
*
|
||||
* Any struct clk passed into __clk_init must have the following members
|
||||
* populated:
|
||||
* .name
|
||||
* .ops
|
||||
* .hw
|
||||
* .parent_names
|
||||
* .num_parents
|
||||
* .flags
|
||||
*
|
||||
* It is not necessary to call clk_register if __clk_init is used directly with
|
||||
* statically initialized clock data.
|
||||
*/
|
||||
void __clk_init(struct device *dev, struct clk *clk);
|
||||
|
||||
#endif /* CONFIG_COMMON_CLK */
|
||||
#endif /* CLK_PRIVATE_H */
|
||||
|
|
@ -0,0 +1,300 @@
|
|||
/*
|
||||
* linux/include/linux/clk-provider.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
|
||||
* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __LINUX_CLK_PROVIDER_H
|
||||
#define __LINUX_CLK_PROVIDER_H
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
|
||||
/**
|
||||
* struct clk_hw - handle for traversing from a struct clk to its corresponding
|
||||
* hardware-specific structure. struct clk_hw should be declared within struct
|
||||
* clk_foo and then referenced by the struct clk instance that uses struct
|
||||
* clk_foo's clk_ops
|
||||
*
|
||||
* clk: pointer to the struct clk instance that points back to this struct
|
||||
* clk_hw instance
|
||||
*/
|
||||
struct clk_hw {
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
/*
|
||||
* flags used across common struct clk. these flags should only affect the
|
||||
* top-level framework. custom flags for dealing with hardware specifics
|
||||
* belong in struct clk_foo
|
||||
*/
|
||||
#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
|
||||
#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
|
||||
#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
|
||||
#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
|
||||
#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
|
||||
|
||||
/**
|
||||
* struct clk_ops - Callback operations for hardware clocks; these are to
|
||||
* be provided by the clock implementation, and will be called by drivers
|
||||
* through the clk_* api.
|
||||
*
|
||||
* @prepare: Prepare the clock for enabling. This must not return until
|
||||
* the clock is fully prepared, and it's safe to call clk_enable.
|
||||
* This callback is intended to allow clock implementations to
|
||||
* do any initialisation that may sleep. Called with
|
||||
* prepare_lock held.
|
||||
*
|
||||
* @unprepare: Release the clock from its prepared state. This will typically
|
||||
* undo any work done in the @prepare callback. Called with
|
||||
* prepare_lock held.
|
||||
*
|
||||
* @enable: Enable the clock atomically. This must not return until the
|
||||
* clock is generating a valid clock signal, usable by consumer
|
||||
* devices. Called with enable_lock held. This function must not
|
||||
* sleep.
|
||||
*
|
||||
* @disable: Disable the clock atomically. Called with enable_lock held.
|
||||
* This function must not sleep.
|
||||
*
|
||||
* @recalc_rate Recalculate the rate of this clock, by quering hardware. The
|
||||
* parent rate is an input parameter. It is up to the caller to
|
||||
* insure that the prepare_mutex is held across this call.
|
||||
* Returns the calculated rate. Optional, but recommended - if
|
||||
* this op is not set then clock rate will be initialized to 0.
|
||||
*
|
||||
* @round_rate: Given a target rate as input, returns the closest rate actually
|
||||
* supported by the clock.
|
||||
*
|
||||
* @get_parent: Queries the hardware to determine the parent of a clock. The
|
||||
* return value is a u8 which specifies the index corresponding to
|
||||
* the parent clock. This index can be applied to either the
|
||||
* .parent_names or .parents arrays. In short, this function
|
||||
* translates the parent value read from hardware into an array
|
||||
* index. Currently only called when the clock is initialized by
|
||||
* __clk_init. This callback is mandatory for clocks with
|
||||
* multiple parents. It is optional (and unnecessary) for clocks
|
||||
* with 0 or 1 parents.
|
||||
*
|
||||
* @set_parent: Change the input source of this clock; for clocks with multiple
|
||||
* possible parents specify a new parent by passing in the index
|
||||
* as a u8 corresponding to the parent in either the .parent_names
|
||||
* or .parents arrays. This function in affect translates an
|
||||
* array index into the value programmed into the hardware.
|
||||
* Returns 0 on success, -EERROR otherwise.
|
||||
*
|
||||
* @set_rate: Change the rate of this clock. If this callback returns
|
||||
* CLK_SET_RATE_PARENT, the rate change will be propagated to the
|
||||
* parent clock (which may propagate again if the parent clock
|
||||
* also sets this flag). The requested rate of the parent is
|
||||
* passed back from the callback in the second 'unsigned long *'
|
||||
* argument. Note that it is up to the hardware clock's set_rate
|
||||
* implementation to insure that clocks do not run out of spec
|
||||
* when propgating the call to set_rate up to the parent. One way
|
||||
* to do this is to gate the clock (via clk_disable and/or
|
||||
* clk_unprepare) before calling clk_set_rate, then ungating it
|
||||
* afterward. If your clock also has the CLK_GATE_SET_RATE flag
|
||||
* set then this will insure safety. Returns 0 on success,
|
||||
* -EERROR otherwise.
|
||||
*
|
||||
* The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
|
||||
* implementations to split any work between atomic (enable) and sleepable
|
||||
* (prepare) contexts. If enabling a clock requires code that might sleep,
|
||||
* this must be done in clk_prepare. Clock enable code that will never be
|
||||
* called in a sleepable context may be implement in clk_enable.
|
||||
*
|
||||
* Typically, drivers will call clk_prepare when a clock may be needed later
|
||||
* (eg. when a device is opened), and clk_enable when the clock is actually
|
||||
* required (eg. from an interrupt). Note that clk_prepare MUST have been
|
||||
* called before clk_enable.
|
||||
*/
|
||||
struct clk_ops {
|
||||
int (*prepare)(struct clk_hw *hw);
|
||||
void (*unprepare)(struct clk_hw *hw);
|
||||
int (*enable)(struct clk_hw *hw);
|
||||
void (*disable)(struct clk_hw *hw);
|
||||
int (*is_enabled)(struct clk_hw *hw);
|
||||
unsigned long (*recalc_rate)(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
long (*round_rate)(struct clk_hw *hw, unsigned long,
|
||||
unsigned long *);
|
||||
int (*set_parent)(struct clk_hw *hw, u8 index);
|
||||
u8 (*get_parent)(struct clk_hw *hw);
|
||||
int (*set_rate)(struct clk_hw *hw, unsigned long);
|
||||
void (*init)(struct clk_hw *hw);
|
||||
};
|
||||
|
||||
/*
|
||||
* DOC: Basic clock implementations common to many platforms
|
||||
*
|
||||
* Each basic clock hardware type is comprised of a structure describing the
|
||||
* clock hardware, implementations of the relevant callbacks in struct clk_ops,
|
||||
* unique flags for that hardware type, a registration function and an
|
||||
* alternative macro for static initialization
|
||||
*/
|
||||
|
||||
/**
|
||||
* struct clk_fixed_rate - fixed-rate clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @fixed_rate: constant frequency of clock
|
||||
*/
|
||||
struct clk_fixed_rate {
|
||||
struct clk_hw hw;
|
||||
unsigned long fixed_rate;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
unsigned long fixed_rate);
|
||||
|
||||
/**
|
||||
* struct clk_gate - gating clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @reg: register controlling gate
|
||||
* @bit_idx: single bit controlling gate
|
||||
* @flags: hardware-specific flags
|
||||
* @lock: register lock
|
||||
*
|
||||
* Clock which can gate its output. Implements .enable & .disable
|
||||
*
|
||||
* Flags:
|
||||
* CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
|
||||
* enable the clock. Setting this flag does the opposite: setting the bit
|
||||
* disable the clock and clearing it enables the clock
|
||||
*/
|
||||
struct clk_gate {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u8 bit_idx;
|
||||
u8 flags;
|
||||
spinlock_t *lock;
|
||||
char *parent[1];
|
||||
};
|
||||
|
||||
#define CLK_GATE_SET_TO_DISABLE BIT(0)
|
||||
|
||||
struct clk *clk_register_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* struct clk_divider - adjustable divider clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @reg: register containing the divider
|
||||
* @shift: shift to the divider bit field
|
||||
* @width: width of the divider bit field
|
||||
* @lock: register lock
|
||||
*
|
||||
* Clock with an adjustable divider affecting its output frequency. Implements
|
||||
* .recalc_rate, .set_rate and .round_rate
|
||||
*
|
||||
* Flags:
|
||||
* CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
|
||||
* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
|
||||
* the raw value read from the register, with the value of zero considered
|
||||
* invalid
|
||||
* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
|
||||
* the hardware register
|
||||
*/
|
||||
struct clk_divider {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 flags;
|
||||
spinlock_t *lock;
|
||||
char *parent[1];
|
||||
};
|
||||
|
||||
#define CLK_DIVIDER_ONE_BASED BIT(0)
|
||||
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
|
||||
|
||||
struct clk *clk_register_divider(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags, spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* struct clk_mux - multiplexer clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @reg: register controlling multiplexer
|
||||
* @shift: shift to multiplexer bit field
|
||||
* @width: width of mutliplexer bit field
|
||||
* @num_clks: number of parent clocks
|
||||
* @lock: register lock
|
||||
*
|
||||
* Clock with multiple selectable parents. Implements .get_parent, .set_parent
|
||||
* and .recalc_rate
|
||||
*
|
||||
* Flags:
|
||||
* CLK_MUX_INDEX_ONE - register index starts at 1, not 0
|
||||
* CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
|
||||
*/
|
||||
struct clk_mux {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 flags;
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define CLK_MUX_INDEX_ONE BIT(0)
|
||||
#define CLK_MUX_INDEX_BIT BIT(1)
|
||||
|
||||
struct clk *clk_register_mux(struct device *dev, const char *name,
|
||||
char **parent_names, u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_mux_flags, spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* clk_register - allocate a new clock, register it and return an opaque cookie
|
||||
* @dev: device that is registering this clock
|
||||
* @name: clock name
|
||||
* @ops: operations this clock supports
|
||||
* @hw: link to hardware-specific clock data
|
||||
* @parent_names: array of string names for all possible parents
|
||||
* @num_parents: number of possible parents
|
||||
* @flags: framework-level hints and quirks
|
||||
*
|
||||
* clk_register is the primary interface for populating the clock tree with new
|
||||
* clock nodes. It returns a pointer to the newly allocated struct clk which
|
||||
* cannot be dereferenced by driver code but may be used in conjuction with the
|
||||
* rest of the clock API.
|
||||
*/
|
||||
struct clk *clk_register(struct device *dev, const char *name,
|
||||
const struct clk_ops *ops, struct clk_hw *hw,
|
||||
char **parent_names, u8 num_parents, unsigned long flags);
|
||||
|
||||
/* helper functions */
|
||||
const char *__clk_get_name(struct clk *clk);
|
||||
struct clk_hw *__clk_get_hw(struct clk *clk);
|
||||
u8 __clk_get_num_parents(struct clk *clk);
|
||||
struct clk *__clk_get_parent(struct clk *clk);
|
||||
inline int __clk_get_enable_count(struct clk *clk);
|
||||
inline int __clk_get_prepare_count(struct clk *clk);
|
||||
unsigned long __clk_get_rate(struct clk *clk);
|
||||
unsigned long __clk_get_flags(struct clk *clk);
|
||||
int __clk_is_enabled(struct clk *clk);
|
||||
struct clk *__clk_lookup(const char *name);
|
||||
|
||||
/*
|
||||
* FIXME clock api without lock protection
|
||||
*/
|
||||
int __clk_prepare(struct clk *clk);
|
||||
void __clk_unprepare(struct clk *clk);
|
||||
void __clk_reparent(struct clk *clk, struct clk *new_parent);
|
||||
unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
|
||||
|
||||
#endif /* CONFIG_COMMON_CLK */
|
||||
#endif /* CLK_PROVIDER_H */
|
||||
|
|
@ -3,6 +3,7 @@
|
|||
*
|
||||
* Copyright (C) 2004 ARM Limited.
|
||||
* Written by Deep Blue Solutions Limited.
|
||||
* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -12,19 +13,76 @@
|
|||
#define __LINUX_CLK_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/notifier.h>
|
||||
|
||||
struct device;
|
||||
|
||||
/*
|
||||
* The base API.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* struct clk - an machine class defined object / cookie.
|
||||
*/
|
||||
struct clk;
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
|
||||
/**
|
||||
* DOC: clk notifier callback types
|
||||
*
|
||||
* PRE_RATE_CHANGE - called immediately before the clk rate is changed,
|
||||
* to indicate that the rate change will proceed. Drivers must
|
||||
* immediately terminate any operations that will be affected by the
|
||||
* rate change. Callbacks may either return NOTIFY_DONE or
|
||||
* NOTIFY_STOP.
|
||||
*
|
||||
* ABORT_RATE_CHANGE: called if the rate change failed for some reason
|
||||
* after PRE_RATE_CHANGE. In this case, all registered notifiers on
|
||||
* the clk will be called with ABORT_RATE_CHANGE. Callbacks must
|
||||
* always return NOTIFY_DONE.
|
||||
*
|
||||
* POST_RATE_CHANGE - called after the clk rate change has successfully
|
||||
* completed. Callbacks must always return NOTIFY_DONE.
|
||||
*
|
||||
*/
|
||||
#define PRE_RATE_CHANGE BIT(0)
|
||||
#define POST_RATE_CHANGE BIT(1)
|
||||
#define ABORT_RATE_CHANGE BIT(2)
|
||||
|
||||
/**
|
||||
* struct clk_notifier - associate a clk with a notifier
|
||||
* @clk: struct clk * to associate the notifier with
|
||||
* @notifier_head: a blocking_notifier_head for this clk
|
||||
* @node: linked list pointers
|
||||
*
|
||||
* A list of struct clk_notifier is maintained by the notifier code.
|
||||
* An entry is created whenever code registers the first notifier on a
|
||||
* particular @clk. Future notifiers on that @clk are added to the
|
||||
* @notifier_head.
|
||||
*/
|
||||
struct clk_notifier {
|
||||
struct clk *clk;
|
||||
struct srcu_notifier_head notifier_head;
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clk_notifier_data - rate data to pass to the notifier callback
|
||||
* @clk: struct clk * being changed
|
||||
* @old_rate: previous rate of this clk
|
||||
* @new_rate: new rate of this clk
|
||||
*
|
||||
* For a pre-notifier, old_rate is the clk's rate before this rate
|
||||
* change, and new_rate is what the rate will be in the future. For a
|
||||
* post-notifier, old_rate and new_rate are both set to the clk's
|
||||
* current rate (this was done to optimize the implementation).
|
||||
*/
|
||||
struct clk_notifier_data {
|
||||
struct clk *clk;
|
||||
unsigned long old_rate;
|
||||
unsigned long new_rate;
|
||||
};
|
||||
|
||||
int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
|
||||
|
||||
int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
|
||||
|
||||
#endif /* !CONFIG_COMMON_CLK */
|
||||
|
||||
/**
|
||||
* clk_get - lookup and obtain a reference to a clock producer.
|
||||
* @dev: device for clock "consumer"
|
||||
|
|
|
|||
Loading…
Reference in New Issue