usb: dwc3: exynos: Add provision for suspend clock
DWC3 controller on Exynos SoC series have separate control for suspend clock which replaces pipe3_rx_pclk as clock source to a small part of DWC3 core that operates when SS PHY is in its lowest power state (P3) in states SS.disabled and U3. Suggested-by: Anton Tikhomirov <av.tikhomirov@samsung.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -34,6 +34,8 @@ struct dwc3_exynos {
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struct device *dev;
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struct device *dev;
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struct clk *clk;
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struct clk *clk;
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struct clk *susp_clk;
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struct regulator *vdd33;
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struct regulator *vdd33;
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struct regulator *vdd10;
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struct regulator *vdd10;
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};
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};
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@ -140,6 +142,13 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
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}
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}
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clk_prepare_enable(exynos->clk);
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clk_prepare_enable(exynos->clk);
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exynos->susp_clk = devm_clk_get(dev, "usbdrd30_susp_clk");
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if (IS_ERR(exynos->susp_clk)) {
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dev_dbg(dev, "no suspend clk specified\n");
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exynos->susp_clk = NULL;
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}
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clk_prepare_enable(exynos->susp_clk);
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exynos->vdd33 = devm_regulator_get(dev, "vdd33");
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exynos->vdd33 = devm_regulator_get(dev, "vdd33");
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if (IS_ERR(exynos->vdd33)) {
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if (IS_ERR(exynos->vdd33)) {
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ret = PTR_ERR(exynos->vdd33);
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ret = PTR_ERR(exynos->vdd33);
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@ -181,6 +190,7 @@ err4:
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err3:
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err3:
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regulator_disable(exynos->vdd33);
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regulator_disable(exynos->vdd33);
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err2:
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err2:
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clk_disable_unprepare(exynos->susp_clk);
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clk_disable_unprepare(exynos->clk);
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clk_disable_unprepare(exynos->clk);
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return ret;
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return ret;
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}
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}
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@ -193,6 +203,7 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
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platform_device_unregister(exynos->usb2_phy);
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platform_device_unregister(exynos->usb2_phy);
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platform_device_unregister(exynos->usb3_phy);
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platform_device_unregister(exynos->usb3_phy);
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clk_disable_unprepare(exynos->susp_clk);
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clk_disable_unprepare(exynos->clk);
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clk_disable_unprepare(exynos->clk);
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regulator_disable(exynos->vdd33);
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regulator_disable(exynos->vdd33);
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