MIPS: uasm: add sync instruction
This patch allows use of the sync instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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@ -141,6 +141,7 @@ Ip_u2u1u3(_sra);
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Ip_u2u1u3(_srl);
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Ip_u3u1u2(_subu);
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Ip_u2s3u1(_sw);
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Ip_u1(_sync);
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Ip_u1(_syscall);
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Ip_0(_tlbp);
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Ip_0(_tlbr);
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@ -99,6 +99,7 @@ static struct insn insn_table_MM[] = {
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{ insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD },
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{ insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD },
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{ insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
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{ insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS },
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{ insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 },
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{ insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },
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{ insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },
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@ -107,6 +107,7 @@ static struct insn insn_table[] = {
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{ insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
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{ insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
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{ insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE },
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{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
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{ insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
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{ insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
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@ -53,8 +53,8 @@ enum opcode {
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insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
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insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,
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insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
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insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor,
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insn_xori,
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insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr,
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insn_xor, insn_xori,
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};
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struct insn {
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@ -271,6 +271,7 @@ I_u2u1u3(_srl)
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I_u2u1u3(_rotr)
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I_u3u1u2(_subu)
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I_u2s3u1(_sw)
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I_u1(_sync)
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I_0(_tlbp)
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I_0(_tlbr)
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I_0(_tlbwi)
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