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[POWERPC] QE: change qe_setbrg() to take an enum qe_clock instead of an integer 

qe_setbrg() currently takes an integer to indicate the BRG number.  Change that
to take an enum qe_clock instead, since this enum is intended to represent
clock sources.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi 2007-11-29 17:26:30 -06:00 committed by Kumar Gala
parent c5eeb55999
commit 7264ec4454
2 changed files with 56 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/powerpc/sysdev/qe_lib/qe.c
View File

@ -167,19 +167,20 @@ unsigned int get_brg_clk(void)
/* Program the BRG to the given sampling rate and multiplier
*
* @brg: the BRG, 1-16
* @brg: the BRG, QE_BRG1 - QE_BRG16
* @rate: the desired sampling rate
* @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
* GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
* then 'multiplier' should be 8.
*
* Also note that the value programmed into the BRGC register must be even.
*/
void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier)
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
{
u32 divisor, tempval;
u32 div16 = 0;
if ((brg < QE_BRG1) || (brg > QE_BRG16))
return -EINVAL;
divisor = get_brg_clk() / (rate * multiplier);
if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
@ -196,8 +197,11 @@ void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier)
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
QE_BRGC_ENABLE | div16;
out_be32(&qe_immr->brg.brgc[brg - 1], tempval);
out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
return 0;
}
EXPORT_SYMBOL(qe_setbrg);
/* Initialize SNUMs (thread serial numbers) according to
* QE Module Control chapter, SNUM table

94
include/asm-powerpc/qe.h
View File

@ -28,6 +28,52 @@
#define MEM_PART_SECONDARY 1
#define MEM_PART_MURAM 2
/* Clocks and BRGs */
enum qe_clock {
QE_CLK_NONE = 0,
QE_BRG1, /* Baud Rate Generator 1 */
QE_BRG2, /* Baud Rate Generator 2 */
QE_BRG3, /* Baud Rate Generator 3 */
QE_BRG4, /* Baud Rate Generator 4 */
QE_BRG5, /* Baud Rate Generator 5 */
QE_BRG6, /* Baud Rate Generator 6 */
QE_BRG7, /* Baud Rate Generator 7 */
QE_BRG8, /* Baud Rate Generator 8 */
QE_BRG9, /* Baud Rate Generator 9 */
QE_BRG10, /* Baud Rate Generator 10 */
QE_BRG11, /* Baud Rate Generator 11 */
QE_BRG12, /* Baud Rate Generator 12 */
QE_BRG13, /* Baud Rate Generator 13 */
QE_BRG14, /* Baud Rate Generator 14 */
QE_BRG15, /* Baud Rate Generator 15 */
QE_BRG16, /* Baud Rate Generator 16 */
QE_CLK1, /* Clock 1 */
QE_CLK2, /* Clock 2 */
QE_CLK3, /* Clock 3 */
QE_CLK4, /* Clock 4 */
QE_CLK5, /* Clock 5 */
QE_CLK6, /* Clock 6 */
QE_CLK7, /* Clock 7 */
QE_CLK8, /* Clock 8 */
QE_CLK9, /* Clock 9 */
QE_CLK10, /* Clock 10 */
QE_CLK11, /* Clock 11 */
QE_CLK12, /* Clock 12 */
QE_CLK13, /* Clock 13 */
QE_CLK14, /* Clock 14 */
QE_CLK15, /* Clock 15 */
QE_CLK16, /* Clock 16 */
QE_CLK17, /* Clock 17 */
QE_CLK18, /* Clock 18 */
QE_CLK19, /* Clock 19 */
QE_CLK20, /* Clock 20 */
QE_CLK21, /* Clock 21 */
QE_CLK22, /* Clock 22 */
QE_CLK23, /* Clock 23 */
QE_CLK24, /* Clock 24 */
QE_CLK_DUMMY
};
/* Export QE common operations */
extern void qe_reset(void);
extern int par_io_init(struct device_node *np);
@ -38,7 +84,7 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
/* QE internal API */
int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier);
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
unsigned long qe_muram_alloc(int size, int align);
@ -129,52 +175,6 @@ enum comm_dir {
COMM_DIR_RX_AND_TX = 3
};
/* Clocks and BRGs */
enum qe_clock {
QE_CLK_NONE = 0,
QE_BRG1, /* Baud Rate Generator 1 */
QE_BRG2, /* Baud Rate Generator 2 */
QE_BRG3, /* Baud Rate Generator 3 */
QE_BRG4, /* Baud Rate Generator 4 */
QE_BRG5, /* Baud Rate Generator 5 */
QE_BRG6, /* Baud Rate Generator 6 */
QE_BRG7, /* Baud Rate Generator 7 */
QE_BRG8, /* Baud Rate Generator 8 */
QE_BRG9, /* Baud Rate Generator 9 */
QE_BRG10, /* Baud Rate Generator 10 */
QE_BRG11, /* Baud Rate Generator 11 */
QE_BRG12, /* Baud Rate Generator 12 */
QE_BRG13, /* Baud Rate Generator 13 */
QE_BRG14, /* Baud Rate Generator 14 */
QE_BRG15, /* Baud Rate Generator 15 */
QE_BRG16, /* Baud Rate Generator 16 */
QE_CLK1, /* Clock 1 */
QE_CLK2, /* Clock 2 */
QE_CLK3, /* Clock 3 */
QE_CLK4, /* Clock 4 */
QE_CLK5, /* Clock 5 */
QE_CLK6, /* Clock 6 */
QE_CLK7, /* Clock 7 */
QE_CLK8, /* Clock 8 */
QE_CLK9, /* Clock 9 */
QE_CLK10, /* Clock 10 */
QE_CLK11, /* Clock 11 */
QE_CLK12, /* Clock 12 */
QE_CLK13, /* Clock 13 */
QE_CLK14, /* Clock 14 */
QE_CLK15, /* Clock 15 */
QE_CLK16, /* Clock 16 */
QE_CLK17, /* Clock 17 */
QE_CLK18, /* Clock 18 */
QE_CLK19, /* Clock 19 */
QE_CLK20, /* Clock 20 */
QE_CLK21, /* Clock 21 */
QE_CLK22, /* Clock 22 */
QE_CLK23, /* Clock 23 */
QE_CLK24, /* Clock 24 */
QE_CLK_DUMMY,
};
/* QE CMXUCR Registers.
* There are two UCCs represented in each of the four CMXUCR registers.
* These values are for the UCC in the LSBs