Merge branches 'sh/intc-extension', 'sh/dmaengine', 'sh/serial-dma' and 'sh/clkfwk'
Conflicts: arch/sh/kernel/cpu/clock.c Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
commit
720fcb36ac
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@ -0,0 +1,35 @@
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||||||
|
/*
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||||||
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* arch/sh/include/asm/clkdev.h
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*
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* Cloned from arch/arm/include/asm/clkdev.h:
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|
*
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|
* Copyright (C) 2008 Russell King.
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*
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||||||
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* This program is free software; you can redistribute it and/or modify
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||||||
|
* it under the terms of the GNU General Public License version 2 as
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||||||
|
* published by the Free Software Foundation.
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||||||
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*
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* Helper for the clk API to assist looking up a struct clk.
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|
*/
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#ifndef __ASM_CLKDEV_H
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#define __ASM_CLKDEV_H
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struct clk;
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struct clk_lookup {
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struct list_head node;
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const char *dev_id;
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const char *con_id;
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struct clk *clk;
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};
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struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
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const char *dev_fmt, ...);
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void clkdev_add(struct clk_lookup *cl);
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void clkdev_drop(struct clk_lookup *cl);
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void clkdev_add_table(struct clk_lookup *, size_t);
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int clk_add_alias(const char *, const char *, char *, struct device *);
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#endif
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@ -45,13 +45,6 @@ struct clk {
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struct cpufreq_frequency_table *freq_table;
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struct cpufreq_frequency_table *freq_table;
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};
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};
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struct clk_lookup {
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struct list_head node;
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const char *dev_id;
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const char *con_id;
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struct clk *clk;
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};
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#define CLK_ENABLE_ON_INIT (1 << 0)
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#define CLK_ENABLE_ON_INIT (1 << 0)
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/* Should be defined by processor-specific code */
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/* Should be defined by processor-specific code */
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|
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@ -10,14 +10,9 @@
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#ifndef ASM_DMAENGINE_H
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#ifndef ASM_DMAENGINE_H
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#define ASM_DMAENGINE_H
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#define ASM_DMAENGINE_H
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#include <linux/dmaengine.h>
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#include <linux/sh_dma.h>
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#include <linux/list.h>
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#include <asm/dma-register.h>
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enum {
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#define SH_DMAC_MAX_CHANNELS 6
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enum sh_dmae_slave_chan_id {
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SHDMA_SLAVE_SCIF0_TX,
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SHDMA_SLAVE_SCIF0_TX,
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SHDMA_SLAVE_SCIF0_RX,
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SHDMA_SLAVE_SCIF0_RX,
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SHDMA_SLAVE_SCIF1_TX,
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SHDMA_SLAVE_SCIF1_TX,
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@ -34,60 +29,6 @@ enum sh_dmae_slave_chan_id {
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SHDMA_SLAVE_SIUA_RX,
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SHDMA_SLAVE_SIUA_RX,
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SHDMA_SLAVE_SIUB_TX,
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SHDMA_SLAVE_SIUB_TX,
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SHDMA_SLAVE_SIUB_RX,
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SHDMA_SLAVE_SIUB_RX,
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SHDMA_SLAVE_NUMBER, /* Must stay last */
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};
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struct sh_dmae_slave_config {
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enum sh_dmae_slave_chan_id slave_id;
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dma_addr_t addr;
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u32 chcr;
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char mid_rid;
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};
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|
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struct sh_dmae_channel {
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unsigned int offset;
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unsigned int dmars;
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unsigned int dmars_bit;
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};
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|
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struct sh_dmae_pdata {
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|
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struct sh_dmae_slave_config *slave;
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|
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int slave_num;
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|
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struct sh_dmae_channel *channel;
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|
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int channel_num;
|
|
||||||
unsigned int ts_low_shift;
|
|
||||||
unsigned int ts_low_mask;
|
|
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unsigned int ts_high_shift;
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unsigned int ts_high_mask;
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|
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unsigned int *ts_shift;
|
|
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int ts_shift_num;
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u16 dmaor_init;
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|
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};
|
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|
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struct device;
|
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|
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/* Used by slave DMA clients to request DMA to/from a specific peripheral */
|
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struct sh_dmae_slave {
|
|
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enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */
|
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struct device *dma_dev; /* Set by the platform */
|
|
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struct sh_dmae_slave_config *config; /* Set by the driver */
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|
||||||
};
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|
||||||
|
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||||||
struct sh_dmae_regs {
|
|
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u32 sar; /* SAR / source address */
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|
||||||
u32 dar; /* DAR / destination address */
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|
||||||
u32 tcr; /* TCR / transfer count */
|
|
||||||
};
|
|
||||||
|
|
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struct sh_desc {
|
|
||||||
struct sh_dmae_regs hw;
|
|
||||||
struct list_head node;
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|
||||||
struct dma_async_tx_descriptor async_tx;
|
|
||||||
enum dma_data_direction direction;
|
|
||||||
dma_cookie_t cookie;
|
|
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size_t partial;
|
|
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int chunks;
|
|
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int mark;
|
|
||||||
};
|
};
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|
|
||||||
#endif
|
#endif
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|
|
|
@ -17,10 +17,10 @@ struct device;
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|
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struct siu_platform {
|
struct siu_platform {
|
||||||
struct device *dma_dev;
|
struct device *dma_dev;
|
||||||
enum sh_dmae_slave_chan_id dma_slave_tx_a;
|
unsigned int dma_slave_tx_a;
|
||||||
enum sh_dmae_slave_chan_id dma_slave_rx_a;
|
unsigned int dma_slave_rx_a;
|
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enum sh_dmae_slave_chan_id dma_slave_tx_b;
|
unsigned int dma_slave_tx_b;
|
||||||
enum sh_dmae_slave_chan_id dma_slave_rx_b;
|
unsigned int dma_slave_rx_b;
|
||||||
};
|
};
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|
||||||
#endif /* ASM_SIU_H */
|
#endif /* ASM_SIU_H */
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||||||
|
|
|
@ -11,7 +11,7 @@ endif
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|
|
||||||
CFLAGS_REMOVE_return_address.o = -pg
|
CFLAGS_REMOVE_return_address.o = -pg
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|
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obj-y := debugtraps.o dma-nommu.o dumpstack.o \
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obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \
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idle.o io.o io_generic.o irq.o \
|
idle.o io.o io_generic.o irq.o \
|
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irq_$(BITS).o machvec.o nmi_debug.o process.o \
|
irq_$(BITS).o machvec.o nmi_debug.o process.o \
|
||||||
process_$(BITS).o ptrace_$(BITS).o \
|
process_$(BITS).o ptrace_$(BITS).o \
|
||||||
|
|
|
@ -0,0 +1,169 @@
|
||||||
|
/*
|
||||||
|
* arch/sh/kernel/clkdev.c
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||||||
|
*
|
||||||
|
* Cloned from arch/arm/common/clkdev.c:
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008 Russell King.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* Helper for the clk API to assist looking up a struct clk.
|
||||||
|
*/
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||||||
|
#include <linux/module.h>
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#include <linux/kernel.h>
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|
#include <linux/device.h>
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|
#include <linux/list.h>
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|
#include <linux/errno.h>
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|
#include <linux/err.h>
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|
#include <linux/string.h>
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|
#include <linux/mutex.h>
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|
#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <asm/clock.h>
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#include <asm/clkdev.h>
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|
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|
static LIST_HEAD(clocks);
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|
static DEFINE_MUTEX(clocks_mutex);
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|
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||||||
|
/*
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||||||
|
* Find the correct struct clk for the device and connection ID.
|
||||||
|
* We do slightly fuzzy matching here:
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||||||
|
* An entry with a NULL ID is assumed to be a wildcard.
|
||||||
|
* If an entry has a device ID, it must match
|
||||||
|
* If an entry has a connection ID, it must match
|
||||||
|
* Then we take the most specific entry - with the following
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||||||
|
* order of precidence: dev+con > dev only > con only.
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||||||
|
*/
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||||||
|
static struct clk *clk_find(const char *dev_id, const char *con_id)
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|
{
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|
struct clk_lookup *p;
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|
struct clk *clk = NULL;
|
||||||
|
int match, best = 0;
|
||||||
|
|
||||||
|
list_for_each_entry(p, &clocks, node) {
|
||||||
|
match = 0;
|
||||||
|
if (p->dev_id) {
|
||||||
|
if (!dev_id || strcmp(p->dev_id, dev_id))
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|
continue;
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|
match += 2;
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||||||
|
}
|
||||||
|
if (p->con_id) {
|
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|
if (!con_id || strcmp(p->con_id, con_id))
|
||||||
|
continue;
|
||||||
|
match += 1;
|
||||||
|
}
|
||||||
|
if (match == 0)
|
||||||
|
continue;
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||||||
|
|
||||||
|
if (match > best) {
|
||||||
|
clk = p->clk;
|
||||||
|
best = match;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return clk;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct clk *clk_get_sys(const char *dev_id, const char *con_id)
|
||||||
|
{
|
||||||
|
struct clk *clk;
|
||||||
|
|
||||||
|
mutex_lock(&clocks_mutex);
|
||||||
|
clk = clk_find(dev_id, con_id);
|
||||||
|
mutex_unlock(&clocks_mutex);
|
||||||
|
|
||||||
|
return clk ? clk : ERR_PTR(-ENOENT);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(clk_get_sys);
|
||||||
|
|
||||||
|
void clkdev_add(struct clk_lookup *cl)
|
||||||
|
{
|
||||||
|
mutex_lock(&clocks_mutex);
|
||||||
|
list_add_tail(&cl->node, &clocks);
|
||||||
|
mutex_unlock(&clocks_mutex);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(clkdev_add);
|
||||||
|
|
||||||
|
void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
|
||||||
|
{
|
||||||
|
mutex_lock(&clocks_mutex);
|
||||||
|
while (num--) {
|
||||||
|
list_add_tail(&cl->node, &clocks);
|
||||||
|
cl++;
|
||||||
|
}
|
||||||
|
mutex_unlock(&clocks_mutex);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define MAX_DEV_ID 20
|
||||||
|
#define MAX_CON_ID 16
|
||||||
|
|
||||||
|
struct clk_lookup_alloc {
|
||||||
|
struct clk_lookup cl;
|
||||||
|
char dev_id[MAX_DEV_ID];
|
||||||
|
char con_id[MAX_CON_ID];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct clk_lookup * __init_refok
|
||||||
|
clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
|
||||||
|
{
|
||||||
|
struct clk_lookup_alloc *cla;
|
||||||
|
|
||||||
|
if (!slab_is_available())
|
||||||
|
cla = alloc_bootmem_low_pages(sizeof(*cla));
|
||||||
|
else
|
||||||
|
cla = kzalloc(sizeof(*cla), GFP_KERNEL);
|
||||||
|
|
||||||
|
if (!cla)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
cla->cl.clk = clk;
|
||||||
|
if (con_id) {
|
||||||
|
strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
|
||||||
|
cla->cl.con_id = cla->con_id;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dev_fmt) {
|
||||||
|
va_list ap;
|
||||||
|
|
||||||
|
va_start(ap, dev_fmt);
|
||||||
|
vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
|
||||||
|
cla->cl.dev_id = cla->dev_id;
|
||||||
|
va_end(ap);
|
||||||
|
}
|
||||||
|
|
||||||
|
return &cla->cl;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(clkdev_alloc);
|
||||||
|
|
||||||
|
int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
|
||||||
|
struct device *dev)
|
||||||
|
{
|
||||||
|
struct clk *r = clk_get(dev, id);
|
||||||
|
struct clk_lookup *l;
|
||||||
|
|
||||||
|
if (IS_ERR(r))
|
||||||
|
return PTR_ERR(r);
|
||||||
|
|
||||||
|
l = clkdev_alloc(r, alias, alias_dev_name);
|
||||||
|
clk_put(r);
|
||||||
|
if (!l)
|
||||||
|
return -ENODEV;
|
||||||
|
clkdev_add(l);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(clk_add_alias);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* clkdev_drop - remove a clock dynamically allocated
|
||||||
|
*/
|
||||||
|
void clkdev_drop(struct clk_lookup *cl)
|
||||||
|
{
|
||||||
|
mutex_lock(&clocks_mutex);
|
||||||
|
list_del(&cl->node);
|
||||||
|
mutex_unlock(&clocks_mutex);
|
||||||
|
kfree(cl);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(clkdev_drop);
|
|
@ -338,6 +338,11 @@ int __init __deprecated cpg_clk_init(void)
|
||||||
ret |= clk_register(clk);
|
ret |= clk_register(clk);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
|
||||||
|
clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
|
||||||
|
clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
|
||||||
|
clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -10,10 +10,6 @@
|
||||||
*
|
*
|
||||||
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
|
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
|
||||||
*
|
*
|
||||||
* With clkdev bits:
|
|
||||||
*
|
|
||||||
* Copyright (C) 2008 Russell King.
|
|
||||||
*
|
|
||||||
* This file is subject to the terms and conditions of the GNU General Public
|
* This file is subject to the terms and conditions of the GNU General Public
|
||||||
* License. See the file "COPYING" in the main directory of this archive
|
* License. See the file "COPYING" in the main directory of this archive
|
||||||
* for more details.
|
* for more details.
|
||||||
|
@ -30,6 +26,7 @@
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/debugfs.h>
|
#include <linux/debugfs.h>
|
||||||
#include <linux/cpufreq.h>
|
#include <linux/cpufreq.h>
|
||||||
|
#include <linux/clk.h>
|
||||||
#include <asm/clock.h>
|
#include <asm/clock.h>
|
||||||
#include <asm/machvec.h>
|
#include <asm/machvec.h>
|
||||||
|
|
||||||
|
@ -397,56 +394,6 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(clk_round_rate);
|
EXPORT_SYMBOL_GPL(clk_round_rate);
|
||||||
|
|
||||||
/*
|
|
||||||
* Find the correct struct clk for the device and connection ID.
|
|
||||||
* We do slightly fuzzy matching here:
|
|
||||||
* An entry with a NULL ID is assumed to be a wildcard.
|
|
||||||
* If an entry has a device ID, it must match
|
|
||||||
* If an entry has a connection ID, it must match
|
|
||||||
* Then we take the most specific entry - with the following
|
|
||||||
* order of precedence: dev+con > dev only > con only.
|
|
||||||
*/
|
|
||||||
static struct clk *clk_find(const char *dev_id, const char *con_id)
|
|
||||||
{
|
|
||||||
struct clk_lookup *p;
|
|
||||||
struct clk *clk = NULL;
|
|
||||||
int match, best = 0;
|
|
||||||
|
|
||||||
list_for_each_entry(p, &clock_list, node) {
|
|
||||||
match = 0;
|
|
||||||
if (p->dev_id) {
|
|
||||||
if (!dev_id || strcmp(p->dev_id, dev_id))
|
|
||||||
continue;
|
|
||||||
match += 2;
|
|
||||||
}
|
|
||||||
if (p->con_id) {
|
|
||||||
if (!con_id || strcmp(p->con_id, con_id))
|
|
||||||
continue;
|
|
||||||
match += 1;
|
|
||||||
}
|
|
||||||
if (match == 0)
|
|
||||||
continue;
|
|
||||||
|
|
||||||
if (match > best) {
|
|
||||||
clk = p->clk;
|
|
||||||
best = match;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return clk;
|
|
||||||
}
|
|
||||||
|
|
||||||
struct clk *clk_get_sys(const char *dev_id, const char *con_id)
|
|
||||||
{
|
|
||||||
struct clk *clk;
|
|
||||||
|
|
||||||
mutex_lock(&clock_list_sem);
|
|
||||||
clk = clk_find(dev_id, con_id);
|
|
||||||
mutex_unlock(&clock_list_sem);
|
|
||||||
|
|
||||||
return clk ? clk : ERR_PTR(-ENOENT);
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL_GPL(clk_get_sys);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Returns a clock. Note that we first try to use device id on the bus
|
* Returns a clock. Note that we first try to use device id on the bus
|
||||||
* and clock name. If this fails, we try to use clock name only.
|
* and clock name. If this fails, we try to use clock name only.
|
||||||
|
|
|
@ -128,17 +128,14 @@ static struct platform_device eth_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt0_platform_data = {
|
static struct sh_timer_config cmt0_platform_data = {
|
||||||
.name = "CMT0",
|
|
||||||
.channel_offset = 0x02,
|
.channel_offset = 0x02,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt0_resources[] = {
|
static struct resource cmt0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT0",
|
|
||||||
.start = 0xf84a0072,
|
.start = 0xf84a0072,
|
||||||
.end = 0xf84a0077,
|
.end = 0xf84a0077,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -160,17 +157,14 @@ static struct platform_device cmt0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt1_platform_data = {
|
static struct sh_timer_config cmt1_platform_data = {
|
||||||
.name = "CMT1",
|
|
||||||
.channel_offset = 0x08,
|
.channel_offset = 0x08,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt1_resources[] = {
|
static struct resource cmt1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT1",
|
|
||||||
.start = 0xf84a0078,
|
.start = 0xf84a0078,
|
||||||
.end = 0xf84a007d,
|
.end = 0xf84a007d,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -115,16 +115,13 @@ static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
|
||||||
mask_registers, prio_registers, NULL);
|
mask_registers, prio_registers, NULL);
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_0_platform_data = {
|
static struct sh_timer_config mtu2_0_platform_data = {
|
||||||
.name = "MTU2_0",
|
|
||||||
.channel_offset = -0x80,
|
.channel_offset = -0x80,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_0_resources[] = {
|
static struct resource mtu2_0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_0",
|
|
||||||
.start = 0xff801300,
|
.start = 0xff801300,
|
||||||
.end = 0xff801326,
|
.end = 0xff801326,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -146,16 +143,13 @@ static struct platform_device mtu2_0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_1_platform_data = {
|
static struct sh_timer_config mtu2_1_platform_data = {
|
||||||
.name = "MTU2_1",
|
|
||||||
.channel_offset = -0x100,
|
.channel_offset = -0x100,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_1_resources[] = {
|
static struct resource mtu2_1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_1",
|
|
||||||
.start = 0xff801380,
|
.start = 0xff801380,
|
||||||
.end = 0xff801390,
|
.end = 0xff801390,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -177,16 +171,13 @@ static struct platform_device mtu2_1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_2_platform_data = {
|
static struct sh_timer_config mtu2_2_platform_data = {
|
||||||
.name = "MTU2_2",
|
|
||||||
.channel_offset = 0x80,
|
.channel_offset = 0x80,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_2_resources[] = {
|
static struct resource mtu2_2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_2",
|
|
||||||
.start = 0xff801000,
|
.start = 0xff801000,
|
||||||
.end = 0xff80100a,
|
.end = 0xff80100a,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -318,16 +318,13 @@ static struct platform_device rtc_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_0_platform_data = {
|
static struct sh_timer_config mtu2_0_platform_data = {
|
||||||
.name = "MTU2_0",
|
|
||||||
.channel_offset = -0x80,
|
.channel_offset = -0x80,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_0_resources[] = {
|
static struct resource mtu2_0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_0",
|
|
||||||
.start = 0xfffe4300,
|
.start = 0xfffe4300,
|
||||||
.end = 0xfffe4326,
|
.end = 0xfffe4326,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -349,16 +346,13 @@ static struct platform_device mtu2_0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_1_platform_data = {
|
static struct sh_timer_config mtu2_1_platform_data = {
|
||||||
.name = "MTU2_1",
|
|
||||||
.channel_offset = -0x100,
|
.channel_offset = -0x100,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_1_resources[] = {
|
static struct resource mtu2_1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_1",
|
|
||||||
.start = 0xfffe4380,
|
.start = 0xfffe4380,
|
||||||
.end = 0xfffe4390,
|
.end = 0xfffe4390,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -380,16 +374,13 @@ static struct platform_device mtu2_1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_2_platform_data = {
|
static struct sh_timer_config mtu2_2_platform_data = {
|
||||||
.name = "MTU2_2",
|
|
||||||
.channel_offset = 0x80,
|
.channel_offset = 0x80,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_2_resources[] = {
|
static struct resource mtu2_2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_2",
|
|
||||||
.start = 0xfffe4000,
|
.start = 0xfffe4000,
|
||||||
.end = 0xfffe400a,
|
.end = 0xfffe400a,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -234,17 +234,14 @@ static struct platform_device scif3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt0_platform_data = {
|
static struct sh_timer_config cmt0_platform_data = {
|
||||||
.name = "CMT0",
|
|
||||||
.channel_offset = 0x02,
|
.channel_offset = 0x02,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt0_resources[] = {
|
static struct resource cmt0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT0",
|
|
||||||
.start = 0xfffec002,
|
.start = 0xfffec002,
|
||||||
.end = 0xfffec007,
|
.end = 0xfffec007,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -266,17 +263,14 @@ static struct platform_device cmt0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt1_platform_data = {
|
static struct sh_timer_config cmt1_platform_data = {
|
||||||
.name = "CMT1",
|
|
||||||
.channel_offset = 0x08,
|
.channel_offset = 0x08,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt1_resources[] = {
|
static struct resource cmt1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT1",
|
|
||||||
.start = 0xfffec008,
|
.start = 0xfffec008,
|
||||||
.end = 0xfffec00d,
|
.end = 0xfffec00d,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -298,16 +292,13 @@ static struct platform_device cmt1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_0_platform_data = {
|
static struct sh_timer_config mtu2_0_platform_data = {
|
||||||
.name = "MTU2_0",
|
|
||||||
.channel_offset = -0x80,
|
.channel_offset = -0x80,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_0_resources[] = {
|
static struct resource mtu2_0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_0",
|
|
||||||
.start = 0xfffe4300,
|
.start = 0xfffe4300,
|
||||||
.end = 0xfffe4326,
|
.end = 0xfffe4326,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -329,16 +320,13 @@ static struct platform_device mtu2_0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_1_platform_data = {
|
static struct sh_timer_config mtu2_1_platform_data = {
|
||||||
.name = "MTU2_1",
|
|
||||||
.channel_offset = -0x100,
|
.channel_offset = -0x100,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_1_resources[] = {
|
static struct resource mtu2_1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_1",
|
|
||||||
.start = 0xfffe4380,
|
.start = 0xfffe4380,
|
||||||
.end = 0xfffe4390,
|
.end = 0xfffe4390,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -194,17 +194,14 @@ static struct platform_device scif3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt0_platform_data = {
|
static struct sh_timer_config cmt0_platform_data = {
|
||||||
.name = "CMT0",
|
|
||||||
.channel_offset = 0x02,
|
.channel_offset = 0x02,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt0_resources[] = {
|
static struct resource cmt0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT0",
|
|
||||||
.start = 0xfffec002,
|
.start = 0xfffec002,
|
||||||
.end = 0xfffec007,
|
.end = 0xfffec007,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -226,17 +223,14 @@ static struct platform_device cmt0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt1_platform_data = {
|
static struct sh_timer_config cmt1_platform_data = {
|
||||||
.name = "CMT1",
|
|
||||||
.channel_offset = 0x08,
|
.channel_offset = 0x08,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt1_resources[] = {
|
static struct resource cmt1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT1",
|
|
||||||
.start = 0xfffec008,
|
.start = 0xfffec008,
|
||||||
.end = 0xfffec00d,
|
.end = 0xfffec00d,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -258,16 +252,13 @@ static struct platform_device cmt1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_0_platform_data = {
|
static struct sh_timer_config mtu2_0_platform_data = {
|
||||||
.name = "MTU2_0",
|
|
||||||
.channel_offset = -0x80,
|
.channel_offset = -0x80,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_0_resources[] = {
|
static struct resource mtu2_0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_0",
|
|
||||||
.start = 0xfffe4300,
|
.start = 0xfffe4300,
|
||||||
.end = 0xfffe4326,
|
.end = 0xfffe4326,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -289,16 +280,13 @@ static struct platform_device mtu2_0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_1_platform_data = {
|
static struct sh_timer_config mtu2_1_platform_data = {
|
||||||
.name = "MTU2_1",
|
|
||||||
.channel_offset = -0x100,
|
.channel_offset = -0x100,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_1_resources[] = {
|
static struct resource mtu2_1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_1",
|
|
||||||
.start = 0xfffe4380,
|
.start = 0xfffe4380,
|
||||||
.end = 0xfffe4390,
|
.end = 0xfffe4390,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -320,16 +308,13 @@ static struct platform_device mtu2_1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config mtu2_2_platform_data = {
|
static struct sh_timer_config mtu2_2_platform_data = {
|
||||||
.name = "MTU2_2",
|
|
||||||
.channel_offset = 0x80,
|
.channel_offset = 0x80,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource mtu2_2_resources[] = {
|
static struct resource mtu2_2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "MTU2_2",
|
|
||||||
.start = 0xfffe4000,
|
.start = 0xfffe4000,
|
||||||
.end = 0xfffe400a,
|
.end = 0xfffe400a,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -124,16 +124,13 @@ static struct platform_device rtc_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x02,
|
.channel_offset = 0x02,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xfffffe94,
|
.start = 0xfffffe94,
|
||||||
.end = 0xfffffe9f,
|
.end = 0xfffffe9f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -155,16 +152,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0xe,
|
.channel_offset = 0xe,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xfffffea0,
|
.start = 0xfffffea0,
|
||||||
.end = 0xfffffeab,
|
.end = 0xfffffeab,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -186,15 +180,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1a,
|
.channel_offset = 0x1a,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xfffffeac,
|
.start = 0xfffffeac,
|
||||||
.end = 0xfffffebb,
|
.end = 0xfffffebb,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -157,16 +157,13 @@ static struct platform_device scif2_device = {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x02,
|
.channel_offset = 0x02,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xfffffe94,
|
.start = 0xfffffe94,
|
||||||
.end = 0xfffffe9f,
|
.end = 0xfffffe9f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -188,16 +185,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0xe,
|
.channel_offset = 0xe,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xfffffea0,
|
.start = 0xfffffea0,
|
||||||
.end = 0xfffffeab,
|
.end = 0xfffffeab,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -219,15 +213,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1a,
|
.channel_offset = 0x1a,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xfffffeac,
|
.start = 0xfffffeac,
|
||||||
.end = 0xfffffebb,
|
.end = 0xfffffebb,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -127,16 +127,13 @@ static struct platform_device scif1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x02,
|
.channel_offset = 0x02,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xa412fe94,
|
.start = 0xa412fe94,
|
||||||
.end = 0xa412fe9f,
|
.end = 0xa412fe9f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -158,16 +155,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0xe,
|
.channel_offset = 0xe,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xa412fea0,
|
.start = 0xa412fea0,
|
||||||
.end = 0xa412feab,
|
.end = 0xa412feab,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -189,15 +183,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1a,
|
.channel_offset = 0x1a,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xa412feac,
|
.start = 0xa412feac,
|
||||||
.end = 0xa412feb5,
|
.end = 0xa412feb5,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -130,17 +130,14 @@ static struct platform_device usbf_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt0_platform_data = {
|
static struct sh_timer_config cmt0_platform_data = {
|
||||||
.name = "CMT0",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 125,
|
.clocksource_rating = 125,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt0_resources[] = {
|
static struct resource cmt0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT0",
|
|
||||||
.start = 0x044a0010,
|
.start = 0x044a0010,
|
||||||
.end = 0x044a001b,
|
.end = 0x044a001b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -162,15 +159,12 @@ static struct platform_device cmt0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt1_platform_data = {
|
static struct sh_timer_config cmt1_platform_data = {
|
||||||
.name = "CMT1",
|
|
||||||
.channel_offset = 0x20,
|
.channel_offset = 0x20,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt1_resources[] = {
|
static struct resource cmt1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT1",
|
|
||||||
.start = 0x044a0020,
|
.start = 0x044a0020,
|
||||||
.end = 0x044a002b,
|
.end = 0x044a002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -192,15 +186,12 @@ static struct platform_device cmt1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt2_platform_data = {
|
static struct sh_timer_config cmt2_platform_data = {
|
||||||
.name = "CMT2",
|
|
||||||
.channel_offset = 0x30,
|
.channel_offset = 0x30,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt2_resources[] = {
|
static struct resource cmt2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT2",
|
|
||||||
.start = 0x044a0030,
|
.start = 0x044a0030,
|
||||||
.end = 0x044a003b,
|
.end = 0x044a003b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -222,15 +213,12 @@ static struct platform_device cmt2_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt3_platform_data = {
|
static struct sh_timer_config cmt3_platform_data = {
|
||||||
.name = "CMT3",
|
|
||||||
.channel_offset = 0x40,
|
.channel_offset = 0x40,
|
||||||
.timer_bit = 3,
|
.timer_bit = 3,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt3_resources[] = {
|
static struct resource cmt3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT3",
|
|
||||||
.start = 0x044a0040,
|
.start = 0x044a0040,
|
||||||
.end = 0x044a004b,
|
.end = 0x044a004b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -252,15 +240,12 @@ static struct platform_device cmt3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt4_platform_data = {
|
static struct sh_timer_config cmt4_platform_data = {
|
||||||
.name = "CMT4",
|
|
||||||
.channel_offset = 0x50,
|
.channel_offset = 0x50,
|
||||||
.timer_bit = 4,
|
.timer_bit = 4,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt4_resources[] = {
|
static struct resource cmt4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT4",
|
|
||||||
.start = 0x044a0050,
|
.start = 0x044a0050,
|
||||||
.end = 0x044a005b,
|
.end = 0x044a005b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -282,16 +267,13 @@ static struct platform_device cmt4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x02,
|
.channel_offset = 0x02,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xa412fe94,
|
.start = 0xa412fe94,
|
||||||
.end = 0xa412fe9f,
|
.end = 0xa412fe9f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -313,16 +295,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0xe,
|
.channel_offset = 0xe,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xa412fea0,
|
.start = 0xa412fea0,
|
||||||
.end = 0xa412feab,
|
.end = 0xa412feab,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -344,15 +323,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1a,
|
.channel_offset = 0x1a,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xa412feac,
|
.start = 0xa412feac,
|
||||||
.end = 0xa412feb5,
|
.end = 0xa412feb5,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -31,16 +31,13 @@ static struct platform_device scif0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -62,16 +59,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -93,15 +87,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002f,
|
.end = 0xffd8002f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -66,16 +66,13 @@ static struct platform_device scif1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -97,16 +94,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -128,15 +122,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002f,
|
.end = 0xffd8002f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -163,15 +154,12 @@ static struct platform_device tmu2_device = {
|
||||||
defined(CONFIG_CPU_SUBTYPE_SH7751R)
|
defined(CONFIG_CPU_SUBTYPE_SH7751R)
|
||||||
|
|
||||||
static struct sh_timer_config tmu3_platform_data = {
|
static struct sh_timer_config tmu3_platform_data = {
|
||||||
.name = "TMU3",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu3_resources[] = {
|
static struct resource tmu3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU3",
|
|
||||||
.start = 0xfe100008,
|
.start = 0xfe100008,
|
||||||
.end = 0xfe100013,
|
.end = 0xfe100013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -193,15 +181,12 @@ static struct platform_device tmu3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu4_platform_data = {
|
static struct sh_timer_config tmu4_platform_data = {
|
||||||
.name = "TMU4",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu4_resources[] = {
|
static struct resource tmu4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU4",
|
|
||||||
.start = 0xfe100014,
|
.start = 0xfe100014,
|
||||||
.end = 0xfe10001f,
|
.end = 0xfe10001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -187,16 +187,13 @@ static struct platform_device scif3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -218,16 +215,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -249,15 +243,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002f,
|
.end = 0xffd8002f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -154,15 +154,15 @@ static struct clk mstp_clks[] = {
|
||||||
MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||||
MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
|
MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
|
||||||
MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||||
MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
||||||
MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
|
MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
|
||||||
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
|
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
|
||||||
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
||||||
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
||||||
MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
|
SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
|
||||||
MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
|
SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
|
||||||
MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
||||||
MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0),
|
SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
|
||||||
MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
|
MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
|
||||||
MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||||
MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
|
MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
|
||||||
|
|
|
@ -158,14 +158,14 @@ static struct clk mstp_clks[] = {
|
||||||
MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||||
MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
|
MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
|
||||||
MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||||
MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
|
||||||
MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
|
MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
|
||||||
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
|
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
|
||||||
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
|
||||||
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
|
||||||
MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
|
SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
|
||||||
MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
|
SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
|
||||||
MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
|
||||||
MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
|
||||||
MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
|
MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
|
||||||
|
|
||||||
|
|
|
@ -160,13 +160,13 @@ struct clk div6_clks[] = {
|
||||||
static struct clk mstp_clks[] = {
|
static struct clk mstp_clks[] = {
|
||||||
SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
|
SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
|
||||||
SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
|
SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
|
||||||
SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0),
|
SH_HWBLK_CLK("tmu_fck", -1, P_CLK, HWBLK_TMU, 0),
|
||||||
SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
|
SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
|
||||||
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
|
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
|
||||||
SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
|
SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
|
||||||
SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
|
SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
|
||||||
SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
|
SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
|
||||||
SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
|
SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
|
||||||
|
|
||||||
SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
|
SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
|
||||||
SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
|
SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
|
||||||
|
|
|
@ -21,6 +21,8 @@
|
||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
|
#include <linux/clk.h>
|
||||||
|
#include <asm/clkdev.h>
|
||||||
#include <asm/clock.h>
|
#include <asm/clock.h>
|
||||||
#include <asm/hwblk.h>
|
#include <asm/hwblk.h>
|
||||||
#include <cpu/sh7723.h>
|
#include <cpu/sh7723.h>
|
||||||
|
@ -171,18 +173,18 @@ static struct clk mstp_clks[] = {
|
||||||
SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
|
SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
|
||||||
SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
|
SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
|
||||||
SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
|
SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
|
||||||
SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0),
|
SH_HWBLK_CLK("tmu012_fck", -1, P_CLK, HWBLK_TMU0, 0),
|
||||||
SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
|
SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
|
||||||
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
|
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
|
||||||
SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
|
SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
|
||||||
SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
|
SH_HWBLK_CLK("tmu345_fck", -1, P_CLK, HWBLK_TMU1, 0),
|
||||||
SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
|
SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
|
||||||
SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
|
SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
|
||||||
SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
|
SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
|
||||||
SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
|
SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
|
||||||
SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0),
|
SH_HWBLK_CLK("sci_fck", 3, B_CLK, HWBLK_SCIF3, 0),
|
||||||
SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0),
|
SH_HWBLK_CLK("sci_fck", 4, B_CLK, HWBLK_SCIF4, 0),
|
||||||
SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0),
|
SH_HWBLK_CLK("sci_fck", 5, B_CLK, HWBLK_SCIF5, 0),
|
||||||
SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
|
SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
|
||||||
SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
|
SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
|
||||||
SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0),
|
SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0),
|
||||||
|
@ -211,6 +213,40 @@ static struct clk mstp_clks[] = {
|
||||||
SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
|
SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct clk_lookup lookups[] = {
|
||||||
|
{
|
||||||
|
/* TMU0 */
|
||||||
|
.dev_id = "sh_tmu.0",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[11], /* tmu012_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU1 */
|
||||||
|
.dev_id = "sh_tmu.1",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[11],
|
||||||
|
}, {
|
||||||
|
/* TMU2 */
|
||||||
|
.dev_id = "sh_tmu.2",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[11],
|
||||||
|
}, {
|
||||||
|
/* TMU3 */
|
||||||
|
.dev_id = "sh_tmu.3",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[15], /* tmu345_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU4 */
|
||||||
|
.dev_id = "sh_tmu.4",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[15],
|
||||||
|
}, {
|
||||||
|
/* TMU5 */
|
||||||
|
.dev_id = "sh_tmu.5",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[15],
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
int __init arch_clk_init(void)
|
int __init arch_clk_init(void)
|
||||||
{
|
{
|
||||||
int k, ret = 0;
|
int k, ret = 0;
|
||||||
|
@ -222,7 +258,9 @@ int __init arch_clk_init(void)
|
||||||
pll_clk.parent = &extal_clk;
|
pll_clk.parent = &extal_clk;
|
||||||
|
|
||||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||||
ret = clk_register(main_clks[k]);
|
ret |= clk_register(main_clks[k]);
|
||||||
|
|
||||||
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||||
|
|
||||||
if (!ret)
|
if (!ret)
|
||||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||||
|
|
|
@ -21,6 +21,8 @@
|
||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
|
#include <linux/clk.h>
|
||||||
|
#include <asm/clkdev.h>
|
||||||
#include <asm/clock.h>
|
#include <asm/clock.h>
|
||||||
#include <asm/hwblk.h>
|
#include <asm/hwblk.h>
|
||||||
#include <cpu/sh7724.h>
|
#include <cpu/sh7724.h>
|
||||||
|
@ -189,17 +191,17 @@ static struct clk mstp_clks[] = {
|
||||||
SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
|
SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
|
||||||
SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
|
SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
|
||||||
SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
|
SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
|
||||||
SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0),
|
SH_HWBLK_CLK("tmu012_fck", -1, P_CLK, HWBLK_TMU0, 0),
|
||||||
SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
|
SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
|
||||||
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
|
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
|
||||||
SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
|
SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
|
||||||
SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
|
SH_HWBLK_CLK("tmu345_fck", -1, P_CLK, HWBLK_TMU1, 0),
|
||||||
SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
|
SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
|
||||||
SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
|
SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
|
||||||
SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
|
SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
|
||||||
SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0),
|
SH_HWBLK_CLK("sci_fck", 3, B_CLK, HWBLK_SCIF3, 0),
|
||||||
SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0),
|
SH_HWBLK_CLK("sci_fck", 4, B_CLK, HWBLK_SCIF4, 0),
|
||||||
SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0),
|
SH_HWBLK_CLK("sci_fck", 5, B_CLK, HWBLK_SCIF5, 0),
|
||||||
SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
|
SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
|
||||||
SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
|
SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
|
||||||
|
|
||||||
|
@ -233,6 +235,40 @@ static struct clk mstp_clks[] = {
|
||||||
SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
|
SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct clk_lookup lookups[] = {
|
||||||
|
{
|
||||||
|
/* TMU0 */
|
||||||
|
.dev_id = "sh_tmu.0",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[12], /* tmu012_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU1 */
|
||||||
|
.dev_id = "sh_tmu.1",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[12],
|
||||||
|
}, {
|
||||||
|
/* TMU2 */
|
||||||
|
.dev_id = "sh_tmu.2",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[12],
|
||||||
|
}, {
|
||||||
|
/* TMU3 */
|
||||||
|
.dev_id = "sh_tmu.3",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[16], /* tmu345_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU4 */
|
||||||
|
.dev_id = "sh_tmu.4",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[16],
|
||||||
|
}, {
|
||||||
|
/* TMU5 */
|
||||||
|
.dev_id = "sh_tmu.5",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[16],
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
int __init arch_clk_init(void)
|
int __init arch_clk_init(void)
|
||||||
{
|
{
|
||||||
int k, ret = 0;
|
int k, ret = 0;
|
||||||
|
@ -246,6 +282,8 @@ int __init arch_clk_init(void)
|
||||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||||
ret = clk_register(main_clks[k]);
|
ret = clk_register(main_clks[k]);
|
||||||
|
|
||||||
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||||
|
|
||||||
if (!ret)
|
if (!ret)
|
||||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||||
|
|
||||||
|
|
|
@ -3,7 +3,7 @@
|
||||||
*
|
*
|
||||||
* SH7785 support for the clock framework
|
* SH7785 support for the clock framework
|
||||||
*
|
*
|
||||||
* Copyright (C) 2007 - 2009 Paul Mundt
|
* Copyright (C) 2007 - 2010 Paul Mundt
|
||||||
*
|
*
|
||||||
* This file is subject to the terms and conditions of the GNU General Public
|
* This file is subject to the terms and conditions of the GNU General Public
|
||||||
* License. See the file "COPYING" in the main directory of this archive
|
* License. See the file "COPYING" in the main directory of this archive
|
||||||
|
@ -14,6 +14,7 @@
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
#include <linux/cpufreq.h>
|
#include <linux/cpufreq.h>
|
||||||
|
#include <asm/clkdev.h>
|
||||||
#include <asm/clock.h>
|
#include <asm/clock.h>
|
||||||
#include <asm/freq.h>
|
#include <asm/freq.h>
|
||||||
#include <cpu/sh7785.h>
|
#include <cpu/sh7785.h>
|
||||||
|
@ -88,12 +89,12 @@ struct clk div4_clks[DIV4_NR] = {
|
||||||
|
|
||||||
static struct clk mstp_clks[] = {
|
static struct clk mstp_clks[] = {
|
||||||
/* MSTPCR0 */
|
/* MSTPCR0 */
|
||||||
SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
|
SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
|
SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
|
SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
|
SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
|
SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
|
SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
|
||||||
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||||
SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
|
||||||
SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
|
||||||
|
@ -113,12 +114,48 @@ static struct clk mstp_clks[] = {
|
||||||
SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
|
SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct clk_lookup lookups[] = {
|
||||||
|
{
|
||||||
|
/* TMU0 */
|
||||||
|
.dev_id = "sh_tmu.0",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[13], /* tmu012_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU1 */
|
||||||
|
.dev_id = "sh_tmu.1",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[13],
|
||||||
|
}, {
|
||||||
|
/* TMU2 */
|
||||||
|
.dev_id = "sh_tmu.2",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[13],
|
||||||
|
}, {
|
||||||
|
/* TMU3 */
|
||||||
|
.dev_id = "sh_tmu.3",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[12], /* tmu345_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU4 */
|
||||||
|
.dev_id = "sh_tmu.4",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[12],
|
||||||
|
}, {
|
||||||
|
/* TMU5 */
|
||||||
|
.dev_id = "sh_tmu.5",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[12],
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
int __init arch_clk_init(void)
|
int __init arch_clk_init(void)
|
||||||
{
|
{
|
||||||
int i, ret = 0;
|
int i, ret = 0;
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||||
ret |= clk_register(clks[i]);
|
ret |= clk_register(clks[i]);
|
||||||
|
for (i = 0; i < ARRAY_SIZE(lookups); i++)
|
||||||
|
clkdev_add(&lookups[i]);
|
||||||
|
|
||||||
if (!ret)
|
if (!ret)
|
||||||
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
|
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
|
||||||
|
|
|
@ -13,6 +13,8 @@
|
||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
|
#include <linux/clk.h>
|
||||||
|
#include <asm/clkdev.h>
|
||||||
#include <asm/clock.h>
|
#include <asm/clock.h>
|
||||||
#include <asm/freq.h>
|
#include <asm/freq.h>
|
||||||
|
|
||||||
|
@ -87,12 +89,12 @@ struct clk div4_clks[DIV4_NR] = {
|
||||||
|
|
||||||
static struct clk mstp_clks[] = {
|
static struct clk mstp_clks[] = {
|
||||||
/* MSTPCR0 */
|
/* MSTPCR0 */
|
||||||
SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
|
SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
|
SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
|
SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
|
SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
|
SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
|
||||||
SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
|
SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
|
||||||
SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
|
SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
|
||||||
SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
|
SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
|
||||||
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
|
||||||
|
@ -120,12 +122,78 @@ static struct clk mstp_clks[] = {
|
||||||
SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
|
SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct clk_lookup lookups[] = {
|
||||||
|
{
|
||||||
|
/* TMU0 */
|
||||||
|
.dev_id = "sh_tmu.0",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[17], /* tmu012_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU1 */
|
||||||
|
.dev_id = "sh_tmu.1",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[17],
|
||||||
|
}, {
|
||||||
|
/* TMU2 */
|
||||||
|
.dev_id = "sh_tmu.2",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[17],
|
||||||
|
}, {
|
||||||
|
/* TMU3 */
|
||||||
|
.dev_id = "sh_tmu.3",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[16], /* tmu345_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU4 */
|
||||||
|
.dev_id = "sh_tmu.4",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[16],
|
||||||
|
}, {
|
||||||
|
/* TMU5 */
|
||||||
|
.dev_id = "sh_tmu.5",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[16],
|
||||||
|
}, {
|
||||||
|
/* TMU6 */
|
||||||
|
.dev_id = "sh_tmu.6",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[15], /* tmu678_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU7 */
|
||||||
|
.dev_id = "sh_tmu.7",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[15],
|
||||||
|
}, {
|
||||||
|
/* TMU8 */
|
||||||
|
.dev_id = "sh_tmu.8",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[15],
|
||||||
|
}, {
|
||||||
|
/* TMU9 */
|
||||||
|
.dev_id = "sh_tmu.9",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[14], /* tmu9_11_fck */
|
||||||
|
}, {
|
||||||
|
/* TMU10 */
|
||||||
|
.dev_id = "sh_tmu.10",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[14],
|
||||||
|
}, {
|
||||||
|
/* TMU11 */
|
||||||
|
.dev_id = "sh_tmu.11",
|
||||||
|
.con_id = "tmu_fck",
|
||||||
|
.clk = &mstp_clks[14],
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
int __init arch_clk_init(void)
|
int __init arch_clk_init(void)
|
||||||
{
|
{
|
||||||
int i, ret = 0;
|
int i, ret = 0;
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||||
ret |= clk_register(clks[i]);
|
ret |= clk_register(clks[i]);
|
||||||
|
for (i = 0; i < ARRAY_SIZE(lookups); i++)
|
||||||
|
clkdev_add(&lookups[i]);
|
||||||
|
|
||||||
if (!ret)
|
if (!ret)
|
||||||
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
|
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
|
||||||
|
|
|
@ -21,7 +21,6 @@ static struct plat_sci_port scif0_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 80, 80, 80, 80 },
|
.irqs = { 80, 80, 80, 80 },
|
||||||
.clk = "scif0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif0_device = {
|
static struct platform_device scif0_device = {
|
||||||
|
@ -37,7 +36,6 @@ static struct plat_sci_port scif1_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 81, 81, 81, 81 },
|
.irqs = { 81, 81, 81, 81 },
|
||||||
.clk = "scif1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif1_device = {
|
static struct platform_device scif1_device = {
|
||||||
|
@ -53,7 +51,6 @@ static struct plat_sci_port scif2_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 82, 82, 82, 82 },
|
.irqs = { 82, 82, 82, 82 },
|
||||||
.clk = "scif2",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif2_device = {
|
static struct platform_device scif2_device = {
|
||||||
|
@ -69,7 +66,6 @@ static struct plat_sci_port scif3_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 83, 83, 83, 83 },
|
.irqs = { 83, 83, 83, 83 },
|
||||||
.clk = "scif3",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif3_device = {
|
static struct platform_device scif3_device = {
|
||||||
|
@ -207,17 +203,14 @@ static struct platform_device jpu_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt_platform_data = {
|
static struct sh_timer_config cmt_platform_data = {
|
||||||
.name = "CMT",
|
|
||||||
.channel_offset = 0x60,
|
.channel_offset = 0x60,
|
||||||
.timer_bit = 5,
|
.timer_bit = 5,
|
||||||
.clk = "cmt0",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt_resources[] = {
|
static struct resource cmt_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT",
|
|
||||||
.start = 0x044a0060,
|
.start = 0x044a0060,
|
||||||
.end = 0x044a006b,
|
.end = 0x044a006b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -239,16 +232,13 @@ static struct platform_device cmt_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "tmu0",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -270,16 +260,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "tmu0",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -301,15 +288,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "tmu0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002b,
|
.end = 0xffd8002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -23,7 +23,6 @@ static struct plat_sci_port scif0_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 80, 80, 80, 80 },
|
.irqs = { 80, 80, 80, 80 },
|
||||||
.clk = "scif0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif0_device = {
|
static struct platform_device scif0_device = {
|
||||||
|
@ -169,17 +168,14 @@ static struct platform_device veu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt_platform_data = {
|
static struct sh_timer_config cmt_platform_data = {
|
||||||
.name = "CMT",
|
|
||||||
.channel_offset = 0x60,
|
.channel_offset = 0x60,
|
||||||
.timer_bit = 5,
|
.timer_bit = 5,
|
||||||
.clk = "cmt0",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt_resources[] = {
|
static struct resource cmt_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT",
|
|
||||||
.start = 0x044a0060,
|
.start = 0x044a0060,
|
||||||
.end = 0x044a006b,
|
.end = 0x044a006b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -201,16 +197,13 @@ static struct platform_device cmt_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "tmu0",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -232,16 +225,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "tmu0",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -263,15 +253,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "tmu0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002b,
|
.end = 0xffd8002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -174,7 +174,6 @@ static struct plat_sci_port scif0_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 80, 80, 80, 80 },
|
.irqs = { 80, 80, 80, 80 },
|
||||||
.clk = "scif0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif0_device = {
|
static struct platform_device scif0_device = {
|
||||||
|
@ -190,7 +189,6 @@ static struct plat_sci_port scif1_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 81, 81, 81, 81 },
|
.irqs = { 81, 81, 81, 81 },
|
||||||
.clk = "scif1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif1_device = {
|
static struct platform_device scif1_device = {
|
||||||
|
@ -206,7 +204,6 @@ static struct plat_sci_port scif2_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 82, 82, 82, 82 },
|
.irqs = { 82, 82, 82, 82 },
|
||||||
.clk = "scif2",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif2_device = {
|
static struct platform_device scif2_device = {
|
||||||
|
@ -401,17 +398,14 @@ static struct platform_device jpu_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt_platform_data = {
|
static struct sh_timer_config cmt_platform_data = {
|
||||||
.name = "CMT",
|
|
||||||
.channel_offset = 0x60,
|
.channel_offset = 0x60,
|
||||||
.timer_bit = 5,
|
.timer_bit = 5,
|
||||||
.clk = "cmt0",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 125,
|
.clocksource_rating = 125,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt_resources[] = {
|
static struct resource cmt_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT",
|
|
||||||
.start = 0x044a0060,
|
.start = 0x044a0060,
|
||||||
.end = 0x044a006b,
|
.end = 0x044a006b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -436,16 +430,13 @@ static struct platform_device cmt_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "tmu0",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -470,16 +461,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "tmu0",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -504,15 +492,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "tmu0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002b,
|
.end = 0xffd8002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -26,7 +26,6 @@ static struct plat_sci_port scif0_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 80, 80, 80, 80 },
|
.irqs = { 80, 80, 80, 80 },
|
||||||
.clk = "scif0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif0_device = {
|
static struct platform_device scif0_device = {
|
||||||
|
@ -42,7 +41,6 @@ static struct plat_sci_port scif1_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 81, 81, 81, 81 },
|
.irqs = { 81, 81, 81, 81 },
|
||||||
.clk = "scif1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif1_device = {
|
static struct platform_device scif1_device = {
|
||||||
|
@ -58,7 +56,6 @@ static struct plat_sci_port scif2_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 82, 82, 82, 82 },
|
.irqs = { 82, 82, 82, 82 },
|
||||||
.clk = "scif2",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif2_device = {
|
static struct platform_device scif2_device = {
|
||||||
|
@ -74,7 +71,6 @@ static struct plat_sci_port scif3_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIFA,
|
.type = PORT_SCIFA,
|
||||||
.irqs = { 56, 56, 56, 56 },
|
.irqs = { 56, 56, 56, 56 },
|
||||||
.clk = "scif3",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif3_device = {
|
static struct platform_device scif3_device = {
|
||||||
|
@ -90,7 +86,6 @@ static struct plat_sci_port scif4_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIFA,
|
.type = PORT_SCIFA,
|
||||||
.irqs = { 88, 88, 88, 88 },
|
.irqs = { 88, 88, 88, 88 },
|
||||||
.clk = "scif4",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif4_device = {
|
static struct platform_device scif4_device = {
|
||||||
|
@ -106,7 +101,6 @@ static struct plat_sci_port scif5_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIFA,
|
.type = PORT_SCIFA,
|
||||||
.irqs = { 109, 109, 109, 109 },
|
.irqs = { 109, 109, 109, 109 },
|
||||||
.clk = "scif5",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif5_device = {
|
static struct platform_device scif5_device = {
|
||||||
|
@ -211,17 +205,14 @@ static struct platform_device veu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt_platform_data = {
|
static struct sh_timer_config cmt_platform_data = {
|
||||||
.name = "CMT",
|
|
||||||
.channel_offset = 0x60,
|
.channel_offset = 0x60,
|
||||||
.timer_bit = 5,
|
.timer_bit = 5,
|
||||||
.clk = "cmt0",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 125,
|
.clocksource_rating = 125,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt_resources[] = {
|
static struct resource cmt_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT",
|
|
||||||
.start = 0x044a0060,
|
.start = 0x044a0060,
|
||||||
.end = 0x044a006b,
|
.end = 0x044a006b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -246,16 +237,13 @@ static struct platform_device cmt_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "tmu0",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -280,16 +268,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "tmu0",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -314,15 +299,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "tmu0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002b,
|
.end = 0xffd8002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -347,15 +329,12 @@ static struct platform_device tmu2_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu3_platform_data = {
|
static struct sh_timer_config tmu3_platform_data = {
|
||||||
.name = "TMU3",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "tmu1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu3_resources[] = {
|
static struct resource tmu3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU3",
|
|
||||||
.start = 0xffd90008,
|
.start = 0xffd90008,
|
||||||
.end = 0xffd90013,
|
.end = 0xffd90013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -380,15 +359,12 @@ static struct platform_device tmu3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu4_platform_data = {
|
static struct sh_timer_config tmu4_platform_data = {
|
||||||
.name = "TMU4",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "tmu1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu4_resources[] = {
|
static struct resource tmu4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU4",
|
|
||||||
.start = 0xffd90014,
|
.start = 0xffd90014,
|
||||||
.end = 0xffd9001f,
|
.end = 0xffd9001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -413,15 +389,12 @@ static struct platform_device tmu4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu5_platform_data = {
|
static struct sh_timer_config tmu5_platform_data = {
|
||||||
.name = "TMU5",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "tmu1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu5_resources[] = {
|
static struct resource tmu5_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU5",
|
|
||||||
.start = 0xffd90020,
|
.start = 0xffd90020,
|
||||||
.end = 0xffd9002b,
|
.end = 0xffd9002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -213,7 +213,6 @@ static struct plat_sci_port scif0_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 80, 80, 80, 80 },
|
.irqs = { 80, 80, 80, 80 },
|
||||||
.clk = "scif0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif0_device = {
|
static struct platform_device scif0_device = {
|
||||||
|
@ -229,7 +228,6 @@ static struct plat_sci_port scif1_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 81, 81, 81, 81 },
|
.irqs = { 81, 81, 81, 81 },
|
||||||
.clk = "scif1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif1_device = {
|
static struct platform_device scif1_device = {
|
||||||
|
@ -245,7 +243,6 @@ static struct plat_sci_port scif2_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 82, 82, 82, 82 },
|
.irqs = { 82, 82, 82, 82 },
|
||||||
.clk = "scif2",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif2_device = {
|
static struct platform_device scif2_device = {
|
||||||
|
@ -261,7 +258,6 @@ static struct plat_sci_port scif3_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIFA,
|
.type = PORT_SCIFA,
|
||||||
.irqs = { 56, 56, 56, 56 },
|
.irqs = { 56, 56, 56, 56 },
|
||||||
.clk = "scif3",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif3_device = {
|
static struct platform_device scif3_device = {
|
||||||
|
@ -277,7 +273,6 @@ static struct plat_sci_port scif4_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIFA,
|
.type = PORT_SCIFA,
|
||||||
.irqs = { 88, 88, 88, 88 },
|
.irqs = { 88, 88, 88, 88 },
|
||||||
.clk = "scif4",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif4_device = {
|
static struct platform_device scif4_device = {
|
||||||
|
@ -293,7 +288,6 @@ static struct plat_sci_port scif5_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIFA,
|
.type = PORT_SCIFA,
|
||||||
.irqs = { 109, 109, 109, 109 },
|
.irqs = { 109, 109, 109, 109 },
|
||||||
.clk = "scif5",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif5_device = {
|
static struct platform_device scif5_device = {
|
||||||
|
@ -485,17 +479,14 @@ static struct platform_device veu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config cmt_platform_data = {
|
static struct sh_timer_config cmt_platform_data = {
|
||||||
.name = "CMT",
|
|
||||||
.channel_offset = 0x60,
|
.channel_offset = 0x60,
|
||||||
.timer_bit = 5,
|
.timer_bit = 5,
|
||||||
.clk = "cmt0",
|
|
||||||
.clockevent_rating = 125,
|
.clockevent_rating = 125,
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource cmt_resources[] = {
|
static struct resource cmt_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "CMT",
|
|
||||||
.start = 0x044a0060,
|
.start = 0x044a0060,
|
||||||
.end = 0x044a006b,
|
.end = 0x044a006b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -520,16 +511,13 @@ static struct platform_device cmt_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "tmu0",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -554,16 +542,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "tmu0",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -588,15 +573,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "tmu0",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002b,
|
.end = 0xffd8002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -622,15 +604,12 @@ static struct platform_device tmu2_device = {
|
||||||
|
|
||||||
|
|
||||||
static struct sh_timer_config tmu3_platform_data = {
|
static struct sh_timer_config tmu3_platform_data = {
|
||||||
.name = "TMU3",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "tmu1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu3_resources[] = {
|
static struct resource tmu3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU3",
|
|
||||||
.start = 0xffd90008,
|
.start = 0xffd90008,
|
||||||
.end = 0xffd90013,
|
.end = 0xffd90013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -655,15 +634,12 @@ static struct platform_device tmu3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu4_platform_data = {
|
static struct sh_timer_config tmu4_platform_data = {
|
||||||
.name = "TMU4",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "tmu1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu4_resources[] = {
|
static struct resource tmu4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU4",
|
|
||||||
.start = 0xffd90014,
|
.start = 0xffd90014,
|
||||||
.end = 0xffd9001f,
|
.end = 0xffd9001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -688,15 +664,12 @@ static struct platform_device tmu4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu5_platform_data = {
|
static struct sh_timer_config tmu5_platform_data = {
|
||||||
.name = "TMU5",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "tmu1",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu5_resources[] = {
|
static struct resource tmu5_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU5",
|
|
||||||
.start = 0xffd90020,
|
.start = 0xffd90020,
|
||||||
.end = 0xffd9002b,
|
.end = 0xffd9002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -63,16 +63,13 @@ static struct platform_device scif4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xfe430008,
|
.start = 0xfe430008,
|
||||||
.end = 0xfe430013,
|
.end = 0xfe430013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -94,16 +91,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xfe430014,
|
.start = 0xfe430014,
|
||||||
.end = 0xfe43001f,
|
.end = 0xfe43001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -131,16 +131,13 @@ static struct platform_device usbf_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -162,16 +159,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -193,15 +187,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002f,
|
.end = 0xffd8002f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -223,15 +214,12 @@ static struct platform_device tmu2_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu3_platform_data = {
|
static struct sh_timer_config tmu3_platform_data = {
|
||||||
.name = "TMU3",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu3_resources[] = {
|
static struct resource tmu3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU3",
|
|
||||||
.start = 0xffd88008,
|
.start = 0xffd88008,
|
||||||
.end = 0xffd88013,
|
.end = 0xffd88013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -253,15 +241,12 @@ static struct platform_device tmu3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu4_platform_data = {
|
static struct sh_timer_config tmu4_platform_data = {
|
||||||
.name = "TMU4",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu4_resources[] = {
|
static struct resource tmu4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU4",
|
|
||||||
.start = 0xffd88014,
|
.start = 0xffd88014,
|
||||||
.end = 0xffd8801f,
|
.end = 0xffd8801f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -283,15 +268,12 @@ static struct platform_device tmu4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu5_platform_data = {
|
static struct sh_timer_config tmu5_platform_data = {
|
||||||
.name = "TMU5",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu5_resources[] = {
|
static struct resource tmu5_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU5",
|
|
||||||
.start = 0xffd88020,
|
.start = 0xffd88020,
|
||||||
.end = 0xffd8802b,
|
.end = 0xffd8802b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -165,16 +165,13 @@ static struct platform_device scif9_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -196,16 +193,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -227,15 +221,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002f,
|
.end = 0xffd8002f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -257,15 +248,12 @@ static struct platform_device tmu2_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu3_platform_data = {
|
static struct sh_timer_config tmu3_platform_data = {
|
||||||
.name = "TMU3",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu3_resources[] = {
|
static struct resource tmu3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU3",
|
|
||||||
.start = 0xffd81008,
|
.start = 0xffd81008,
|
||||||
.end = 0xffd81013,
|
.end = 0xffd81013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -287,15 +275,12 @@ static struct platform_device tmu3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu4_platform_data = {
|
static struct sh_timer_config tmu4_platform_data = {
|
||||||
.name = "TMU4",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu4_resources[] = {
|
static struct resource tmu4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU4",
|
|
||||||
.start = 0xffd81014,
|
.start = 0xffd81014,
|
||||||
.end = 0xffd8101f,
|
.end = 0xffd8101f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -317,15 +302,12 @@ static struct platform_device tmu4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu5_platform_data = {
|
static struct sh_timer_config tmu5_platform_data = {
|
||||||
.name = "TMU5",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu5_resources[] = {
|
static struct resource tmu5_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU5",
|
|
||||||
.start = 0xffd81020,
|
.start = 0xffd81020,
|
||||||
.end = 0xffd8102f,
|
.end = 0xffd8102f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -347,15 +329,12 @@ static struct platform_device tmu5_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu6_platform_data = {
|
static struct sh_timer_config tmu6_platform_data = {
|
||||||
.name = "TMU6",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu6_resources[] = {
|
static struct resource tmu6_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU6",
|
|
||||||
.start = 0xffd82008,
|
.start = 0xffd82008,
|
||||||
.end = 0xffd82013,
|
.end = 0xffd82013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -377,15 +356,12 @@ static struct platform_device tmu6_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu7_platform_data = {
|
static struct sh_timer_config tmu7_platform_data = {
|
||||||
.name = "TMU7",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu7_resources[] = {
|
static struct resource tmu7_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU7",
|
|
||||||
.start = 0xffd82014,
|
.start = 0xffd82014,
|
||||||
.end = 0xffd8201f,
|
.end = 0xffd8201f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -407,15 +383,12 @@ static struct platform_device tmu7_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu8_platform_data = {
|
static struct sh_timer_config tmu8_platform_data = {
|
||||||
.name = "TMU8",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu8_resources[] = {
|
static struct resource tmu8_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU8",
|
|
||||||
.start = 0xffd82020,
|
.start = 0xffd82020,
|
||||||
.end = 0xffd8202b,
|
.end = 0xffd8202b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -49,16 +49,13 @@ static struct platform_device scif1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -80,16 +77,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -111,15 +105,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002f,
|
.end = 0xffd8002f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -141,15 +132,12 @@ static struct platform_device tmu2_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu3_platform_data = {
|
static struct sh_timer_config tmu3_platform_data = {
|
||||||
.name = "TMU3",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu3_resources[] = {
|
static struct resource tmu3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU3",
|
|
||||||
.start = 0xffdc0008,
|
.start = 0xffdc0008,
|
||||||
.end = 0xffdc0013,
|
.end = 0xffdc0013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -171,15 +159,12 @@ static struct platform_device tmu3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu4_platform_data = {
|
static struct sh_timer_config tmu4_platform_data = {
|
||||||
.name = "TMU4",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu4_resources[] = {
|
static struct resource tmu4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU4",
|
|
||||||
.start = 0xffdc0014,
|
.start = 0xffdc0014,
|
||||||
.end = 0xffdc001f,
|
.end = 0xffdc001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -201,15 +186,12 @@ static struct platform_device tmu4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu5_platform_data = {
|
static struct sh_timer_config tmu5_platform_data = {
|
||||||
.name = "TMU5",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu5_resources[] = {
|
static struct resource tmu5_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU5",
|
|
||||||
.start = 0xffdc0020,
|
.start = 0xffdc0020,
|
||||||
.end = 0xffdc002b,
|
.end = 0xffdc002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -25,7 +25,6 @@ static struct plat_sci_port scif0_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 40, 40, 40, 40 },
|
.irqs = { 40, 40, 40, 40 },
|
||||||
.clk = "scif_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif0_device = {
|
static struct platform_device scif0_device = {
|
||||||
|
@ -41,7 +40,6 @@ static struct plat_sci_port scif1_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 44, 44, 44, 44 },
|
.irqs = { 44, 44, 44, 44 },
|
||||||
.clk = "scif_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif1_device = {
|
static struct platform_device scif1_device = {
|
||||||
|
@ -57,7 +55,6 @@ static struct plat_sci_port scif2_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 60, 60, 60, 60 },
|
.irqs = { 60, 60, 60, 60 },
|
||||||
.clk = "scif_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif2_device = {
|
static struct platform_device scif2_device = {
|
||||||
|
@ -73,7 +70,6 @@ static struct plat_sci_port scif3_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 61, 61, 61, 61 },
|
.irqs = { 61, 61, 61, 61 },
|
||||||
.clk = "scif_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif3_device = {
|
static struct platform_device scif3_device = {
|
||||||
|
@ -89,7 +85,6 @@ static struct plat_sci_port scif4_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 62, 62, 62, 62 },
|
.irqs = { 62, 62, 62, 62 },
|
||||||
.clk = "scif_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif4_device = {
|
static struct platform_device scif4_device = {
|
||||||
|
@ -105,7 +100,6 @@ static struct plat_sci_port scif5_platform_data = {
|
||||||
.flags = UPF_BOOT_AUTOCONF,
|
.flags = UPF_BOOT_AUTOCONF,
|
||||||
.type = PORT_SCIF,
|
.type = PORT_SCIF,
|
||||||
.irqs = { 63, 63, 63, 63 },
|
.irqs = { 63, 63, 63, 63 },
|
||||||
.clk = "scif_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device scif5_device = {
|
static struct platform_device scif5_device = {
|
||||||
|
@ -117,16 +111,13 @@ static struct platform_device scif5_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "tmu012_fck",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -148,16 +139,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "tmu012_fck",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -179,15 +167,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "tmu012_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002f,
|
.end = 0xffd8002f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -209,15 +194,12 @@ static struct platform_device tmu2_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu3_platform_data = {
|
static struct sh_timer_config tmu3_platform_data = {
|
||||||
.name = "TMU3",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "tmu345_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu3_resources[] = {
|
static struct resource tmu3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU3",
|
|
||||||
.start = 0xffdc0008,
|
.start = 0xffdc0008,
|
||||||
.end = 0xffdc0013,
|
.end = 0xffdc0013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -239,15 +221,12 @@ static struct platform_device tmu3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu4_platform_data = {
|
static struct sh_timer_config tmu4_platform_data = {
|
||||||
.name = "TMU4",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "tmu345_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu4_resources[] = {
|
static struct resource tmu4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU4",
|
|
||||||
.start = 0xffdc0014,
|
.start = 0xffdc0014,
|
||||||
.end = 0xffdc001f,
|
.end = 0xffdc001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -269,15 +248,12 @@ static struct platform_device tmu4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu5_platform_data = {
|
static struct sh_timer_config tmu5_platform_data = {
|
||||||
.name = "TMU5",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "tmu345_fck",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu5_resources[] = {
|
static struct resource tmu5_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU5",
|
|
||||||
.start = 0xffdc0020,
|
.start = 0xffdc0020,
|
||||||
.end = 0xffdc002b,
|
.end = 0xffdc002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -117,16 +117,13 @@ static struct platform_device scif5_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffd80008,
|
.start = 0xffd80008,
|
||||||
.end = 0xffd80013,
|
.end = 0xffd80013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -148,16 +145,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffd80014,
|
.start = 0xffd80014,
|
||||||
.end = 0xffd8001f,
|
.end = 0xffd8001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -179,15 +173,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffd80020,
|
.start = 0xffd80020,
|
||||||
.end = 0xffd8002f,
|
.end = 0xffd8002f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -209,15 +200,12 @@ static struct platform_device tmu2_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu3_platform_data = {
|
static struct sh_timer_config tmu3_platform_data = {
|
||||||
.name = "TMU3",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu3_resources[] = {
|
static struct resource tmu3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU3",
|
|
||||||
.start = 0xffda0008,
|
.start = 0xffda0008,
|
||||||
.end = 0xffda0013,
|
.end = 0xffda0013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -239,15 +227,12 @@ static struct platform_device tmu3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu4_platform_data = {
|
static struct sh_timer_config tmu4_platform_data = {
|
||||||
.name = "TMU4",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu4_resources[] = {
|
static struct resource tmu4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU4",
|
|
||||||
.start = 0xffda0014,
|
.start = 0xffda0014,
|
||||||
.end = 0xffda001f,
|
.end = 0xffda001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -269,15 +254,12 @@ static struct platform_device tmu4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu5_platform_data = {
|
static struct sh_timer_config tmu5_platform_data = {
|
||||||
.name = "TMU5",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu5_resources[] = {
|
static struct resource tmu5_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU5",
|
|
||||||
.start = 0xffda0020,
|
.start = 0xffda0020,
|
||||||
.end = 0xffda002b,
|
.end = 0xffda002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -299,15 +281,12 @@ static struct platform_device tmu5_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu6_platform_data = {
|
static struct sh_timer_config tmu6_platform_data = {
|
||||||
.name = "TMU6",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu6_resources[] = {
|
static struct resource tmu6_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU6",
|
|
||||||
.start = 0xffdc0008,
|
.start = 0xffdc0008,
|
||||||
.end = 0xffdc0013,
|
.end = 0xffdc0013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -329,15 +308,12 @@ static struct platform_device tmu6_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu7_platform_data = {
|
static struct sh_timer_config tmu7_platform_data = {
|
||||||
.name = "TMU7",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu7_resources[] = {
|
static struct resource tmu7_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU7",
|
|
||||||
.start = 0xffdc0014,
|
.start = 0xffdc0014,
|
||||||
.end = 0xffdc001f,
|
.end = 0xffdc001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -359,15 +335,12 @@ static struct platform_device tmu7_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu8_platform_data = {
|
static struct sh_timer_config tmu8_platform_data = {
|
||||||
.name = "TMU8",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu8_resources[] = {
|
static struct resource tmu8_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU8",
|
|
||||||
.start = 0xffdc0020,
|
.start = 0xffdc0020,
|
||||||
.end = 0xffdc002b,
|
.end = 0xffdc002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -389,15 +362,12 @@ static struct platform_device tmu8_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu9_platform_data = {
|
static struct sh_timer_config tmu9_platform_data = {
|
||||||
.name = "TMU9",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu9_resources[] = {
|
static struct resource tmu9_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU9",
|
|
||||||
.start = 0xffde0008,
|
.start = 0xffde0008,
|
||||||
.end = 0xffde0013,
|
.end = 0xffde0013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -419,15 +389,12 @@ static struct platform_device tmu9_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu10_platform_data = {
|
static struct sh_timer_config tmu10_platform_data = {
|
||||||
.name = "TMU10",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu10_resources[] = {
|
static struct resource tmu10_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU10",
|
|
||||||
.start = 0xffde0014,
|
.start = 0xffde0014,
|
||||||
.end = 0xffde001f,
|
.end = 0xffde001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -449,15 +416,12 @@ static struct platform_device tmu10_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu11_platform_data = {
|
static struct sh_timer_config tmu11_platform_data = {
|
||||||
.name = "TMU11",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu11_resources[] = {
|
static struct resource tmu11_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU11",
|
|
||||||
.start = 0xffde0020,
|
.start = 0xffde0020,
|
||||||
.end = 0xffde002b,
|
.end = 0xffde002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -70,16 +70,13 @@ static struct platform_device scif2_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = 0xffc10008,
|
.start = 0xffc10008,
|
||||||
.end = 0xffc10013,
|
.end = 0xffc10013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -101,16 +98,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = 0xffc10014,
|
.start = 0xffc10014,
|
||||||
.end = 0xffc1001f,
|
.end = 0xffc1001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -132,15 +126,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = 0xffc10020,
|
.start = 0xffc10020,
|
||||||
.end = 0xffc1002f,
|
.end = 0xffc1002f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -162,15 +153,12 @@ static struct platform_device tmu2_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu3_platform_data = {
|
static struct sh_timer_config tmu3_platform_data = {
|
||||||
.name = "TMU3",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu3_resources[] = {
|
static struct resource tmu3_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU3",
|
|
||||||
.start = 0xffc20008,
|
.start = 0xffc20008,
|
||||||
.end = 0xffc20013,
|
.end = 0xffc20013,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -192,15 +180,12 @@ static struct platform_device tmu3_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu4_platform_data = {
|
static struct sh_timer_config tmu4_platform_data = {
|
||||||
.name = "TMU4",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu4_resources[] = {
|
static struct resource tmu4_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU4",
|
|
||||||
.start = 0xffc20014,
|
.start = 0xffc20014,
|
||||||
.end = 0xffc2001f,
|
.end = 0xffc2001f,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -222,15 +207,12 @@ static struct platform_device tmu4_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu5_platform_data = {
|
static struct sh_timer_config tmu5_platform_data = {
|
||||||
.name = "TMU5",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu5_resources[] = {
|
static struct resource tmu5_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU5",
|
|
||||||
.start = 0xffc20020,
|
.start = 0xffc20020,
|
||||||
.end = 0xffc2002b,
|
.end = 0xffc2002b,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -68,16 +68,13 @@ static struct platform_device rtc_device = {
|
||||||
#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
|
#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
|
||||||
|
|
||||||
static struct sh_timer_config tmu0_platform_data = {
|
static struct sh_timer_config tmu0_platform_data = {
|
||||||
.name = "TMU0",
|
|
||||||
.channel_offset = 0x04,
|
.channel_offset = 0x04,
|
||||||
.timer_bit = 0,
|
.timer_bit = 0,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clockevent_rating = 200,
|
.clockevent_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu0_resources[] = {
|
static struct resource tmu0_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU0",
|
|
||||||
.start = TMU0_BASE,
|
.start = TMU0_BASE,
|
||||||
.end = TMU0_BASE + 0xc - 1,
|
.end = TMU0_BASE + 0xc - 1,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -99,16 +96,13 @@ static struct platform_device tmu0_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu1_platform_data = {
|
static struct sh_timer_config tmu1_platform_data = {
|
||||||
.name = "TMU1",
|
|
||||||
.channel_offset = 0x10,
|
.channel_offset = 0x10,
|
||||||
.timer_bit = 1,
|
.timer_bit = 1,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
.clocksource_rating = 200,
|
.clocksource_rating = 200,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu1_resources[] = {
|
static struct resource tmu1_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU1",
|
|
||||||
.start = TMU1_BASE,
|
.start = TMU1_BASE,
|
||||||
.end = TMU1_BASE + 0xc - 1,
|
.end = TMU1_BASE + 0xc - 1,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
@ -130,15 +124,12 @@ static struct platform_device tmu1_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct sh_timer_config tmu2_platform_data = {
|
static struct sh_timer_config tmu2_platform_data = {
|
||||||
.name = "TMU2",
|
|
||||||
.channel_offset = 0x1c,
|
.channel_offset = 0x1c,
|
||||||
.timer_bit = 2,
|
.timer_bit = 2,
|
||||||
.clk = "peripheral_clk",
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource tmu2_resources[] = {
|
static struct resource tmu2_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.name = "TMU2",
|
|
||||||
.start = TMU2_BASE,
|
.start = TMU2_BASE,
|
||||||
.end = TMU2_BASE + 0xc - 1,
|
.end = TMU2_BASE + 0xc - 1,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
|
|
@ -1254,6 +1254,26 @@ static int __init early_platform_driver_probe_id(char *class_str,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (match) {
|
if (match) {
|
||||||
|
/*
|
||||||
|
* Set up a sensible init_name to enable
|
||||||
|
* dev_name() and others to be used before the
|
||||||
|
* rest of the driver core is initialized.
|
||||||
|
*/
|
||||||
|
if (!match->dev.init_name) {
|
||||||
|
if (match->id != -1)
|
||||||
|
match->dev.init_name =
|
||||||
|
kasprintf(GFP_KERNEL, "%s.%d",
|
||||||
|
match->name,
|
||||||
|
match->id);
|
||||||
|
else
|
||||||
|
match->dev.init_name =
|
||||||
|
kasprintf(GFP_KERNEL, "%s",
|
||||||
|
match->name);
|
||||||
|
|
||||||
|
if (!match->dev.init_name)
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
if (epdrv->pdrv->probe(match))
|
if (epdrv->pdrv->probe(match))
|
||||||
pr_warning("%s: unable to probe %s early.\n",
|
pr_warning("%s: unable to probe %s early.\n",
|
||||||
class_str, match->name);
|
class_str, match->name);
|
||||||
|
|
|
@ -149,13 +149,12 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
|
||||||
|
|
||||||
static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
|
static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
|
||||||
{
|
{
|
||||||
struct sh_timer_config *cfg = p->pdev->dev.platform_data;
|
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
/* enable clock */
|
/* enable clock */
|
||||||
ret = clk_enable(p->clk);
|
ret = clk_enable(p->clk);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
|
dev_err(&p->pdev->dev, "cannot enable clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -278,7 +277,7 @@ static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
|
||||||
delay = 1;
|
delay = 1;
|
||||||
|
|
||||||
if (!delay)
|
if (!delay)
|
||||||
pr_warning("sh_cmt: too long delay\n");
|
dev_warn(&p->pdev->dev, "too long delay\n");
|
||||||
|
|
||||||
} while (delay);
|
} while (delay);
|
||||||
}
|
}
|
||||||
|
@ -288,7 +287,7 @@ static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
|
|
||||||
if (delta > p->max_match_value)
|
if (delta > p->max_match_value)
|
||||||
pr_warning("sh_cmt: delta out of range\n");
|
dev_warn(&p->pdev->dev, "delta out of range\n");
|
||||||
|
|
||||||
spin_lock_irqsave(&p->lock, flags);
|
spin_lock_irqsave(&p->lock, flags);
|
||||||
p->next_match_value = delta;
|
p->next_match_value = delta;
|
||||||
|
@ -450,7 +449,7 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
|
||||||
cs->resume = sh_cmt_clocksource_resume;
|
cs->resume = sh_cmt_clocksource_resume;
|
||||||
cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
|
cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
|
||||||
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
||||||
pr_info("sh_cmt: %s used as clock source\n", cs->name);
|
dev_info(&p->pdev->dev, "used as clock source\n");
|
||||||
clocksource_register(cs);
|
clocksource_register(cs);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -496,13 +495,11 @@ static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
|
||||||
|
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
case CLOCK_EVT_MODE_PERIODIC:
|
case CLOCK_EVT_MODE_PERIODIC:
|
||||||
pr_info("sh_cmt: %s used for periodic clock events\n",
|
dev_info(&p->pdev->dev, "used for periodic clock events\n");
|
||||||
ced->name);
|
|
||||||
sh_cmt_clock_event_start(p, 1);
|
sh_cmt_clock_event_start(p, 1);
|
||||||
break;
|
break;
|
||||||
case CLOCK_EVT_MODE_ONESHOT:
|
case CLOCK_EVT_MODE_ONESHOT:
|
||||||
pr_info("sh_cmt: %s used for oneshot clock events\n",
|
dev_info(&p->pdev->dev, "used for oneshot clock events\n");
|
||||||
ced->name);
|
|
||||||
sh_cmt_clock_event_start(p, 0);
|
sh_cmt_clock_event_start(p, 0);
|
||||||
break;
|
break;
|
||||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||||
|
@ -543,7 +540,7 @@ static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
|
||||||
ced->set_next_event = sh_cmt_clock_event_next;
|
ced->set_next_event = sh_cmt_clock_event_next;
|
||||||
ced->set_mode = sh_cmt_clock_event_mode;
|
ced->set_mode = sh_cmt_clock_event_mode;
|
||||||
|
|
||||||
pr_info("sh_cmt: %s used for clock events\n", ced->name);
|
dev_info(&p->pdev->dev, "used for clock events\n");
|
||||||
clockevents_register_device(ced);
|
clockevents_register_device(ced);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -600,23 +597,27 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
|
||||||
/* map memory, let mapbase point to our channel */
|
/* map memory, let mapbase point to our channel */
|
||||||
p->mapbase = ioremap_nocache(res->start, resource_size(res));
|
p->mapbase = ioremap_nocache(res->start, resource_size(res));
|
||||||
if (p->mapbase == NULL) {
|
if (p->mapbase == NULL) {
|
||||||
pr_err("sh_cmt: failed to remap I/O memory\n");
|
dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
|
||||||
goto err0;
|
goto err0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* request irq using setup_irq() (too early for request_irq()) */
|
/* request irq using setup_irq() (too early for request_irq()) */
|
||||||
p->irqaction.name = cfg->name;
|
p->irqaction.name = dev_name(&p->pdev->dev);
|
||||||
p->irqaction.handler = sh_cmt_interrupt;
|
p->irqaction.handler = sh_cmt_interrupt;
|
||||||
p->irqaction.dev_id = p;
|
p->irqaction.dev_id = p;
|
||||||
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
|
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
|
||||||
|
|
||||||
/* get hold of clock */
|
/* get hold of clock */
|
||||||
|
p->clk = clk_get(&p->pdev->dev, "cmt_fck");
|
||||||
|
if (IS_ERR(p->clk)) {
|
||||||
|
dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
|
||||||
p->clk = clk_get(&p->pdev->dev, cfg->clk);
|
p->clk = clk_get(&p->pdev->dev, cfg->clk);
|
||||||
if (IS_ERR(p->clk)) {
|
if (IS_ERR(p->clk)) {
|
||||||
pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk);
|
dev_err(&p->pdev->dev, "cannot get clock\n");
|
||||||
ret = PTR_ERR(p->clk);
|
ret = PTR_ERR(p->clk);
|
||||||
goto err1;
|
goto err1;
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
if (resource_size(res) == 6) {
|
if (resource_size(res) == 6) {
|
||||||
p->width = 16;
|
p->width = 16;
|
||||||
|
@ -628,17 +629,17 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
|
||||||
p->clear_bits = ~0xc000;
|
p->clear_bits = ~0xc000;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = sh_cmt_register(p, cfg->name,
|
ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
|
||||||
cfg->clockevent_rating,
|
cfg->clockevent_rating,
|
||||||
cfg->clocksource_rating);
|
cfg->clocksource_rating);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
pr_err("sh_cmt: registration failed\n");
|
dev_err(&p->pdev->dev, "registration failed\n");
|
||||||
goto err1;
|
goto err1;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = setup_irq(irq, &p->irqaction);
|
ret = setup_irq(irq, &p->irqaction);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
pr_err("sh_cmt: failed to request irq %d\n", irq);
|
dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
|
||||||
goto err1;
|
goto err1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -653,11 +654,10 @@ err0:
|
||||||
static int __devinit sh_cmt_probe(struct platform_device *pdev)
|
static int __devinit sh_cmt_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct sh_cmt_priv *p = platform_get_drvdata(pdev);
|
struct sh_cmt_priv *p = platform_get_drvdata(pdev);
|
||||||
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
if (p) {
|
if (p) {
|
||||||
pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name);
|
dev_info(&pdev->dev, "kept as earlytimer\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -118,13 +118,12 @@ static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
|
||||||
|
|
||||||
static int sh_mtu2_enable(struct sh_mtu2_priv *p)
|
static int sh_mtu2_enable(struct sh_mtu2_priv *p)
|
||||||
{
|
{
|
||||||
struct sh_timer_config *cfg = p->pdev->dev.platform_data;
|
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
/* enable clock */
|
/* enable clock */
|
||||||
ret = clk_enable(p->clk);
|
ret = clk_enable(p->clk);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
pr_err("sh_mtu2: cannot enable clock \"%s\"\n", cfg->clk);
|
dev_err(&p->pdev->dev, "cannot enable clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -193,8 +192,7 @@ static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
|
||||||
|
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
case CLOCK_EVT_MODE_PERIODIC:
|
case CLOCK_EVT_MODE_PERIODIC:
|
||||||
pr_info("sh_mtu2: %s used for periodic clock events\n",
|
dev_info(&p->pdev->dev, "used for periodic clock events\n");
|
||||||
ced->name);
|
|
||||||
sh_mtu2_enable(p);
|
sh_mtu2_enable(p);
|
||||||
break;
|
break;
|
||||||
case CLOCK_EVT_MODE_UNUSED:
|
case CLOCK_EVT_MODE_UNUSED:
|
||||||
|
@ -221,12 +219,12 @@ static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
|
||||||
ced->cpumask = cpumask_of(0);
|
ced->cpumask = cpumask_of(0);
|
||||||
ced->set_mode = sh_mtu2_clock_event_mode;
|
ced->set_mode = sh_mtu2_clock_event_mode;
|
||||||
|
|
||||||
pr_info("sh_mtu2: %s used for clock events\n", ced->name);
|
dev_info(&p->pdev->dev, "used for clock events\n");
|
||||||
clockevents_register_device(ced);
|
clockevents_register_device(ced);
|
||||||
|
|
||||||
ret = setup_irq(p->irqaction.irq, &p->irqaction);
|
ret = setup_irq(p->irqaction.irq, &p->irqaction);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
pr_err("sh_mtu2: failed to request irq %d\n",
|
dev_err(&p->pdev->dev, "failed to request irq %d\n",
|
||||||
p->irqaction.irq);
|
p->irqaction.irq);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -273,26 +271,31 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
|
||||||
/* map memory, let mapbase point to our channel */
|
/* map memory, let mapbase point to our channel */
|
||||||
p->mapbase = ioremap_nocache(res->start, resource_size(res));
|
p->mapbase = ioremap_nocache(res->start, resource_size(res));
|
||||||
if (p->mapbase == NULL) {
|
if (p->mapbase == NULL) {
|
||||||
pr_err("sh_mtu2: failed to remap I/O memory\n");
|
dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
|
||||||
goto err0;
|
goto err0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* setup data for setup_irq() (too early for request_irq()) */
|
/* setup data for setup_irq() (too early for request_irq()) */
|
||||||
p->irqaction.name = cfg->name;
|
p->irqaction.name = dev_name(&p->pdev->dev);
|
||||||
p->irqaction.handler = sh_mtu2_interrupt;
|
p->irqaction.handler = sh_mtu2_interrupt;
|
||||||
p->irqaction.dev_id = p;
|
p->irqaction.dev_id = p;
|
||||||
p->irqaction.irq = irq;
|
p->irqaction.irq = irq;
|
||||||
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
|
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
|
||||||
|
|
||||||
/* get hold of clock */
|
/* get hold of clock */
|
||||||
|
p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
|
||||||
|
if (IS_ERR(p->clk)) {
|
||||||
|
dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
|
||||||
p->clk = clk_get(&p->pdev->dev, cfg->clk);
|
p->clk = clk_get(&p->pdev->dev, cfg->clk);
|
||||||
if (IS_ERR(p->clk)) {
|
if (IS_ERR(p->clk)) {
|
||||||
pr_err("sh_mtu2: cannot get clock \"%s\"\n", cfg->clk);
|
dev_err(&p->pdev->dev, "cannot get clock\n");
|
||||||
ret = PTR_ERR(p->clk);
|
ret = PTR_ERR(p->clk);
|
||||||
goto err1;
|
goto err1;
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
return sh_mtu2_register(p, cfg->name, cfg->clockevent_rating);
|
return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
|
||||||
|
cfg->clockevent_rating);
|
||||||
err1:
|
err1:
|
||||||
iounmap(p->mapbase);
|
iounmap(p->mapbase);
|
||||||
err0:
|
err0:
|
||||||
|
@ -302,11 +305,10 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
|
||||||
static int __devinit sh_mtu2_probe(struct platform_device *pdev)
|
static int __devinit sh_mtu2_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
|
struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
|
||||||
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
if (p) {
|
if (p) {
|
||||||
pr_info("sh_mtu2: %s kept as earlytimer\n", cfg->name);
|
dev_info(&pdev->dev, "kept as earlytimer\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -106,13 +106,12 @@ static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
|
||||||
|
|
||||||
static int sh_tmu_enable(struct sh_tmu_priv *p)
|
static int sh_tmu_enable(struct sh_tmu_priv *p)
|
||||||
{
|
{
|
||||||
struct sh_timer_config *cfg = p->pdev->dev.platform_data;
|
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
/* enable clock */
|
/* enable clock */
|
||||||
ret = clk_enable(p->clk);
|
ret = clk_enable(p->clk);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg->clk);
|
dev_err(&p->pdev->dev, "cannot enable clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -228,7 +227,7 @@ static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
|
||||||
cs->disable = sh_tmu_clocksource_disable;
|
cs->disable = sh_tmu_clocksource_disable;
|
||||||
cs->mask = CLOCKSOURCE_MASK(32);
|
cs->mask = CLOCKSOURCE_MASK(32);
|
||||||
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
||||||
pr_info("sh_tmu: %s used as clock source\n", cs->name);
|
dev_info(&p->pdev->dev, "used as clock source\n");
|
||||||
clocksource_register(cs);
|
clocksource_register(cs);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -276,13 +275,11 @@ static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
|
||||||
|
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
case CLOCK_EVT_MODE_PERIODIC:
|
case CLOCK_EVT_MODE_PERIODIC:
|
||||||
pr_info("sh_tmu: %s used for periodic clock events\n",
|
dev_info(&p->pdev->dev, "used for periodic clock events\n");
|
||||||
ced->name);
|
|
||||||
sh_tmu_clock_event_start(p, 1);
|
sh_tmu_clock_event_start(p, 1);
|
||||||
break;
|
break;
|
||||||
case CLOCK_EVT_MODE_ONESHOT:
|
case CLOCK_EVT_MODE_ONESHOT:
|
||||||
pr_info("sh_tmu: %s used for oneshot clock events\n",
|
dev_info(&p->pdev->dev, "used for oneshot clock events\n");
|
||||||
ced->name);
|
|
||||||
sh_tmu_clock_event_start(p, 0);
|
sh_tmu_clock_event_start(p, 0);
|
||||||
break;
|
break;
|
||||||
case CLOCK_EVT_MODE_UNUSED:
|
case CLOCK_EVT_MODE_UNUSED:
|
||||||
|
@ -323,12 +320,12 @@ static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
|
||||||
ced->set_next_event = sh_tmu_clock_event_next;
|
ced->set_next_event = sh_tmu_clock_event_next;
|
||||||
ced->set_mode = sh_tmu_clock_event_mode;
|
ced->set_mode = sh_tmu_clock_event_mode;
|
||||||
|
|
||||||
pr_info("sh_tmu: %s used for clock events\n", ced->name);
|
dev_info(&p->pdev->dev, "used for clock events\n");
|
||||||
clockevents_register_device(ced);
|
clockevents_register_device(ced);
|
||||||
|
|
||||||
ret = setup_irq(p->irqaction.irq, &p->irqaction);
|
ret = setup_irq(p->irqaction.irq, &p->irqaction);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
pr_err("sh_tmu: failed to request irq %d\n",
|
dev_err(&p->pdev->dev, "failed to request irq %d\n",
|
||||||
p->irqaction.irq);
|
p->irqaction.irq);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -378,26 +375,30 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
|
||||||
/* map memory, let mapbase point to our channel */
|
/* map memory, let mapbase point to our channel */
|
||||||
p->mapbase = ioremap_nocache(res->start, resource_size(res));
|
p->mapbase = ioremap_nocache(res->start, resource_size(res));
|
||||||
if (p->mapbase == NULL) {
|
if (p->mapbase == NULL) {
|
||||||
pr_err("sh_tmu: failed to remap I/O memory\n");
|
dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
|
||||||
goto err0;
|
goto err0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* setup data for setup_irq() (too early for request_irq()) */
|
/* setup data for setup_irq() (too early for request_irq()) */
|
||||||
p->irqaction.name = cfg->name;
|
p->irqaction.name = dev_name(&p->pdev->dev);
|
||||||
p->irqaction.handler = sh_tmu_interrupt;
|
p->irqaction.handler = sh_tmu_interrupt;
|
||||||
p->irqaction.dev_id = p;
|
p->irqaction.dev_id = p;
|
||||||
p->irqaction.irq = irq;
|
p->irqaction.irq = irq;
|
||||||
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
|
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
|
||||||
|
|
||||||
/* get hold of clock */
|
/* get hold of clock */
|
||||||
|
p->clk = clk_get(&p->pdev->dev, "tmu_fck");
|
||||||
|
if (IS_ERR(p->clk)) {
|
||||||
|
dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
|
||||||
p->clk = clk_get(&p->pdev->dev, cfg->clk);
|
p->clk = clk_get(&p->pdev->dev, cfg->clk);
|
||||||
if (IS_ERR(p->clk)) {
|
if (IS_ERR(p->clk)) {
|
||||||
pr_err("sh_tmu: cannot get clock \"%s\"\n", cfg->clk);
|
dev_err(&p->pdev->dev, "cannot get clock\n");
|
||||||
ret = PTR_ERR(p->clk);
|
ret = PTR_ERR(p->clk);
|
||||||
goto err1;
|
goto err1;
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
return sh_tmu_register(p, cfg->name,
|
return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
|
||||||
cfg->clockevent_rating,
|
cfg->clockevent_rating,
|
||||||
cfg->clocksource_rating);
|
cfg->clocksource_rating);
|
||||||
err1:
|
err1:
|
||||||
|
@ -409,11 +410,10 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
|
||||||
static int __devinit sh_tmu_probe(struct platform_device *pdev)
|
static int __devinit sh_tmu_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct sh_tmu_priv *p = platform_get_drvdata(pdev);
|
struct sh_tmu_priv *p = platform_get_drvdata(pdev);
|
||||||
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
if (p) {
|
if (p) {
|
||||||
pr_info("sh_tmu: %s kept as earlytimer\n", cfg->name);
|
dev_info(&pdev->dev, "kept as earlytimer\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -25,8 +25,7 @@
|
||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/pm_runtime.h>
|
#include <linux/pm_runtime.h>
|
||||||
|
#include <linux/sh_dma.h>
|
||||||
#include <asm/dmaengine.h>
|
|
||||||
|
|
||||||
#include "shdma.h"
|
#include "shdma.h"
|
||||||
|
|
||||||
|
@ -44,7 +43,7 @@ enum sh_dmae_desc_status {
|
||||||
#define LOG2_DEFAULT_XFER_SIZE 2
|
#define LOG2_DEFAULT_XFER_SIZE 2
|
||||||
|
|
||||||
/* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
|
/* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
|
||||||
static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
|
static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)];
|
||||||
|
|
||||||
static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
|
static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
|
||||||
|
|
||||||
|
@ -266,7 +265,7 @@ static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct sh_dmae_slave_config *sh_dmae_find_slave(
|
static struct sh_dmae_slave_config *sh_dmae_find_slave(
|
||||||
struct sh_dmae_chan *sh_chan, enum sh_dmae_slave_chan_id slave_id)
|
struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
|
||||||
{
|
{
|
||||||
struct dma_device *dma_dev = sh_chan->common.device;
|
struct dma_device *dma_dev = sh_chan->common.device;
|
||||||
struct sh_dmae_device *shdev = container_of(dma_dev,
|
struct sh_dmae_device *shdev = container_of(dma_dev,
|
||||||
|
@ -274,11 +273,11 @@ static struct sh_dmae_slave_config *sh_dmae_find_slave(
|
||||||
struct sh_dmae_pdata *pdata = shdev->pdata;
|
struct sh_dmae_pdata *pdata = shdev->pdata;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER)
|
if (param->slave_id >= SH_DMA_SLAVE_NUMBER)
|
||||||
return NULL;
|
return NULL;
|
||||||
|
|
||||||
for (i = 0; i < pdata->slave_num; i++)
|
for (i = 0; i < pdata->slave_num; i++)
|
||||||
if (pdata->slave[i].slave_id == slave_id)
|
if (pdata->slave[i].slave_id == param->slave_id)
|
||||||
return pdata->slave + i;
|
return pdata->slave + i;
|
||||||
|
|
||||||
return NULL;
|
return NULL;
|
||||||
|
@ -299,7 +298,7 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
|
||||||
if (param) {
|
if (param) {
|
||||||
struct sh_dmae_slave_config *cfg;
|
struct sh_dmae_slave_config *cfg;
|
||||||
|
|
||||||
cfg = sh_dmae_find_slave(sh_chan, param->slave_id);
|
cfg = sh_dmae_find_slave(sh_chan, param);
|
||||||
if (!cfg)
|
if (!cfg)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
|
|
|
@ -17,8 +17,8 @@
|
||||||
#include <linux/interrupt.h>
|
#include <linux/interrupt.h>
|
||||||
#include <linux/list.h>
|
#include <linux/list.h>
|
||||||
|
|
||||||
#include <asm/dmaengine.h>
|
#define SH_DMAC_MAX_CHANNELS 6
|
||||||
|
#define SH_DMA_SLAVE_NUMBER 256
|
||||||
#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
|
#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
|
||||||
|
|
||||||
struct device;
|
struct device;
|
||||||
|
|
|
@ -82,16 +82,16 @@ struct sci_port {
|
||||||
|
|
||||||
/* Interface clock */
|
/* Interface clock */
|
||||||
struct clk *iclk;
|
struct clk *iclk;
|
||||||
/* Data clock */
|
/* Function clock */
|
||||||
struct clk *dclk;
|
struct clk *fclk;
|
||||||
|
|
||||||
struct list_head node;
|
struct list_head node;
|
||||||
struct dma_chan *chan_tx;
|
struct dma_chan *chan_tx;
|
||||||
struct dma_chan *chan_rx;
|
struct dma_chan *chan_rx;
|
||||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||||
struct device *dma_dev;
|
struct device *dma_dev;
|
||||||
enum sh_dmae_slave_chan_id slave_tx;
|
unsigned int slave_tx;
|
||||||
enum sh_dmae_slave_chan_id slave_rx;
|
unsigned int slave_rx;
|
||||||
struct dma_async_tx_descriptor *desc_tx;
|
struct dma_async_tx_descriptor *desc_tx;
|
||||||
struct dma_async_tx_descriptor *desc_rx[2];
|
struct dma_async_tx_descriptor *desc_rx[2];
|
||||||
dma_cookie_t cookie_tx;
|
dma_cookie_t cookie_tx;
|
||||||
|
@ -106,6 +106,7 @@ struct sci_port {
|
||||||
struct work_struct work_tx;
|
struct work_struct work_tx;
|
||||||
struct work_struct work_rx;
|
struct work_struct work_rx;
|
||||||
struct timer_list rx_timer;
|
struct timer_list rx_timer;
|
||||||
|
unsigned int rx_timeout;
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -673,22 +674,22 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
|
||||||
struct sci_port *s = to_sci_port(port);
|
struct sci_port *s = to_sci_port(port);
|
||||||
|
|
||||||
if (s->chan_rx) {
|
if (s->chan_rx) {
|
||||||
unsigned long tout;
|
|
||||||
u16 scr = sci_in(port, SCSCR);
|
u16 scr = sci_in(port, SCSCR);
|
||||||
u16 ssr = sci_in(port, SCxSR);
|
u16 ssr = sci_in(port, SCxSR);
|
||||||
|
|
||||||
/* Disable future Rx interrupts */
|
/* Disable future Rx interrupts */
|
||||||
sci_out(port, SCSCR, scr & ~SCI_CTRL_FLAGS_RIE);
|
if (port->type == PORT_SCIFA) {
|
||||||
|
disable_irq_nosync(irq);
|
||||||
|
scr |= 0x4000;
|
||||||
|
} else {
|
||||||
|
scr &= ~SCI_CTRL_FLAGS_RIE;
|
||||||
|
}
|
||||||
|
sci_out(port, SCSCR, scr);
|
||||||
/* Clear current interrupt */
|
/* Clear current interrupt */
|
||||||
sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
|
sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
|
||||||
/* Calculate delay for 1.5 DMA buffers */
|
dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
|
||||||
tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
|
jiffies, s->rx_timeout);
|
||||||
port->fifosize / 2;
|
mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
|
||||||
dev_dbg(port->dev, "Rx IRQ: setup timeout in %lu ms\n",
|
|
||||||
tout * 1000 / HZ);
|
|
||||||
if (tout < 2)
|
|
||||||
tout = 2;
|
|
||||||
mod_timer(&s->rx_timer, jiffies + tout);
|
|
||||||
|
|
||||||
return IRQ_HANDLED;
|
return IRQ_HANDLED;
|
||||||
}
|
}
|
||||||
|
@ -798,7 +799,7 @@ static int sci_notifier(struct notifier_block *self,
|
||||||
(phase == CPUFREQ_RESUMECHANGE)) {
|
(phase == CPUFREQ_RESUMECHANGE)) {
|
||||||
spin_lock_irqsave(&priv->lock, flags);
|
spin_lock_irqsave(&priv->lock, flags);
|
||||||
list_for_each_entry(sci_port, &priv->ports, node)
|
list_for_each_entry(sci_port, &priv->ports, node)
|
||||||
sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
|
sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
|
||||||
spin_unlock_irqrestore(&priv->lock, flags);
|
spin_unlock_irqrestore(&priv->lock, flags);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -809,21 +810,17 @@ static void sci_clk_enable(struct uart_port *port)
|
||||||
{
|
{
|
||||||
struct sci_port *sci_port = to_sci_port(port);
|
struct sci_port *sci_port = to_sci_port(port);
|
||||||
|
|
||||||
clk_enable(sci_port->dclk);
|
|
||||||
sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
|
|
||||||
|
|
||||||
if (sci_port->iclk)
|
|
||||||
clk_enable(sci_port->iclk);
|
clk_enable(sci_port->iclk);
|
||||||
|
sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
|
||||||
|
clk_enable(sci_port->fclk);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void sci_clk_disable(struct uart_port *port)
|
static void sci_clk_disable(struct uart_port *port)
|
||||||
{
|
{
|
||||||
struct sci_port *sci_port = to_sci_port(port);
|
struct sci_port *sci_port = to_sci_port(port);
|
||||||
|
|
||||||
if (sci_port->iclk)
|
clk_disable(sci_port->fclk);
|
||||||
clk_disable(sci_port->iclk);
|
clk_disable(sci_port->iclk);
|
||||||
|
|
||||||
clk_disable(sci_port->dclk);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int sci_request_irq(struct sci_port *port)
|
static int sci_request_irq(struct sci_port *port)
|
||||||
|
@ -912,22 +909,26 @@ static void sci_dma_tx_complete(void *arg)
|
||||||
|
|
||||||
spin_lock_irqsave(&port->lock, flags);
|
spin_lock_irqsave(&port->lock, flags);
|
||||||
|
|
||||||
xmit->tail += s->sg_tx.length;
|
xmit->tail += sg_dma_len(&s->sg_tx);
|
||||||
xmit->tail &= UART_XMIT_SIZE - 1;
|
xmit->tail &= UART_XMIT_SIZE - 1;
|
||||||
|
|
||||||
port->icount.tx += s->sg_tx.length;
|
port->icount.tx += sg_dma_len(&s->sg_tx);
|
||||||
|
|
||||||
async_tx_ack(s->desc_tx);
|
async_tx_ack(s->desc_tx);
|
||||||
s->cookie_tx = -EINVAL;
|
s->cookie_tx = -EINVAL;
|
||||||
s->desc_tx = NULL;
|
s->desc_tx = NULL;
|
||||||
|
|
||||||
spin_unlock_irqrestore(&port->lock, flags);
|
|
||||||
|
|
||||||
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
||||||
uart_write_wakeup(port);
|
uart_write_wakeup(port);
|
||||||
|
|
||||||
if (uart_circ_chars_pending(xmit))
|
if (!uart_circ_empty(xmit)) {
|
||||||
schedule_work(&s->work_tx);
|
schedule_work(&s->work_tx);
|
||||||
|
} else if (port->type == PORT_SCIFA) {
|
||||||
|
u16 ctrl = sci_in(port, SCSCR);
|
||||||
|
sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE);
|
||||||
|
}
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&port->lock, flags);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Locking: called with port lock held */
|
/* Locking: called with port lock held */
|
||||||
|
@ -971,13 +972,13 @@ static void sci_dma_rx_complete(void *arg)
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
int count;
|
int count;
|
||||||
|
|
||||||
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
|
dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
|
||||||
|
|
||||||
spin_lock_irqsave(&port->lock, flags);
|
spin_lock_irqsave(&port->lock, flags);
|
||||||
|
|
||||||
count = sci_dma_rx_push(s, tty, s->buf_len_rx);
|
count = sci_dma_rx_push(s, tty, s->buf_len_rx);
|
||||||
|
|
||||||
mod_timer(&s->rx_timer, jiffies + msecs_to_jiffies(5));
|
mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
|
||||||
|
|
||||||
spin_unlock_irqrestore(&port->lock, flags);
|
spin_unlock_irqrestore(&port->lock, flags);
|
||||||
|
|
||||||
|
@ -1049,6 +1050,8 @@ static void sci_submit_rx(struct sci_port *s)
|
||||||
sci_rx_dma_release(s, true);
|
sci_rx_dma_release(s, true);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
|
||||||
|
s->cookie_rx[i], i);
|
||||||
}
|
}
|
||||||
|
|
||||||
s->active_rx = s->cookie_rx[0];
|
s->active_rx = s->cookie_rx[0];
|
||||||
|
@ -1106,10 +1109,10 @@ static void work_fn_rx(struct work_struct *work)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
dev_dbg(port->dev, "%s: cookie %d #%d\n", __func__,
|
|
||||||
s->cookie_rx[new], new);
|
|
||||||
|
|
||||||
s->active_rx = s->cookie_rx[!new];
|
s->active_rx = s->cookie_rx[!new];
|
||||||
|
|
||||||
|
dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
|
||||||
|
s->cookie_rx[new], new, s->active_rx);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void work_fn_tx(struct work_struct *work)
|
static void work_fn_tx(struct work_struct *work)
|
||||||
|
@ -1130,14 +1133,13 @@ static void work_fn_tx(struct work_struct *work)
|
||||||
*/
|
*/
|
||||||
spin_lock_irq(&port->lock);
|
spin_lock_irq(&port->lock);
|
||||||
sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
|
sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
|
||||||
sg->dma_address = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
|
sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
|
||||||
sg->offset;
|
sg->offset;
|
||||||
sg->length = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
|
sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
|
||||||
CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
|
CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
|
||||||
sg->dma_length = sg->length;
|
|
||||||
spin_unlock_irq(&port->lock);
|
spin_unlock_irq(&port->lock);
|
||||||
|
|
||||||
BUG_ON(!sg->length);
|
BUG_ON(!sg_dma_len(sg));
|
||||||
|
|
||||||
desc = chan->device->device_prep_slave_sg(chan,
|
desc = chan->device->device_prep_slave_sg(chan,
|
||||||
sg, s->sg_len_tx, DMA_TO_DEVICE,
|
sg, s->sg_len_tx, DMA_TO_DEVICE,
|
||||||
|
@ -1172,23 +1174,28 @@ static void work_fn_tx(struct work_struct *work)
|
||||||
|
|
||||||
static void sci_start_tx(struct uart_port *port)
|
static void sci_start_tx(struct uart_port *port)
|
||||||
{
|
{
|
||||||
|
struct sci_port *s = to_sci_port(port);
|
||||||
unsigned short ctrl;
|
unsigned short ctrl;
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||||
struct sci_port *s = to_sci_port(port);
|
if (port->type == PORT_SCIFA) {
|
||||||
|
u16 new, scr = sci_in(port, SCSCR);
|
||||||
if (s->chan_tx) {
|
if (s->chan_tx)
|
||||||
if (!uart_circ_empty(&s->port.state->xmit) && s->cookie_tx < 0)
|
new = scr | 0x8000;
|
||||||
schedule_work(&s->work_tx);
|
else
|
||||||
|
new = scr & ~0x8000;
|
||||||
return;
|
if (new != scr)
|
||||||
|
sci_out(port, SCSCR, new);
|
||||||
}
|
}
|
||||||
|
if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
|
||||||
|
s->cookie_tx < 0)
|
||||||
|
schedule_work(&s->work_tx);
|
||||||
#endif
|
#endif
|
||||||
|
if (!s->chan_tx || port->type == PORT_SCIFA) {
|
||||||
/* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
|
/* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
|
||||||
ctrl = sci_in(port, SCSCR);
|
ctrl = sci_in(port, SCSCR);
|
||||||
ctrl |= SCI_CTRL_FLAGS_TIE;
|
sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE);
|
||||||
sci_out(port, SCSCR, ctrl);
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void sci_stop_tx(struct uart_port *port)
|
static void sci_stop_tx(struct uart_port *port)
|
||||||
|
@ -1197,6 +1204,8 @@ static void sci_stop_tx(struct uart_port *port)
|
||||||
|
|
||||||
/* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
|
/* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
|
||||||
ctrl = sci_in(port, SCSCR);
|
ctrl = sci_in(port, SCSCR);
|
||||||
|
if (port->type == PORT_SCIFA)
|
||||||
|
ctrl &= ~0x8000;
|
||||||
ctrl &= ~SCI_CTRL_FLAGS_TIE;
|
ctrl &= ~SCI_CTRL_FLAGS_TIE;
|
||||||
sci_out(port, SCSCR, ctrl);
|
sci_out(port, SCSCR, ctrl);
|
||||||
}
|
}
|
||||||
|
@ -1207,6 +1216,8 @@ static void sci_start_rx(struct uart_port *port)
|
||||||
|
|
||||||
/* Set RIE (Receive Interrupt Enable) bit in SCSCR */
|
/* Set RIE (Receive Interrupt Enable) bit in SCSCR */
|
||||||
ctrl |= sci_in(port, SCSCR);
|
ctrl |= sci_in(port, SCSCR);
|
||||||
|
if (port->type == PORT_SCIFA)
|
||||||
|
ctrl &= ~0x4000;
|
||||||
sci_out(port, SCSCR, ctrl);
|
sci_out(port, SCSCR, ctrl);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1216,6 +1227,8 @@ static void sci_stop_rx(struct uart_port *port)
|
||||||
|
|
||||||
/* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
|
/* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
|
||||||
ctrl = sci_in(port, SCSCR);
|
ctrl = sci_in(port, SCSCR);
|
||||||
|
if (port->type == PORT_SCIFA)
|
||||||
|
ctrl &= ~0x4000;
|
||||||
ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
|
ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
|
||||||
sci_out(port, SCSCR, ctrl);
|
sci_out(port, SCSCR, ctrl);
|
||||||
}
|
}
|
||||||
|
@ -1250,8 +1263,12 @@ static void rx_timer_fn(unsigned long arg)
|
||||||
{
|
{
|
||||||
struct sci_port *s = (struct sci_port *)arg;
|
struct sci_port *s = (struct sci_port *)arg;
|
||||||
struct uart_port *port = &s->port;
|
struct uart_port *port = &s->port;
|
||||||
|
|
||||||
u16 scr = sci_in(port, SCSCR);
|
u16 scr = sci_in(port, SCSCR);
|
||||||
|
|
||||||
|
if (port->type == PORT_SCIFA) {
|
||||||
|
scr &= ~0x4000;
|
||||||
|
enable_irq(s->irqs[1]);
|
||||||
|
}
|
||||||
sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
|
sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
|
||||||
dev_dbg(port->dev, "DMA Rx timed out\n");
|
dev_dbg(port->dev, "DMA Rx timed out\n");
|
||||||
schedule_work(&s->work_rx);
|
schedule_work(&s->work_rx);
|
||||||
|
@ -1338,8 +1355,7 @@ static void sci_request_dma(struct uart_port *port)
|
||||||
sg_init_table(sg, 1);
|
sg_init_table(sg, 1);
|
||||||
sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
|
sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
|
||||||
(int)buf[i] & ~PAGE_MASK);
|
(int)buf[i] & ~PAGE_MASK);
|
||||||
sg->dma_address = dma[i];
|
sg_dma_address(sg) = dma[i];
|
||||||
sg->dma_length = sg->length;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
INIT_WORK(&s->work_rx, work_fn_rx);
|
INIT_WORK(&s->work_rx, work_fn_rx);
|
||||||
|
@ -1402,8 +1418,12 @@ static void sci_shutdown(struct uart_port *port)
|
||||||
static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
|
static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||||
struct ktermios *old)
|
struct ktermios *old)
|
||||||
{
|
{
|
||||||
|
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||||
|
struct sci_port *s = to_sci_port(port);
|
||||||
|
#endif
|
||||||
unsigned int status, baud, smr_val, max_baud;
|
unsigned int status, baud, smr_val, max_baud;
|
||||||
int t = -1;
|
int t = -1;
|
||||||
|
u16 scfcr = 0;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* earlyprintk comes here early on with port->uartclk set to zero.
|
* earlyprintk comes here early on with port->uartclk set to zero.
|
||||||
|
@ -1426,7 +1446,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||||
sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
|
sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
|
||||||
|
|
||||||
if (port->type != PORT_SCI)
|
if (port->type != PORT_SCI)
|
||||||
sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
|
sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
|
||||||
|
|
||||||
smr_val = sci_in(port, SCSMR) & 3;
|
smr_val = sci_in(port, SCSMR) & 3;
|
||||||
if ((termios->c_cflag & CSIZE) == CS7)
|
if ((termios->c_cflag & CSIZE) == CS7)
|
||||||
|
@ -1457,10 +1477,32 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||||
}
|
}
|
||||||
|
|
||||||
sci_init_pins(port, termios->c_cflag);
|
sci_init_pins(port, termios->c_cflag);
|
||||||
sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
|
sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
|
||||||
|
|
||||||
sci_out(port, SCSCR, SCSCR_INIT(port));
|
sci_out(port, SCSCR, SCSCR_INIT(port));
|
||||||
|
|
||||||
|
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||||
|
/*
|
||||||
|
* Calculate delay for 1.5 DMA buffers: see
|
||||||
|
* drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
|
||||||
|
* (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
|
||||||
|
* calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
|
||||||
|
* Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
|
||||||
|
* sizes), but it has been found out experimentally, that this is not
|
||||||
|
* enough: the driver too often needlessly runs on a DMA timeout. 20ms
|
||||||
|
* as a minimum seem to work perfectly.
|
||||||
|
*/
|
||||||
|
if (s->chan_rx) {
|
||||||
|
s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
|
||||||
|
port->fifosize / 2;
|
||||||
|
dev_dbg(port->dev,
|
||||||
|
"DMA Rx t-out %ums, tty t-out %u jiffies\n",
|
||||||
|
s->rx_timeout * 1000 / HZ, port->timeout);
|
||||||
|
if (s->rx_timeout < msecs_to_jiffies(20))
|
||||||
|
s->rx_timeout = msecs_to_jiffies(20);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
if ((termios->c_cflag & CREAD) != 0)
|
if ((termios->c_cflag & CREAD) != 0)
|
||||||
sci_start_rx(port);
|
sci_start_rx(port);
|
||||||
}
|
}
|
||||||
|
@ -1552,7 +1594,7 @@ static struct uart_ops sci_uart_ops = {
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
static void __devinit sci_init_single(struct platform_device *dev,
|
static int __devinit sci_init_single(struct platform_device *dev,
|
||||||
struct sci_port *sci_port,
|
struct sci_port *sci_port,
|
||||||
unsigned int index,
|
unsigned int index,
|
||||||
struct plat_sci_port *p)
|
struct plat_sci_port *p)
|
||||||
|
@ -1576,8 +1618,23 @@ static void __devinit sci_init_single(struct platform_device *dev,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (dev) {
|
if (dev) {
|
||||||
sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
|
sci_port->iclk = clk_get(&dev->dev, "sci_ick");
|
||||||
sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
|
if (IS_ERR(sci_port->iclk)) {
|
||||||
|
sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
|
||||||
|
if (IS_ERR(sci_port->iclk)) {
|
||||||
|
dev_err(&dev->dev, "can't get iclk\n");
|
||||||
|
return PTR_ERR(sci_port->iclk);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The function clock is optional, ignore it if we can't
|
||||||
|
* find it.
|
||||||
|
*/
|
||||||
|
sci_port->fclk = clk_get(&dev->dev, "sci_fck");
|
||||||
|
if (IS_ERR(sci_port->fclk))
|
||||||
|
sci_port->fclk = NULL;
|
||||||
|
|
||||||
sci_port->enable = sci_clk_enable;
|
sci_port->enable = sci_clk_enable;
|
||||||
sci_port->disable = sci_clk_disable;
|
sci_port->disable = sci_clk_disable;
|
||||||
port->dev = &dev->dev;
|
port->dev = &dev->dev;
|
||||||
|
@ -1604,6 +1661,7 @@ static void __devinit sci_init_single(struct platform_device *dev,
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
|
memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
|
#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
|
||||||
|
@ -1753,8 +1811,11 @@ static int sci_remove(struct platform_device *dev)
|
||||||
cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
|
cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
|
||||||
|
|
||||||
spin_lock_irqsave(&priv->lock, flags);
|
spin_lock_irqsave(&priv->lock, flags);
|
||||||
list_for_each_entry(p, &priv->ports, node)
|
list_for_each_entry(p, &priv->ports, node) {
|
||||||
uart_remove_one_port(&sci_uart_driver, &p->port);
|
uart_remove_one_port(&sci_uart_driver, &p->port);
|
||||||
|
clk_put(p->iclk);
|
||||||
|
clk_put(p->fclk);
|
||||||
|
}
|
||||||
spin_unlock_irqrestore(&priv->lock, flags);
|
spin_unlock_irqrestore(&priv->lock, flags);
|
||||||
|
|
||||||
kfree(priv);
|
kfree(priv);
|
||||||
|
@ -1780,7 +1841,9 @@ static int __devinit sci_probe_single(struct platform_device *dev,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
sci_init_single(dev, sciport, index, p);
|
ret = sci_init_single(dev, sciport, index, p);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
|
ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
|
||||||
if (ret)
|
if (ret)
|
||||||
|
|
|
@ -44,6 +44,12 @@ struct intc_handle_int {
|
||||||
unsigned long handle;
|
unsigned long handle;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct intc_window {
|
||||||
|
phys_addr_t phys;
|
||||||
|
void __iomem *virt;
|
||||||
|
unsigned long size;
|
||||||
|
};
|
||||||
|
|
||||||
struct intc_desc_int {
|
struct intc_desc_int {
|
||||||
struct list_head list;
|
struct list_head list;
|
||||||
struct sys_device sysdev;
|
struct sys_device sysdev;
|
||||||
|
@ -57,6 +63,8 @@ struct intc_desc_int {
|
||||||
unsigned int nr_prio;
|
unsigned int nr_prio;
|
||||||
struct intc_handle_int *sense;
|
struct intc_handle_int *sense;
|
||||||
unsigned int nr_sense;
|
unsigned int nr_sense;
|
||||||
|
struct intc_window *window;
|
||||||
|
unsigned int nr_windows;
|
||||||
struct irq_chip chip;
|
struct irq_chip chip;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -446,11 +454,39 @@ static int intc_set_sense(unsigned int irq, unsigned int type)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static unsigned long intc_phys_to_virt(struct intc_desc_int *d,
|
||||||
|
unsigned long address)
|
||||||
|
{
|
||||||
|
struct intc_window *window;
|
||||||
|
int k;
|
||||||
|
|
||||||
|
/* scan through physical windows and convert address */
|
||||||
|
for (k = 0; k < d->nr_windows; k++) {
|
||||||
|
window = d->window + k;
|
||||||
|
|
||||||
|
if (address < window->phys)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
if (address >= (window->phys + window->size))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
address -= window->phys;
|
||||||
|
address += (unsigned long)window->virt;
|
||||||
|
|
||||||
|
return address;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* no windows defined, register must be 1:1 mapped virt:phys */
|
||||||
|
return address;
|
||||||
|
}
|
||||||
|
|
||||||
static unsigned int __init intc_get_reg(struct intc_desc_int *d,
|
static unsigned int __init intc_get_reg(struct intc_desc_int *d,
|
||||||
unsigned long address)
|
unsigned long address)
|
||||||
{
|
{
|
||||||
unsigned int k;
|
unsigned int k;
|
||||||
|
|
||||||
|
address = intc_phys_to_virt(d, address);
|
||||||
|
|
||||||
for (k = 0; k < d->nr_reg; k++) {
|
for (k = 0; k < d->nr_reg; k++) {
|
||||||
if (d->reg[k] == address)
|
if (d->reg[k] == address)
|
||||||
return k;
|
return k;
|
||||||
|
@ -800,6 +836,8 @@ static unsigned int __init save_reg(struct intc_desc_int *d,
|
||||||
unsigned int smp)
|
unsigned int smp)
|
||||||
{
|
{
|
||||||
if (value) {
|
if (value) {
|
||||||
|
value = intc_phys_to_virt(d, value);
|
||||||
|
|
||||||
d->reg[cnt] = value;
|
d->reg[cnt] = value;
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
d->smp[cnt] = smp;
|
d->smp[cnt] = smp;
|
||||||
|
@ -815,25 +853,52 @@ static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
|
||||||
generic_handle_irq((unsigned int)get_irq_data(irq));
|
generic_handle_irq((unsigned int)get_irq_data(irq));
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init register_intc_controller(struct intc_desc *desc)
|
int __init register_intc_controller(struct intc_desc *desc)
|
||||||
{
|
{
|
||||||
unsigned int i, k, smp;
|
unsigned int i, k, smp;
|
||||||
struct intc_hw_desc *hw = &desc->hw;
|
struct intc_hw_desc *hw = &desc->hw;
|
||||||
struct intc_desc_int *d;
|
struct intc_desc_int *d;
|
||||||
|
struct resource *res;
|
||||||
|
|
||||||
d = kzalloc(sizeof(*d), GFP_NOWAIT);
|
d = kzalloc(sizeof(*d), GFP_NOWAIT);
|
||||||
|
if (!d)
|
||||||
|
goto err0;
|
||||||
|
|
||||||
INIT_LIST_HEAD(&d->list);
|
INIT_LIST_HEAD(&d->list);
|
||||||
list_add(&d->list, &intc_list);
|
list_add(&d->list, &intc_list);
|
||||||
|
|
||||||
|
if (desc->num_resources) {
|
||||||
|
d->nr_windows = desc->num_resources;
|
||||||
|
d->window = kzalloc(d->nr_windows * sizeof(*d->window),
|
||||||
|
GFP_NOWAIT);
|
||||||
|
if (!d->window)
|
||||||
|
goto err1;
|
||||||
|
|
||||||
|
for (k = 0; k < d->nr_windows; k++) {
|
||||||
|
res = desc->resource + k;
|
||||||
|
WARN_ON(resource_type(res) != IORESOURCE_MEM);
|
||||||
|
d->window[k].phys = res->start;
|
||||||
|
d->window[k].size = resource_size(res);
|
||||||
|
d->window[k].virt = ioremap_nocache(res->start,
|
||||||
|
resource_size(res));
|
||||||
|
if (!d->window[k].virt)
|
||||||
|
goto err2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
|
d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
|
||||||
d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
|
d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
|
||||||
d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
|
d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
|
||||||
d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
|
d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
|
||||||
|
|
||||||
d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
|
d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
|
||||||
|
if (!d->reg)
|
||||||
|
goto err2;
|
||||||
|
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
|
d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
|
||||||
|
if (!d->smp)
|
||||||
|
goto err3;
|
||||||
#endif
|
#endif
|
||||||
k = 0;
|
k = 0;
|
||||||
|
|
||||||
|
@ -848,6 +913,8 @@ void __init register_intc_controller(struct intc_desc *desc)
|
||||||
if (hw->prio_regs) {
|
if (hw->prio_regs) {
|
||||||
d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
|
d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
|
||||||
GFP_NOWAIT);
|
GFP_NOWAIT);
|
||||||
|
if (!d->prio)
|
||||||
|
goto err4;
|
||||||
|
|
||||||
for (i = 0; i < hw->nr_prio_regs; i++) {
|
for (i = 0; i < hw->nr_prio_regs; i++) {
|
||||||
smp = IS_SMP(hw->prio_regs[i]);
|
smp = IS_SMP(hw->prio_regs[i]);
|
||||||
|
@ -859,6 +926,8 @@ void __init register_intc_controller(struct intc_desc *desc)
|
||||||
if (hw->sense_regs) {
|
if (hw->sense_regs) {
|
||||||
d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
|
d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
|
||||||
GFP_NOWAIT);
|
GFP_NOWAIT);
|
||||||
|
if (!d->sense)
|
||||||
|
goto err5;
|
||||||
|
|
||||||
for (i = 0; i < hw->nr_sense_regs; i++)
|
for (i = 0; i < hw->nr_sense_regs; i++)
|
||||||
k += save_reg(d, k, hw->sense_regs[i].reg, 0);
|
k += save_reg(d, k, hw->sense_regs[i].reg, 0);
|
||||||
|
@ -941,6 +1010,28 @@ void __init register_intc_controller(struct intc_desc *desc)
|
||||||
/* enable bits matching force_enable after registering irqs */
|
/* enable bits matching force_enable after registering irqs */
|
||||||
if (desc->force_enable)
|
if (desc->force_enable)
|
||||||
intc_enable_disable_enum(desc, d, desc->force_enable, 1);
|
intc_enable_disable_enum(desc, d, desc->force_enable, 1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
err5:
|
||||||
|
kfree(d->prio);
|
||||||
|
err4:
|
||||||
|
#ifdef CONFIG_SMP
|
||||||
|
kfree(d->smp);
|
||||||
|
err3:
|
||||||
|
#endif
|
||||||
|
kfree(d->reg);
|
||||||
|
err2:
|
||||||
|
for (k = 0; k < d->nr_windows; k++)
|
||||||
|
if (d->window[k].virt)
|
||||||
|
iounmap(d->window[k].virt);
|
||||||
|
|
||||||
|
kfree(d->window);
|
||||||
|
err1:
|
||||||
|
kfree(d);
|
||||||
|
err0:
|
||||||
|
pr_err("unable to allocate INTC memory\n");
|
||||||
|
|
||||||
|
return -ENOMEM;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int intc_suspend(struct sys_device *dev, pm_message_t state)
|
static int intc_suspend(struct sys_device *dev, pm_message_t state)
|
||||||
|
|
|
@ -451,6 +451,10 @@ struct device {
|
||||||
|
|
||||||
static inline const char *dev_name(const struct device *dev)
|
static inline const char *dev_name(const struct device *dev)
|
||||||
{
|
{
|
||||||
|
/* Use the init name until the kobject becomes available */
|
||||||
|
if (dev->init_name)
|
||||||
|
return dev->init_name;
|
||||||
|
|
||||||
return kobject_name(&dev->kobj);
|
return kobject_name(&dev->kobj);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -33,8 +33,8 @@ struct plat_sci_port {
|
||||||
char *clk; /* clock string */
|
char *clk; /* clock string */
|
||||||
struct device *dma_dev;
|
struct device *dma_dev;
|
||||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||||
enum sh_dmae_slave_chan_id dma_slave_tx;
|
unsigned int dma_slave_tx;
|
||||||
enum sh_dmae_slave_chan_id dma_slave_rx;
|
unsigned int dma_slave_rx;
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,101 @@
|
||||||
|
/*
|
||||||
|
* Header for the new SH dmaengine driver
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
#ifndef SH_DMA_H
|
||||||
|
#define SH_DMA_H
|
||||||
|
|
||||||
|
#include <linux/list.h>
|
||||||
|
#include <linux/dmaengine.h>
|
||||||
|
|
||||||
|
/* Used by slave DMA clients to request DMA to/from a specific peripheral */
|
||||||
|
struct sh_dmae_slave {
|
||||||
|
unsigned int slave_id; /* Set by the platform */
|
||||||
|
struct device *dma_dev; /* Set by the platform */
|
||||||
|
struct sh_dmae_slave_config *config; /* Set by the driver */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct sh_dmae_regs {
|
||||||
|
u32 sar; /* SAR / source address */
|
||||||
|
u32 dar; /* DAR / destination address */
|
||||||
|
u32 tcr; /* TCR / transfer count */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct sh_desc {
|
||||||
|
struct sh_dmae_regs hw;
|
||||||
|
struct list_head node;
|
||||||
|
struct dma_async_tx_descriptor async_tx;
|
||||||
|
enum dma_data_direction direction;
|
||||||
|
dma_cookie_t cookie;
|
||||||
|
size_t partial;
|
||||||
|
int chunks;
|
||||||
|
int mark;
|
||||||
|
};
|
||||||
|
struct sh_dmae_slave_config {
|
||||||
|
unsigned int slave_id;
|
||||||
|
dma_addr_t addr;
|
||||||
|
u32 chcr;
|
||||||
|
char mid_rid;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct sh_dmae_channel {
|
||||||
|
unsigned int offset;
|
||||||
|
unsigned int dmars;
|
||||||
|
unsigned int dmars_bit;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct sh_dmae_pdata {
|
||||||
|
struct sh_dmae_slave_config *slave;
|
||||||
|
int slave_num;
|
||||||
|
struct sh_dmae_channel *channel;
|
||||||
|
int channel_num;
|
||||||
|
unsigned int ts_low_shift;
|
||||||
|
unsigned int ts_low_mask;
|
||||||
|
unsigned int ts_high_shift;
|
||||||
|
unsigned int ts_high_mask;
|
||||||
|
unsigned int *ts_shift;
|
||||||
|
int ts_shift_num;
|
||||||
|
u16 dmaor_init;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* DMA register */
|
||||||
|
#define SAR 0x00
|
||||||
|
#define DAR 0x04
|
||||||
|
#define TCR 0x08
|
||||||
|
#define CHCR 0x0C
|
||||||
|
#define DMAOR 0x40
|
||||||
|
|
||||||
|
/* DMAOR definitions */
|
||||||
|
#define DMAOR_AE 0x00000004
|
||||||
|
#define DMAOR_NMIF 0x00000002
|
||||||
|
#define DMAOR_DME 0x00000001
|
||||||
|
|
||||||
|
/* Definitions for the SuperH DMAC */
|
||||||
|
#define REQ_L 0x00000000
|
||||||
|
#define REQ_E 0x00080000
|
||||||
|
#define RACK_H 0x00000000
|
||||||
|
#define RACK_L 0x00040000
|
||||||
|
#define ACK_R 0x00000000
|
||||||
|
#define ACK_W 0x00020000
|
||||||
|
#define ACK_H 0x00000000
|
||||||
|
#define ACK_L 0x00010000
|
||||||
|
#define DM_INC 0x00004000
|
||||||
|
#define DM_DEC 0x00008000
|
||||||
|
#define DM_FIX 0x0000c000
|
||||||
|
#define SM_INC 0x00001000
|
||||||
|
#define SM_DEC 0x00002000
|
||||||
|
#define SM_FIX 0x00003000
|
||||||
|
#define RS_IN 0x00000200
|
||||||
|
#define RS_OUT 0x00000300
|
||||||
|
#define TS_BLK 0x00000040
|
||||||
|
#define TM_BUR 0x00000020
|
||||||
|
#define CHCR_DE 0x00000001
|
||||||
|
#define CHCR_TE 0x00000002
|
||||||
|
#define CHCR_IE 0x00000004
|
||||||
|
|
||||||
|
#endif
|
|
@ -1,6 +1,8 @@
|
||||||
#ifndef __SH_INTC_H
|
#ifndef __SH_INTC_H
|
||||||
#define __SH_INTC_H
|
#define __SH_INTC_H
|
||||||
|
|
||||||
|
#include <linux/ioport.h>
|
||||||
|
|
||||||
typedef unsigned char intc_enum;
|
typedef unsigned char intc_enum;
|
||||||
|
|
||||||
struct intc_vect {
|
struct intc_vect {
|
||||||
|
@ -71,6 +73,8 @@ struct intc_hw_desc {
|
||||||
|
|
||||||
struct intc_desc {
|
struct intc_desc {
|
||||||
char *name;
|
char *name;
|
||||||
|
struct resource *resource;
|
||||||
|
unsigned int num_resources;
|
||||||
intc_enum force_enable;
|
intc_enum force_enable;
|
||||||
intc_enum force_disable;
|
intc_enum force_disable;
|
||||||
struct intc_hw_desc hw;
|
struct intc_hw_desc hw;
|
||||||
|
@ -92,7 +96,7 @@ struct intc_desc symbol __initdata = { \
|
||||||
prio_regs, sense_regs, ack_regs), \
|
prio_regs, sense_regs, ack_regs), \
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init register_intc_controller(struct intc_desc *desc);
|
int __init register_intc_controller(struct intc_desc *desc);
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int intc_set_priority(unsigned int irq, unsigned int prio);
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int intc_set_priority(unsigned int irq, unsigned int prio);
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int reserve_irq_vector(unsigned int irq);
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int reserve_irq_vector(unsigned int irq);
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||||||
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Reference in New Issue