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ARM: mach-shmobile: sh73a0 CPGA fix for PLL CFG bit 

PLL1 and PLL2 in the sh73a0 CPGA has a CFG bit that
must be taken into account to correctly calculate the
frequency.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm 2011-01-20 08:11:11 +00:00 committed by Paul Mundt
parent 2150dace47
commit 71fc5099ed
1 changed files with 9 additions and 1 deletions
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10
arch/arm/mach-shmobile/clock-sh73a0.c
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@ -118,8 +118,16 @@ static unsigned long pll_recalc(struct clk *clk)
{ {
unsigned long mult = 1; unsigned long mult = 1;
if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
/* handle CFG bit for PLL1 and PLL2 */
switch (clk->enable_bit) {
case 1:
case 2:
if (__raw_readl(clk->enable_reg) & (1 << 20))
mult *= 2;
}
}
return clk->parent->rate * mult; return clk->parent->rate * mult;
} }