ARM: mach-shmobile: sh73a0 CPGA fix for PLL CFG bit
PLL1 and PLL2 in the sh73a0 CPGA has a CFG bit that must be taken into account to correctly calculate the frequency. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -118,8 +118,16 @@ static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
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if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
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mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
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/* handle CFG bit for PLL1 and PLL2 */
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switch (clk->enable_bit) {
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case 1:
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case 2:
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if (__raw_readl(clk->enable_reg) & (1 << 20))
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mult *= 2;
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}
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}
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return clk->parent->rate * mult;
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}
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