staging: comedi: mite: move mite_prep_dma()
For aesthetics, move this functions to a more logical spot in the code and add a docbook comment for the exported function. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
c3c860b395
commit
71f53ea4ba
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@ -247,91 +247,6 @@ void mite_dma_arm(struct mite_channel *mite_chan)
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}
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EXPORT_SYMBOL_GPL(mite_dma_arm);
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void mite_prep_dma(struct mite_channel *mite_chan,
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unsigned int num_device_bits, unsigned int num_memory_bits)
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{
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struct mite *mite = mite_chan->mite;
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unsigned int chcr, mcr, dcr, lkcr;
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mite_dma_reset(mite_chan);
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/* short link chaining mode */
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chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
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CHCR_BURSTEN;
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/*
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* Link Complete Interrupt: interrupt every time a link
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* in MITE_RING is completed. This can generate a lot of
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* extra interrupts, but right now we update the values
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* of buf_int_ptr and buf_int_count at each interrupt. A
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* better method is to poll the MITE before each user
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* "read()" to calculate the number of bytes available.
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*/
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chcr |= CHCR_SET_LC_IE;
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if (num_memory_bits == 32 && num_device_bits == 16) {
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/*
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* Doing a combined 32 and 16 bit byteswap gets the 16 bit
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* samples into the fifo in the right order. Tested doing 32 bit
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* memory to 16 bit device transfers to the analog out of a
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* pxi-6281, which has mite version = 1, type = 4. This also
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* works for dma reads from the counters on e-series boards.
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*/
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chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
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}
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if (mite_chan->dir == COMEDI_INPUT)
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chcr |= CHCR_DEV_TO_MEM;
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writel(chcr, mite->mmio + MITE_CHCR(mite_chan->channel));
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/* to/from memory */
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mcr = mite_retry_limit(64) | CR_ASEQUP;
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switch (num_memory_bits) {
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case 8:
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mcr |= CR_PSIZE8;
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break;
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case 16:
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mcr |= CR_PSIZE16;
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break;
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case 32:
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mcr |= CR_PSIZE32;
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break;
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default:
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pr_warn("bug! invalid mem bit width for dma transfer\n");
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break;
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}
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writel(mcr, mite->mmio + MITE_MCR(mite_chan->channel));
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/* from/to device */
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dcr = mite_retry_limit(64) | CR_ASEQUP;
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dcr |= CR_PORTIO | CR_AMDEVICE | mite_drq_reqs(mite_chan->channel);
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switch (num_device_bits) {
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case 8:
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dcr |= CR_PSIZE8;
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break;
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case 16:
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dcr |= CR_PSIZE16;
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break;
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case 32:
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dcr |= CR_PSIZE32;
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break;
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default:
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pr_warn("bug! invalid dev bit width for dma transfer\n");
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break;
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}
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writel(dcr, mite->mmio + MITE_DCR(mite_chan->channel));
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/* reset the DAR */
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writel(0, mite->mmio + MITE_DAR(mite_chan->channel));
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/* the link is 32bits */
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lkcr = mite_retry_limit(64) | CR_ASEQUP | CR_PSIZE32;
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writel(lkcr, mite->mmio + MITE_LKCR(mite_chan->channel));
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/* starting address for link chaining */
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writel(mite_chan->ring->dma_addr,
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mite->mmio + MITE_LKAR(mite_chan->channel));
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}
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EXPORT_SYMBOL_GPL(mite_prep_dma);
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static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
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{
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struct mite *mite = mite_chan->mite;
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@ -532,6 +447,97 @@ int mite_done(struct mite_channel *mite_chan)
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}
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EXPORT_SYMBOL_GPL(mite_done);
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/**
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* mite_prep_dma() - Prepare a MITE dma channel for transfers.
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* @mite_chan: MITE dma channel.
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* @num_device_bits: device transfer size (8, 16, or 32-bits).
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* @num_memory_bits: memory transfer size (8, 16, or 32-bits).
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*/
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void mite_prep_dma(struct mite_channel *mite_chan,
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unsigned int num_device_bits, unsigned int num_memory_bits)
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{
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struct mite *mite = mite_chan->mite;
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unsigned int chcr, mcr, dcr, lkcr;
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mite_dma_reset(mite_chan);
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/* short link chaining mode */
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chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
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CHCR_BURSTEN;
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/*
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* Link Complete Interrupt: interrupt every time a link
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* in MITE_RING is completed. This can generate a lot of
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* extra interrupts, but right now we update the values
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* of buf_int_ptr and buf_int_count at each interrupt. A
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* better method is to poll the MITE before each user
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* "read()" to calculate the number of bytes available.
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*/
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chcr |= CHCR_SET_LC_IE;
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if (num_memory_bits == 32 && num_device_bits == 16) {
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/*
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* Doing a combined 32 and 16 bit byteswap gets the 16 bit
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* samples into the fifo in the right order. Tested doing 32 bit
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* memory to 16 bit device transfers to the analog out of a
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* pxi-6281, which has mite version = 1, type = 4. This also
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* works for dma reads from the counters on e-series boards.
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*/
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chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
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}
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if (mite_chan->dir == COMEDI_INPUT)
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chcr |= CHCR_DEV_TO_MEM;
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writel(chcr, mite->mmio + MITE_CHCR(mite_chan->channel));
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/* to/from memory */
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mcr = mite_retry_limit(64) | CR_ASEQUP;
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switch (num_memory_bits) {
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case 8:
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mcr |= CR_PSIZE8;
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break;
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case 16:
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mcr |= CR_PSIZE16;
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break;
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case 32:
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mcr |= CR_PSIZE32;
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break;
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default:
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pr_warn("bug! invalid mem bit width for dma transfer\n");
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break;
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}
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writel(mcr, mite->mmio + MITE_MCR(mite_chan->channel));
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/* from/to device */
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dcr = mite_retry_limit(64) | CR_ASEQUP;
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dcr |= CR_PORTIO | CR_AMDEVICE | mite_drq_reqs(mite_chan->channel);
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switch (num_device_bits) {
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case 8:
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dcr |= CR_PSIZE8;
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break;
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case 16:
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dcr |= CR_PSIZE16;
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break;
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case 32:
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dcr |= CR_PSIZE32;
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break;
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default:
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pr_warn("bug! invalid dev bit width for dma transfer\n");
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break;
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}
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writel(dcr, mite->mmio + MITE_DCR(mite_chan->channel));
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/* reset the DAR */
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writel(0, mite->mmio + MITE_DAR(mite_chan->channel));
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/* the link is 32bits */
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lkcr = mite_retry_limit(64) | CR_ASEQUP | CR_PSIZE32;
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writel(lkcr, mite->mmio + MITE_LKCR(mite_chan->channel));
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/* starting address for link chaining */
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writel(mite_chan->ring->dma_addr,
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mite->mmio + MITE_LKAR(mite_chan->channel));
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}
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EXPORT_SYMBOL_GPL(mite_prep_dma);
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static struct mite_channel *__mite_request_channel(struct mite *mite,
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struct mite_ring *ring,
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unsigned int min_channel,
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@ -68,7 +68,7 @@ void mite_ack_linkc(struct mite_channel *, struct comedi_subdevice *,
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bool sync);
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int mite_done(struct mite_channel *mite_chan);
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void mite_prep_dma(struct mite_channel *mite_chan,
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void mite_prep_dma(struct mite_channel *,
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unsigned int num_device_bits, unsigned int num_memory_bits);
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struct mite_channel *mite_request_channel_in_range(struct mite *,
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