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linux-sg2042
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stable

This commit is contained in:
Russell King 2011-03-06 08:42:55 +00:00
parent 0fff6b9a4e 53936c56dc
commit 71d8c5b11e
152 changed files with 1585 additions and 1285 deletions
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5
Documentation/DocBook/filesystems.tmpl
View File

@ -82,6 +82,11 @@
</sect1>
</chapter>
<chapter id="fs_events">
<title>Events based on file descriptors</title>
!Efs/eventfd.c
</chapter>
<chapter id="sysfs">
<title>The Filesystem for Exporting Kernel Objects</title>
!Efs/sysfs/file.c

21
Documentation/hwmon/jc42
View File

@ -51,7 +51,8 @@ Supported chips:
* JEDEC JC 42.4 compliant temperature sensor chips
Prefix: 'jc42'
Addresses scanned: I2C 0x18 - 0x1f
Datasheet: -
Datasheet:
http://www.jedec.org/sites/default/files/docs/4_01_04R19.pdf
Author:
Guenter Roeck <guenter.roeck@ericsson.com>
@ -60,7 +61,11 @@ Author:
Description
-----------
This driver implements support for JEDEC JC 42.4 compliant temperature sensors.
This driver implements support for JEDEC JC 42.4 compliant temperature sensors,
which are used on many DDR3 memory modules for mobile devices and servers. Some
systems use the sensor to prevent memory overheating by automatically throttling
the memory controller.
The driver auto-detects the chips listed above, but can be manually instantiated
to support other JC 42.4 compliant chips.
@ -81,15 +86,19 @@ limits. The chip supports only a single register to configure the hysteresis,
which applies to all limits. This register can be written by writing into
temp1_crit_hyst. Other hysteresis attributes are read-only.
If the BIOS has configured the sensor for automatic temperature management, it
is likely that it has locked the registers, i.e., that the temperature limits
cannot be changed.
Sysfs entries
-------------
temp1_input Temperature (RO)
temp1_min Minimum temperature (RW)
temp1_max Maximum temperature (RW)
temp1_crit Critical high temperature (RW)
temp1_min Minimum temperature (RO or RW)
temp1_max Maximum temperature (RO or RW)
temp1_crit Critical high temperature (RO or RW)
temp1_crit_hyst Critical hysteresis temperature (RW)
temp1_crit_hyst Critical hysteresis temperature (RO or RW)
temp1_max_hyst Maximum hysteresis temperature (RO)
temp1_min_alarm Temperature low alarm

8
Documentation/hwmon/k10temp
View File

@ -9,6 +9,8 @@ Supported chips:
Socket S1G3: Athlon II, Sempron, Turion II
* AMD Family 11h processors:
Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
* AMD Family 12h processors: "Llano"
* AMD Family 14h processors: "Brazos" (C/E/G-Series)
Prefix: 'k10temp'
Addresses scanned: PCI space
@ -17,10 +19,14 @@ Supported chips:
http://support.amd.com/us/Processor_TechDocs/31116.pdf
BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors:
http://support.amd.com/us/Processor_TechDocs/41256.pdf
BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
http://support.amd.com/us/Processor_TechDocs/43170.pdf
Revision Guide for AMD Family 10h Processors:
http://support.amd.com/us/Processor_TechDocs/41322.pdf
Revision Guide for AMD Family 11h Processors:
http://support.amd.com/us/Processor_TechDocs/41788.pdf
Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
http://support.amd.com/us/Processor_TechDocs/47534.pdf
AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:
http://support.amd.com/us/Processor_TechDocs/43373.pdf
AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
@ -34,7 +40,7 @@ Description
-----------
This driver permits reading of the internal temperature sensor of AMD
Family 10h and 11h processors.
Family 10h/11h/12h/14h processors.
All these processors have a sensor, but on those for Socket F or AM2+,
the sensor may return inconsistent values (erratum 319). The driver

24
Documentation/kernel-parameters.txt
View File

@ -144,6 +144,11 @@ a fixed number of characters. This limit depends on the architecture
and is between 256 and 4096 characters. It is defined in the file
./include/asm/setup.h as COMMAND_LINE_SIZE.
Finally, the [KMG] suffix is commonly described after a number of kernel
parameter values. These 'K', 'M', and 'G' letters represent the _binary_
multipliers 'Kilo', 'Mega', and 'Giga', equalling 2^10, 2^20, and 2^30
bytes respectively. Such letter suffixes can also be entirely omitted.
acpi= [HW,ACPI,X86]
Advanced Configuration and Power Interface
@ -545,16 +550,20 @@ and is between 256 and 4096 characters. It is defined in the file
Format:
<first_slot>,<last_slot>,<port>,<enum_bit>[,<debug>]
crashkernel=nn[KMG]@ss[KMG]
[KNL] Reserve a chunk of physical memory to
hold a kernel to switch to with kexec on panic.
crashkernel=size[KMG][@offset[KMG]]
[KNL] Using kexec, Linux can switch to a 'crash kernel'
upon panic. This parameter reserves the physical
memory region [offset, offset + size] for that kernel
image. If '@offset' is omitted, then a suitable offset
is selected automatically. Check
Documentation/kdump/kdump.txt for further details.
crashkernel=range1:size1[,range2:size2,...][@offset]
[KNL] Same as above, but depends on the memory
in the running system. The syntax of range is
start-[end] where start and end are both
a memory unit (amount[KMG]). See also
Documentation/kdump/kdump.txt for a example.
Documentation/kdump/kdump.txt for an example.
cs89x0_dma= [HW,NET]
Format: <dma>
@ -1262,10 +1271,9 @@ and is between 256 and 4096 characters. It is defined in the file
6 (KERN_INFO) informational
7 (KERN_DEBUG) debug-level messages
log_buf_len=n Sets the size of the printk ring buffer, in bytes.
Format: { n | nk | nM }
n must be a power of two. The default size
is set in the kernel config file.
log_buf_len=n[KMG] Sets the size of the printk ring buffer,
in bytes. n must be a power of two. The default
size is set in the kernel config file.
logo.nologo [FB] Disables display of the built-in Linux logo.
This may be used to provide more screen space for

3
MAINTAINERS
View File

@ -885,7 +885,7 @@ S: Supported
ARM/QUALCOMM MSM MACHINE SUPPORT
M: David Brown <davidb@codeaurora.org>
M: Daniel Walker <dwalker@codeaurora.org>
M: Daniel Walker <dwalker@fifo99.com>
M: Bryan Huntsman <bryanh@codeaurora.org>
L: linux-arm-msm@vger.kernel.org
F: arch/arm/mach-msm/
@ -2873,7 +2873,6 @@ M: Guenter Roeck <guenter.roeck@ericsson.com>
L: lm-sensors@lm-sensors.org
W: http://www.lm-sensors.org/
T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
T: quilt kernel.org/pub/linux/kernel/people/groeck/linux-staging/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
S: Maintained
F: Documentation/hwmon/

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 38
EXTRAVERSION = -rc5
EXTRAVERSION = -rc6
NAME = Flesh-Eating Bats with Fangs
# *DOCUMENTATION*

25
arch/arm/Kconfig
View File

@ -1177,6 +1177,31 @@ config ARM_ERRATA_743622
visible impact on the overall performance or power consumption of the
processor.
config ARM_ERRATA_751472
bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
depends on CPU_V7 && SMP
help
This option enables the workaround for the 751472 Cortex-A9 (prior
to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
completion of a following broadcasted operation if the second
operation is received by a CPU before the ICIALLUIS has completed,
potentially leading to corrupted entries in the cache or TLB.
config ARM_ERRATA_753970
bool "ARM errata: cache sync operation may be faulty"
depends on CACHE_PL310
help
This option enables the workaround for the 753970 PL310 (r3p0) erratum.
Under some condition the effect of cache sync operation on
the store buffer still remains when the operation completes.
This means that the store buffer is always asked to drain and
this prevents it from merging any further writes. The workaround
is to replace the normal offset of cache sync operation (0x730)
by another offset targeting an unmapped PL310 register 0x740.
This has the same effect as the cache sync operation: store buffer
drain and waiting for all buffers empty.
endmenu
source "arch/arm/common/Kconfig"

2
arch/arm/Makefile
View File

@ -15,7 +15,7 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
LDFLAGS_vmlinux += --be8
endif
OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
OBJCOPYFLAGS :=-O binary -R .comment -S
GZFLAGS :=-9
#KBUILD_CFLAGS +=-pipe
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:

6
arch/arm/boot/compressed/.gitignore vendored
View File

@ -1,3 +1,7 @@
font.c
piggy.gz
lib1funcs.S
piggy.gzip
piggy.lzo
piggy.lzma
vmlinux
vmlinux.lds

1
arch/arm/configs/kirkwood_defconfig
View File

@ -24,6 +24,7 @@ CONFIG_MACH_OPENRD_ULTIMATE=y
CONFIG_MACH_NETSPACE_V2=y
CONFIG_MACH_INETSPACE_V2=y
CONFIG_MACH_NETSPACE_MAX_V2=y
CONFIG_MACH_D2NET_V2=y
CONFIG_MACH_NET2BIG_V2=y
CONFIG_MACH_NET5BIG_V2=y
CONFIG_MACH_T5325=y

1
arch/arm/include/asm/hardware/cache-l2x0.h
View File

@ -36,6 +36,7 @@
#define L2X0_RAW_INTR_STAT 0x21C
#define L2X0_INTR_CLEAR 0x220
#define L2X0_CACHE_SYNC 0x730
#define L2X0_DUMMY_REG 0x740
#define L2X0_INV_LINE_PA 0x770
#define L2X0_INV_WAY 0x77C
#define L2X0_CLEAN_LINE_PA 0x7B0

3
arch/arm/include/asm/hardware/sp810.h
View File

@ -58,6 +58,9 @@
static inline void sysctl_soft_reset(void __iomem *base)
{
/* switch to slow mode */
writel(0x2, base + SCCTRL);
/* writing any value to SCSYSSTAT reg will reset system */
writel(0, base + SCSYSSTAT);
}

3
arch/arm/include/asm/kexec.h
View File

@ -50,6 +50,9 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
}
}
/* Function pointer to optional machine-specific reinitialization */
extern void (*kexec_reinit)(void);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_KEXEC */

105
arch/arm/include/asm/tlb.h
View File

@ -18,16 +18,34 @@
#define __ASMARM_TLB_H
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#ifndef CONFIG_MMU
#include <linux/pagemap.h>
#define tlb_flush(tlb) ((void) tlb)
#include <asm-generic/tlb.h>
#else /* !CONFIG_MMU */
#include <linux/swap.h>
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
/*
* We need to delay page freeing for SMP as other CPUs can access pages
* which have been removed but not yet had their TLB entries invalidated.
* Also, as ARMv7 speculative prefetch can drag new entries into the TLB,
* we need to apply this same delaying tactic to ensure correct operation.
*/
#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
#define tlb_fast_mode(tlb) 0
#define FREE_PTE_NR 500
#else
#define tlb_fast_mode(tlb) 1
#define FREE_PTE_NR 0
#endif
/*
* TLB handling. This allows us to remove pages from the page
@ -36,12 +54,58 @@
struct mmu_gather {
struct mm_struct *mm;
unsigned int fullmm;
struct vm_area_struct *vma;
unsigned long range_start;
unsigned long range_end;
unsigned int nr;
struct page *pages[FREE_PTE_NR];
};
DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
/*
* This is unnecessarily complex. There's three ways the TLB shootdown
* code is used:
* 1. Unmapping a range of vmas. See zap_page_range(), unmap_region().
* tlb->fullmm = 0, and tlb_start_vma/tlb_end_vma will be called.
* tlb->vma will be non-NULL.
* 2. Unmapping all vmas. See exit_mmap().
* tlb->fullmm = 1, and tlb_start_vma/tlb_end_vma will be called.
* tlb->vma will be non-NULL. Additionally, page tables will be freed.
* 3. Unmapping argument pages. See shift_arg_pages().
* tlb->fullmm = 0, but tlb_start_vma/tlb_end_vma will not be called.
* tlb->vma will be NULL.
*/
static inline void tlb_flush(struct mmu_gather *tlb)
{
if (tlb->fullmm || !tlb->vma)
flush_tlb_mm(tlb->mm);
else if (tlb->range_end > 0) {
flush_tlb_range(tlb->vma, tlb->range_start, tlb->range_end);
tlb->range_start = TASK_SIZE;
tlb->range_end = 0;
}
}
static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
{
if (!tlb->fullmm) {
if (addr < tlb->range_start)
tlb->range_start = addr;
if (addr + PAGE_SIZE > tlb->range_end)
tlb->range_end = addr + PAGE_SIZE;
}
}
static inline void tlb_flush_mmu(struct mmu_gather *tlb)
{
tlb_flush(tlb);
if (!tlb_fast_mode(tlb)) {
free_pages_and_swap_cache(tlb->pages, tlb->nr);
tlb->nr = 0;
}
}
static inline struct mmu_gather *
tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
{
@ -49,6 +113,8 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
tlb->mm = mm;
tlb->fullmm = full_mm_flush;
tlb->vma = NULL;
tlb->nr = 0;
return tlb;
}
@ -56,8 +122,7 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
static inline void
tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
{
if (tlb->fullmm)
flush_tlb_mm(tlb->mm);
tlb_flush_mmu(tlb);
/* keep the page table cache within bounds */
check_pgt_cache();
@ -71,12 +136,7 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
static inline void
tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long addr)
{
if (!tlb->fullmm) {
if (addr < tlb->range_start)
tlb->range_start = addr;
if (addr + PAGE_SIZE > tlb->range_end)
tlb->range_end = addr + PAGE_SIZE;
}
tlb_add_flush(tlb, addr);
}
/*
@ -89,6 +149,7 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
{
if (!tlb->fullmm) {
flush_cache_range(vma, vma->vm_start, vma->vm_end);
tlb->vma = vma;
tlb->range_start = TASK_SIZE;
tlb->range_end = 0;
}
@ -97,12 +158,30 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
static inline void
tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
{
if (!tlb->fullmm && tlb->range_end > 0)
flush_tlb_range(vma, tlb->range_start, tlb->range_end);
if (!tlb->fullmm)
tlb_flush(tlb);
}
#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
#define pte_free_tlb(tlb, ptep, addr) pte_free((tlb)->mm, ptep)
static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
if (tlb_fast_mode(tlb)) {
free_page_and_swap_cache(page);
} else {
tlb->pages[tlb->nr++] = page;
if (tlb->nr >= FREE_PTE_NR)
tlb_flush_mmu(tlb);
}
}
static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
unsigned long addr)
{
pgtable_page_dtor(pte);
tlb_add_flush(tlb, addr);
tlb_remove_page(tlb, pte);
}
#define pte_free_tlb(tlb, ptep, addr) __pte_free_tlb(tlb, ptep, addr)
#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp)
#define tlb_migrate_finish(mm) do { } while (0)

7
arch/arm/include/asm/tlbflush.h
View File

@ -10,12 +10,7 @@
#ifndef _ASMARM_TLBFLUSH_H
#define _ASMARM_TLBFLUSH_H
#ifndef CONFIG_MMU
#define tlb_flush(tlb) ((void) tlb)
#else /* CONFIG_MMU */
#ifdef CONFIG_MMU
#include <asm/glue.h>

2
arch/arm/kernel/kprobes-decode.c
View File

@ -1437,7 +1437,7 @@ arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
return space_cccc_1100_010x(insn, asi);
} else if ((insn & 0x0e000000) == 0x0c400000) {
} else if ((insn & 0x0e000000) == 0x0c000000) {
return space_cccc_110x(insn, asi);

7
arch/arm/kernel/machine_kexec.c
View File

@ -75,6 +75,11 @@ void machine_crash_shutdown(struct pt_regs *regs)
printk(KERN_INFO "Loading crashdump kernel...\n");
}
/*
* Function pointer to optional machine-specific reinitialization
*/
void (*kexec_reinit)(void);
void machine_kexec(struct kimage *image)
{
unsigned long page_list;
@ -104,6 +109,8 @@ void machine_kexec(struct kimage *image)
(unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
printk(KERN_INFO "Bye!\n");
if (kexec_reinit)
kexec_reinit();
local_irq_disable();
local_fiq_disable();
setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/

22
arch/arm/kernel/pmu.c
View File

@ -97,28 +97,34 @@ set_irq_affinity(int irq,
irq, cpu);
return err;
#else
return 0;
return -EINVAL;
#endif
}
static int
init_cpu_pmu(void)
{
int i, err = 0;
int i, irqs, err = 0;
struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU];
if (!pdev) {
err = -ENODEV;
goto out;
}
if (!pdev)
return -ENODEV;
for (i = 0; i < pdev->num_resources; ++i) {
irqs = pdev->num_resources;
/*
* If we have a single PMU interrupt that we can't shift, assume that
* we're running on a uniprocessor machine and continue.
*/
if (irqs == 1 && !irq_can_set_affinity(platform_get_irq(pdev, 0)))
return 0;
for (i = 0; i < irqs; ++i) {
err = set_irq_affinity(platform_get_irq(pdev, i), i);
if (err)
break;
}
out:
return err;
}

4
arch/arm/kernel/setup.c
View File

@ -226,8 +226,8 @@ int cpu_architecture(void)
* Register 0 and check for VMSAv7 or PMSAv7 */
asm("mrc p15, 0, %0, c0, c1, 4"
: "=r" (mmfr0));
if ((mmfr0 & 0x0000000f) == 0x00000003 ||
(mmfr0 & 0x000000f0) == 0x00000030)
if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
(mmfr0 & 0x000000f0) >= 0x00000030)
cpu_arch = CPU_ARCH_ARMv7;
else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
(mmfr0 & 0x000000f0) == 0x00000020)

4
arch/arm/kernel/signal.c
View File

@ -474,7 +474,9 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
unsigned long handler = (unsigned long)ka->sa.sa_handler;
unsigned long retcode;
int thumb = 0;
unsigned long cpsr = regs->ARM_cpsr & ~PSR_f;
unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
cpsr |= PSR_ENDSTATE;
/*
* Maybe we need to deliver a 32-bit signal to a 26-bit task.

11
arch/arm/kernel/vmlinux.lds.S
View File

@ -21,6 +21,12 @@
#define ARM_CPU_KEEP(x)
#endif
#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
#define ARM_EXIT_KEEP(x) x
#else
#define ARM_EXIT_KEEP(x)
#endif
OUTPUT_ARCH(arm)
ENTRY(stext)
@ -43,6 +49,7 @@ SECTIONS
_sinittext = .;
HEAD_TEXT
INIT_TEXT
ARM_EXIT_KEEP(EXIT_TEXT)
_einittext = .;
ARM_CPU_DISCARD(PROC_INFO)
__arch_info_begin = .;
@ -67,6 +74,7 @@ SECTIONS
#ifndef CONFIG_XIP_KERNEL
__init_begin = _stext;
INIT_DATA
ARM_EXIT_KEEP(EXIT_DATA)
#endif
}
@ -162,6 +170,7 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
__init_begin = .;
INIT_DATA
ARM_EXIT_KEEP(EXIT_DATA)
. = ALIGN(PAGE_SIZE);
__init_end = .;
#endif
@ -247,6 +256,8 @@ SECTIONS
}
#endif
NOTES
BSS_SECTION(0, 0, 0)
_end = .;

1
arch/arm/mach-dove/cm-a510.c
View File

@ -90,6 +90,7 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board")
.boot_params = 0x00000100,
.init_machine = cm_a510_init,
.map_io = dove_map_io,
.init_early = dove_init_early,
.init_irq = dove_init_irq,
.timer = &dove_timer,
MACHINE_END

8
arch/arm/mach-dove/common.c
View File

@ -532,6 +532,11 @@ void __init dove_i2c_init(void)
/*****************************************************************************
* Time handling
****************************************************************************/
void __init dove_init_early(void)
{
orion_time_set_base(TIMER_VIRT_BASE);
}
static int get_tclk(void)
{
/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
@ -540,7 +545,8 @@ static int get_tclk(void)
static void dove_timer_init(void)
{
orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_DOVE_BRIDGE, get_tclk());
}
struct sys_timer dove_timer = {

1
arch/arm/mach-dove/common.h
View File

@ -22,6 +22,7 @@ extern struct mbus_dram_target_info dove_mbus_dram_info;
*/
void dove_map_io(void);
void dove_init(void);
void dove_init_early(void);
void dove_init_irq(void);
void dove_setup_cpu_mbus(void);
void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);

1
arch/arm/mach-dove/dove-db-setup.c
View File

@ -97,6 +97,7 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
.boot_params = 0x00000100,
.init_machine = dove_db_init,
.map_io = dove_map_io,
.init_early = dove_init_early,
.init_irq = dove_init_irq,
.timer = &dove_timer,
MACHINE_END

4
arch/arm/mach-dove/include/mach/bridge-regs.h
View File

@ -26,10 +26,6 @@
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)

3
arch/arm/mach-dove/include/mach/dove.h
View File

@ -130,7 +130,8 @@
#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)

42
arch/arm/mach-dove/include/mach/gpio.h
View File

@ -6,46 +6,4 @@
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#include <asm/errno.h>
#include <mach/irqs.h>
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */
#define GPIO_MAX 72
#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00)
#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20)
#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : \
((pin < 64) ? GPIO_BASE_HI : \
DOVE_GPIO2_VIRT_BASE))
#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00)
#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04)
#define GPIO_BLINK_EN(pin) (GPIO_BASE(pin) + 0x08)
#define GPIO_IN_POL(pin) (GPIO_BASE(pin) + 0x0c)
#define GPIO_DATA_IN(pin) (GPIO_BASE(pin) + 0x10)
#define GPIO_EDGE_CAUSE(pin) (GPIO_BASE(pin) + 0x14)
#define GPIO_EDGE_MASK(pin) (GPIO_BASE(pin) + 0x18)
#define GPIO_LEVEL_MASK(pin) (GPIO_BASE(pin) + 0x1c)
static inline int gpio_to_irq(int pin)
{
if (pin < NR_GPIO_IRQS)
return pin + IRQ_DOVE_GPIO_START;
return -EINVAL;
}
static inline int irq_to_gpio(int irq)
{
if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
return irq - IRQ_DOVE_GPIO_START;
return -EINVAL;
}
#endif

7
arch/arm/mach-dove/include/mach/irqs.h
View File

@ -92,10 +92,5 @@
#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
/* Required for compatability with PXA AC97 driver. */
#define IRQ_AC97 IRQ_DOVE_AC97
/* Required for compatability with PXA DMA driver. */
#define IRQ_DMA IRQ_DOVE_PDMA
/* Required for compatability with PXA NAND driver */
#define IRQ_NAND IRQ_DOVE_NAND
#endif

30
arch/arm/mach-dove/irq.c
View File

@ -99,11 +99,21 @@ void __init dove_init_irq(void)
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
/*
* Mask and clear GPIO IRQ interrupts.
* Initialize gpiolib for GPIOs 0-71.
*/
writel(0, GPIO_LEVEL_MASK(0));
writel(0, GPIO_EDGE_MASK(0));
writel(0, GPIO_EDGE_CAUSE(0));
orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START);
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 32);
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 64);
/*
* Mask and clear PMU interrupts
@ -111,18 +121,6 @@ void __init dove_init_irq(void)
writel(0, PMU_INTERRUPT_MASK);
writel(0, PMU_INTERRUPT_CAUSE);
for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
set_irq_chip(i, &pmu_irq_chip);
set_irq_handler(i, handle_level_irq);

16
arch/arm/mach-kirkwood/common.c
View File

@ -21,6 +21,7 @@
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/kexec.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/kirkwood.h>
@ -846,9 +847,14 @@ static void __init kirkwood_wdt_init(void)
/*****************************************************************************
* Time handling
****************************************************************************/
void __init kirkwood_init_early(void)
{
orion_time_set_base(TIMER_VIRT_BASE);
}
int kirkwood_tclk;
int __init kirkwood_find_tclk(void)
static int __init kirkwood_find_tclk(void)
{
u32 dev, rev;
@ -864,7 +870,9 @@ int __init kirkwood_find_tclk(void)
static void __init kirkwood_timer_init(void)
{
kirkwood_tclk = kirkwood_find_tclk();
orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
}
struct sys_timer kirkwood_timer = {
@ -1003,6 +1011,10 @@ void __init kirkwood_init(void)
kirkwood_xor0_init();
kirkwood_xor1_init();
kirkwood_crypto_init();
#ifdef CONFIG_KEXEC
kexec_reinit = kirkwood_enable_pcie;
#endif
}
static int __init kirkwood_clock_gate(void)

2
arch/arm/mach-kirkwood/common.h
View File

@ -27,11 +27,13 @@ struct kirkwood_asoc_platform_data;
*/
void kirkwood_map_io(void);
void kirkwood_init(void);
void kirkwood_init_early(void);
void kirkwood_init_irq(void);
extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
void kirkwood_setup_cpu_mbus(void);
void kirkwood_enable_pcie(void);
void kirkwood_pcie_id(u32 *dev, u32 *rev);
void kirkwood_ehci_init(void);

1
arch/arm/mach-kirkwood/d2net_v2-setup.c
View File

@ -224,6 +224,7 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
.boot_params = 0x00000100,
.init_machine = d2net_v2_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

1
arch/arm/mach-kirkwood/db88f6281-bp-setup.c
View File

@ -100,6 +100,7 @@ MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
.boot_params = 0x00000100,
.init_machine = db88f6281_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

1
arch/arm/mach-kirkwood/dockstar-setup.c
View File

@ -105,6 +105,7 @@ MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
.boot_params = 0x00000100,
.init_machine = dockstar_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

1
arch/arm/mach-kirkwood/guruplug-setup.c
View File

@ -124,6 +124,7 @@ MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
.boot_params = 0x00000100,
.init_machine = guruplug_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

3
arch/arm/mach-kirkwood/include/mach/bridge-regs.h
View File

@ -29,9 +29,6 @@
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define WDT_INT_REQ 0x0008
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)

29
arch/arm/mach-kirkwood/include/mach/gpio.h
View File

@ -6,33 +6,4 @@
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#include <mach/irqs.h>
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */
#define GPIO_MAX 50
#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0140 : 0x0100)
#define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x00)
#define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x04)
#define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x08)
#define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x0c)
#define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x10)
#define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x14)
#define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x18)
#define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x1c)
static inline int gpio_to_irq(int pin)
{
return pin + IRQ_KIRKWOOD_GPIO_START;
}
static inline int irq_to_gpio(int irq)
{
return irq - IRQ_KIRKWOOD_GPIO_START;
}
#endif

2
arch/arm/mach-kirkwood/include/mach/kirkwood.h
View File

@ -69,6 +69,8 @@
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140)
#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)

22
arch/arm/mach-kirkwood/irq.c
View File

@ -27,31 +27,21 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
void __init kirkwood_init_irq(void)
{
int i;
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
/*
* Mask and clear GPIO IRQ interrupts.
* Initialize gpiolib for GPIOs 0-49.
*/
writel(0, GPIO_LEVEL_MASK(0));
writel(0, GPIO_EDGE_MASK(0));
writel(0, GPIO_EDGE_CAUSE(0));
writel(0, GPIO_LEVEL_MASK(32));
writel(0, GPIO_EDGE_MASK(32));
writel(0, GPIO_EDGE_CAUSE(32));
for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START + 32);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);

3
arch/arm/mach-kirkwood/mpp.c
View File

@ -49,9 +49,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
if (!variant_mask)
return;
/* Initialize gpiolib. */
orion_gpio_init();
printk(KERN_DEBUG "initial MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
mpp_ctrl[i] = readl(MPP_CTRL(i));

1
arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
View File

@ -166,6 +166,7 @@ MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
.boot_params = 0x00000100,
.init_machine = mv88f6281gtw_ge_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

3
arch/arm/mach-kirkwood/netspace_v2-setup.c
View File

@ -261,6 +261,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
.boot_params = 0x00000100,
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
@ -271,6 +272,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
.boot_params = 0x00000100,
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
@ -281,6 +283,7 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
.boot_params = 0x00000100,
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

2
arch/arm/mach-kirkwood/netxbig_v2-setup.c
View File

@ -402,6 +402,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
.boot_params = 0x00000100,
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
@ -412,6 +413,7 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
.boot_params = 0x00000100,
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

3
arch/arm/mach-kirkwood/openrd-setup.c
View File

@ -217,6 +217,7 @@ MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
.boot_params = 0x00000100,
.init_machine = openrd_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
@ -228,6 +229,7 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
.boot_params = 0x00000100,
.init_machine = openrd_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
@ -239,6 +241,7 @@ MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
.boot_params = 0x00000100,
.init_machine = openrd_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

8
arch/arm/mach-kirkwood/pcie.c
View File

@ -18,8 +18,16 @@
#include <mach/bridge-regs.h>
#include "common.h"
void kirkwood_enable_pcie(void)
{
u32 curr = readl(CLOCK_GATING_CTRL);
if (!(curr & CGC_PEX0))
writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
}
void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
{
kirkwood_enable_pcie();
*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
}

1
arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
View File

@ -82,6 +82,7 @@ MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
.boot_params = 0x00000100,
.init_machine = rd88f6192_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

1
arch/arm/mach-kirkwood/rd88f6281-setup.c
View File

@ -118,6 +118,7 @@ MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
.boot_params = 0x00000100,
.init_machine = rd88f6281_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

2
arch/arm/mach-kirkwood/sheevaplug-setup.c
View File

@ -134,6 +134,7 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
.boot_params = 0x00000100,
.init_machine = sheevaplug_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
@ -144,6 +145,7 @@ MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
.boot_params = 0x00000100,
.init_machine = sheevaplug_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

18
arch/arm/mach-kirkwood/t5325-setup.c
View File

@ -23,6 +23,7 @@
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <sound/alc5623.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/kirkwood.h>
@ -134,6 +135,7 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
MPP33_GE1_TXCTL,
MPP39_AU_I2SBCLK,
MPP40_AU_I2SDO,
MPP43_AU_I2SDI,
MPP41_AU_I2SLRCLK,
MPP42_AU_I2SMCLK,
MPP45_GPIO, /* Power button */
@ -141,6 +143,18 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
0
};
static struct alc5623_platform_data alc5621_data = {
.add_ctrl = 0x3700,
.jack_det_ctrl = 0x4810,
};
static struct i2c_board_info i2c_board_info[] __initdata = {
{
I2C_BOARD_INFO("alc5621", 0x1a),
.platform_data = &alc5621_data,
},
};
#define HP_T5325_GPIO_POWER_OFF 48
static void hp_t5325_power_off(void)
@ -166,6 +180,9 @@ static void __init hp_t5325_init(void)
kirkwood_ehci_init();
platform_device_register(&hp_t5325_button_device);
i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
kirkwood_audio_init();
if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
pm_power_off = hp_t5325_power_off;
@ -187,6 +204,7 @@ MACHINE_START(T5325, "HP t5325 Thin Client")
.boot_params = 0x00000100,
.init_machine = hp_t5325_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

1
arch/arm/mach-kirkwood/ts219-setup.c
View File

@ -135,6 +135,7 @@ MACHINE_START(TS219, "QNAP TS-119/TS-219")
.boot_params = 0x00000100,
.init_machine = qnap_ts219_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

9
arch/arm/mach-kirkwood/ts41x-setup.c
View File

@ -154,6 +154,8 @@ static void __init qnap_ts41x_init(void)
static int __init ts41x_pci_init(void)
{
if (machine_is_ts41x()) {
u32 dev, rev;
/*
* Without this explicit reset, the PCIe SATA controller
* (Marvell 88sx7042/sata_mv) is known to stop working
@ -161,7 +163,11 @@ static int __init ts41x_pci_init(void)
*/
orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
kirkwood_pcie_init(KW_PCIE0);
kirkwood_pcie_id(&dev, &rev);
if (dev == MV88F6282_DEV_ID)
kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
else
kirkwood_pcie_init(KW_PCIE0);
}
return 0;
@ -173,6 +179,7 @@ MACHINE_START(TS41X, "QNAP TS-41x")
.boot_params = 0x00000100,
.init_machine = qnap_ts41x_init,
.map_io = kirkwood_map_io,
.init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

9
arch/arm/mach-loki/common.c
View File

@ -18,6 +18,7 @@
#include <asm/timex.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/bridge-regs.h>
#include <mach/loki.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
@ -290,9 +291,15 @@ void __init loki_uart1_init(void)
/*****************************************************************************
* Time handling
****************************************************************************/
void __init loki_init_early(void)
{
orion_time_set_base(TIMER_VIRT_BASE);
}
static void loki_timer_init(void)
{
orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_LOKI_BRIDGE, LOKI_TCLK);
}
struct sys_timer loki_timer = {

1
arch/arm/mach-loki/common.h
View File

@ -18,6 +18,7 @@ struct mv643xx_eth_platform_data;
*/
void loki_map_io(void);
void loki_init(void);
void loki_init_early(void);
void loki_init_irq(void);
extern struct mbus_dram_target_info loki_mbus_dram_info;

5
arch/arm/mach-loki/include/mach/bridge-regs.h
View File

@ -17,11 +17,6 @@
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR 0x0004
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)

1
arch/arm/mach-loki/lb88rc8480-setup.c
View File

@ -93,6 +93,7 @@ MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
.boot_params = 0x00000100,
.init_machine = lb88rc8480_init,
.map_io = loki_map_io,
.init_early = loki_init_early,
.init_irq = loki_init_irq,
.timer = &loki_timer,
MACHINE_END

1
arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
View File

@ -148,6 +148,7 @@ MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
.boot_params = 0x00000100,
.init_machine = wxl_init,
.map_io = mv78xx0_map_io,
.init_early = mv78xx0_init_early,
.init_irq = mv78xx0_init_irq,
.timer = &mv78xx0_timer,
MACHINE_END

8
arch/arm/mach-mv78xx0/common.c
View File

@ -818,9 +818,15 @@ void __init mv78xx0_uart3_init(void)
/*****************************************************************************
* Time handling
****************************************************************************/
void __init mv78xx0_init_early(void)
{
orion_time_set_base(TIMER_VIRT_BASE);
}
static void mv78xx0_timer_init(void)
{
orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_MV78XX0_TIMER_1, get_tclk());
}
struct sys_timer mv78xx0_timer = {

1
arch/arm/mach-mv78xx0/common.h
View File

@ -20,6 +20,7 @@ struct mv_sata_platform_data;
int mv78xx0_core_index(void);
void mv78xx0_map_io(void);
void mv78xx0_init(void);
void mv78xx0_init_early(void);
void mv78xx0_init_irq(void);
extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;

1
arch/arm/mach-mv78xx0/db78x00-bp-setup.c
View File

@ -96,6 +96,7 @@ MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
.boot_params = 0x00000100,
.init_machine = db78x00_init,
.map_io = mv78xx0_map_io,
.init_early = mv78xx0_init_early,
.init_irq = mv78xx0_init_irq,
.timer = &mv78xx0_timer,
MACHINE_END

4
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
View File

@ -20,10 +20,6 @@
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)

31
arch/arm/mach-mv78xx0/include/mach/gpio.h
View File

@ -6,35 +6,4 @@
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#include <mach/irqs.h>
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */
extern int mv78xx0_core_index(void);
#define GPIO_MAX 32
#define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + 0x0100)
#define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + 0x0104)
#define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + 0x0108)
#define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + 0x010c)
#define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + 0x0110)
#define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + 0x0114)
#define GPIO_MASK_OFF (mv78xx0_core_index() ? 0x18 : 0)
#define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + 0x0118 + GPIO_MASK_OFF)
#define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + 0x011c + GPIO_MASK_OFF)
static inline int gpio_to_irq(int pin)
{
return pin + IRQ_MV78XX0_GPIO_START;
}
static inline int irq_to_gpio(int irq)
{
return irq - IRQ_MV78XX0_GPIO_START;
}
#endif

1
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
View File

@ -71,6 +71,7 @@
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)

22
arch/arm/mach-mv78xx0/irq.c
View File

@ -26,28 +26,18 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
void __init mv78xx0_init_irq(void)
{
int i;
/* Initialize gpiolib. */
orion_gpio_init();
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
/*
* Mask and clear GPIO IRQ interrupts.
* Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
* registers for core #1 are at an offset of 0x18 from those of
* core #0.)
*/
writel(0, GPIO_LEVEL_MASK(0));
writel(0, GPIO_EDGE_MASK(0));
writel(0, GPIO_EDGE_CAUSE(0));
for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
orion_gpio_init(0, 32, GPIO_VIRT_BASE,
mv78xx0_core_index() ? 0x18 : 0,
IRQ_MV78XX0_GPIO_START);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);

3
arch/arm/mach-mv78xx0/mpp.c
View File

@ -44,9 +44,6 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
if (!variant_mask)
return;
/* Initialize gpiolib. */
orion_gpio_init();
printk(KERN_DEBUG "initial MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
mpp_ctrl[i] = readl(MPP_CTRL(i));

1
arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
View File

@ -81,6 +81,7 @@ MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
.boot_params = 0x00000100,
.init_machine = rd78x00_masa_init,
.map_io = mv78xx0_map_io,
.init_early = mv78xx0_init_early,
.init_irq = mv78xx0_init_irq,
.timer = &mv78xx0_timer,
MACHINE_END

10
arch/arm/mach-orion5x/common.c
View File

@ -26,6 +26,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/bridge-regs.h>
#include <mach/hardware.h>
#include <mach/orion5x.h>
#include <plat/ehci-orion.h>
@ -599,6 +600,11 @@ void __init orion5x_wdt_init(void)
/*****************************************************************************
* Time handling
****************************************************************************/
void __init orion5x_init_early(void)
{
orion_time_set_base(TIMER_VIRT_BASE);
}
int orion5x_tclk;
int __init orion5x_find_tclk(void)
@ -616,7 +622,9 @@ int __init orion5x_find_tclk(void)
static void orion5x_timer_init(void)
{
orion5x_tclk = orion5x_find_tclk();
orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_ORION5X_BRIDGE, orion5x_tclk);
}
struct sys_timer orion5x_timer = {

1
arch/arm/mach-orion5x/common.h
View File

@ -9,6 +9,7 @@ struct mv_sata_platform_data;
* Basic Orion init functions used early by machine-setup.
*/
void orion5x_map_io(void);
void orion5x_init_early(void);
void orion5x_init_irq(void);
void orion5x_init(void);
extern int orion5x_tclk;

2
arch/arm/mach-orion5x/d2net-setup.c
View File

@ -339,6 +339,7 @@ MACHINE_START(D2NET, "LaCie d2 Network")
.boot_params = 0x00000100,
.init_machine = d2net_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
@ -350,6 +351,7 @@ MACHINE_START(BIGDISK, "LaCie Big Disk Network")
.boot_params = 0x00000100,
.init_machine = d2net_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/db88f5281-setup.c
View File

@ -361,6 +361,7 @@ MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
.boot_params = 0x00000100,
.init_machine = db88f5281_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
MACHINE_END

1
arch/arm/mach-orion5x/dns323-setup.c
View File

@ -733,6 +733,7 @@ MACHINE_START(DNS323, "D-Link DNS-323")
.boot_params = 0x00000100,
.init_machine = dns323_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/edmini_v2-setup.c
View File

@ -254,6 +254,7 @@ MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
.boot_params = 0x00000100,
.init_machine = edmini_v2_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

6
arch/arm/mach-orion5x/include/mach/bridge-regs.h
View File

@ -22,14 +22,12 @@
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
#define WDT_INT_REQ 0x0008
#define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)

28
arch/arm/mach-orion5x/include/mach/gpio.h
View File

@ -6,32 +6,4 @@
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#include <mach/irqs.h>
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */
#define GPIO_MAX 32
#define GPIO_OUT(pin) ORION5X_DEV_BUS_REG(0x100)
#define GPIO_IO_CONF(pin) ORION5X_DEV_BUS_REG(0x104)
#define GPIO_BLINK_EN(pin) ORION5X_DEV_BUS_REG(0x108)
#define GPIO_IN_POL(pin) ORION5X_DEV_BUS_REG(0x10c)
#define GPIO_DATA_IN(pin) ORION5X_DEV_BUS_REG(0x110)
#define GPIO_EDGE_CAUSE(pin) ORION5X_DEV_BUS_REG(0x114)
#define GPIO_EDGE_MASK(pin) ORION5X_DEV_BUS_REG(0x118)
#define GPIO_LEVEL_MASK(pin) ORION5X_DEV_BUS_REG(0x11c)
static inline int gpio_to_irq(int pin)
{
return pin + IRQ_ORION5X_GPIO_START;
}
static inline int irq_to_gpio(int irq)
{
return irq - IRQ_ORION5X_GPIO_START;
}
#endif

1
arch/arm/mach-orion5x/include/mach/orion5x.h
View File

@ -73,6 +73,7 @@
#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)

19
arch/arm/mach-orion5x/irq.c
View File

@ -28,27 +28,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
void __init orion5x_init_irq(void)
{
int i;
orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
/*
* Mask and clear GPIO IRQ interrupts
* Initialize gpiolib for GPIOs 0-31.
*/
writel(0x0, GPIO_LEVEL_MASK(0));
writel(0x0, GPIO_EDGE_MASK(0));
writel(0x0, GPIO_EDGE_CAUSE(0));
/*
* Register chained level handlers for GPIO IRQs by default.
* User can use set_type() if he wants to use edge types handlers.
*/
for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);

2
arch/arm/mach-orion5x/kurobox_pro-setup.c
View File

@ -382,6 +382,7 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
@ -394,6 +395,7 @@ MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/ls-chl-setup.c
View File

@ -321,6 +321,7 @@ MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
.boot_params = 0x00000100,
.init_machine = lschl_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/ls_hgl-setup.c
View File

@ -268,6 +268,7 @@ MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
.boot_params = 0x00000100,
.init_machine = ls_hgl_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/lsmini-setup.c
View File

@ -270,6 +270,7 @@ MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
.boot_params = 0x00000100,
.init_machine = lsmini_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

3
arch/arm/mach-orion5x/mpp.c
View File

@ -124,9 +124,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
/* Initialize gpiolib. */
orion_gpio_init();
for ( ; mode->mpp >= 0; mode++) {
u32 *reg;
int num_type;

1
arch/arm/mach-orion5x/mss2-setup.c
View File

@ -264,6 +264,7 @@ MACHINE_START(MSS2, "Maxtor Shared Storage II")
.boot_params = 0x00000100,
.init_machine = mss2_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32

1
arch/arm/mach-orion5x/mv2120-setup.c
View File

@ -232,6 +232,7 @@ MACHINE_START(MV2120, "HP Media Vault mv2120")
.boot_params = 0x00000100,
.init_machine = mv2120_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32

1
arch/arm/mach-orion5x/net2big-setup.c
View File

@ -422,6 +422,7 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network")
.boot_params = 0x00000100,
.init_machine = net2big_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
View File

@ -172,6 +172,7 @@ MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
.boot_params = 0x00000100,
.init_machine = rd88f5181l_fxo_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
View File

@ -184,6 +184,7 @@ MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
.boot_params = 0x00000100,
.init_machine = rd88f5181l_ge_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/rd88f5182-setup.c
View File

@ -308,6 +308,7 @@ MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
.boot_params = 0x00000100,
.init_machine = rd88f5182_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
MACHINE_END

1
arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
View File

@ -126,6 +126,7 @@ MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
.boot_params = 0x00000100,
.init_machine = rd88f6183ap_ge_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/terastation_pro2-setup.c
View File

@ -361,6 +361,7 @@ MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
.boot_params = 0x00000100,
.init_machine = tsp2_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/ts209-setup.c
View File

@ -325,6 +325,7 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209")
.boot_params = 0x00000100,
.init_machine = qnap_ts209_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/ts409-setup.c
View File

@ -314,6 +314,7 @@ MACHINE_START(TS409, "QNAP TS-409")
.boot_params = 0x00000100,
.init_machine = qnap_ts409_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

15
arch/arm/mach-orion5x/ts78xx-fpga.h
View File

@ -1,3 +1,4 @@
#define TS7800_FPGA_MAGIC 0x00b480
#define FPGAID(_magic, _rev) ((_magic << 8) + _rev)
/*
@ -6,11 +7,15 @@
*/
enum fpga_ids {
/* Technologic Systems */
TS7800_REV_1 = FPGAID(0x00b480, 0x01),
TS7800_REV_2 = FPGAID(0x00b480, 0x02),
TS7800_REV_3 = FPGAID(0x00b480, 0x03),
TS7800_REV_4 = FPGAID(0x00b480, 0x04),
TS7800_REV_5 = FPGAID(0x00b480, 0x05),
TS7800_REV_1 = FPGAID(TS7800_FPGA_MAGIC, 0x01),
TS7800_REV_2 = FPGAID(TS7800_FPGA_MAGIC, 0x02),
TS7800_REV_3 = FPGAID(TS7800_FPGA_MAGIC, 0x03),
TS7800_REV_4 = FPGAID(TS7800_FPGA_MAGIC, 0x04),
TS7800_REV_5 = FPGAID(TS7800_FPGA_MAGIC, 0x05),
TS7800_REV_6 = FPGAID(TS7800_FPGA_MAGIC, 0x06),
TS7800_REV_7 = FPGAID(TS7800_FPGA_MAGIC, 0x07),
TS7800_REV_8 = FPGAID(TS7800_FPGA_MAGIC, 0x08),
TS7800_REV_9 = FPGAID(TS7800_FPGA_MAGIC, 0x09),
/* Unaffordable & Expensive */
UAE_DUMMY = FPGAID(0xffffff, 0x01),

78
arch/arm/mach-orion5x/ts78xx-setup.c
View File

@ -191,6 +191,60 @@ static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
return readb(TS_NAND_CTRL) & 0x20;
}
static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
const uint8_t *buf, int len)
{
struct nand_chip *chip = mtd->priv;
void __iomem *io_base = chip->IO_ADDR_W;
unsigned long off = ((unsigned long)buf & 3);
int sz;
if (off) {
sz = min_t(int, 4 - off, len);
writesb(io_base, buf, sz);
buf += sz;
len -= sz;
}
sz = len >> 2;
if (sz) {
u32 *buf32 = (u32 *)buf;
writesl(io_base, buf32, sz);
buf += sz << 2;
len -= sz << 2;
}
if (len)
writesb(io_base, buf, len);
}
static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
uint8_t *buf, int len)
{
struct nand_chip *chip = mtd->priv;
void __iomem *io_base = chip->IO_ADDR_R;
unsigned long off = ((unsigned long)buf & 3);
int sz;
if (off) {
sz = min_t(int, 4 - off, len);
readsb(io_base, buf, sz);
buf += sz;
len -= sz;
}
sz = len >> 2;
if (sz) {
u32 *buf32 = (u32 *)buf;
readsl(io_base, buf32, sz);
buf += sz << 2;
len -= sz << 2;
}
if (len)
readsb(io_base, buf, len);
}
const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
static struct mtd_partition ts78xx_ts_nand_parts[] = {
@ -233,6 +287,8 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
*/
.cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
.dev_ready = ts78xx_ts_nand_dev_ready,
.write_buf = ts78xx_ts_nand_write_buf,
.read_buf = ts78xx_ts_nand_read_buf,
},
};
@ -334,14 +390,29 @@ static void ts78xx_fpga_supports(void)
case TS7800_REV_3:
case TS7800_REV_4:
case TS7800_REV_5:
case TS7800_REV_6:
case TS7800_REV_7:
case TS7800_REV_8:
case TS7800_REV_9:
ts78xx_fpga.supports.ts_rtc.present = 1;
ts78xx_fpga.supports.ts_nand.present = 1;
ts78xx_fpga.supports.ts_rng.present = 1;
break;
default:
ts78xx_fpga.supports.ts_rtc.present = 0;
ts78xx_fpga.supports.ts_nand.present = 0;
ts78xx_fpga.supports.ts_rng.present = 0;
/* enable devices if magic matches */
switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
case TS7800_FPGA_MAGIC:
printk(KERN_WARNING "TS-7800 FPGA: unrecognized revision 0x%.2x\n",
ts78xx_fpga.id & 0xff);
ts78xx_fpga.supports.ts_rtc.present = 1;
ts78xx_fpga.supports.ts_nand.present = 1;
ts78xx_fpga.supports.ts_rng.present = 1;
break;
default:
ts78xx_fpga.supports.ts_rtc.present = 0;
ts78xx_fpga.supports.ts_nand.present = 0;
ts78xx_fpga.supports.ts_rng.present = 0;
}
}
}
@ -553,6 +624,7 @@ MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
.boot_params = 0x00000100,
.init_machine = ts78xx_init,
.map_io = ts78xx_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
MACHINE_END

1
arch/arm/mach-orion5x/wnr854t-setup.c
View File

@ -175,6 +175,7 @@ MACHINE_START(WNR854T, "Netgear WNR854T")
.boot_params = 0x00000100,
.init_machine = wnr854t_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

1
arch/arm/mach-orion5x/wrt350n-v2-setup.c
View File

@ -263,6 +263,7 @@ MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
.boot_params = 0x00000100,
.init_machine = wrt350n_v2_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,

71
arch/arm/mach-s5p6442/include/mach/map.h
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s5p6442/include/mach/map.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Memory map definitions
@ -16,56 +16,61 @@
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5P6442_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5P6442_PA_CHIPID
#define S5P6442_PA_SDRAM 0x20000000
#define S5P6442_PA_SYSCON (0xE0100000)
#define S5P_PA_SYSCON S5P6442_PA_SYSCON
#define S5P6442_PA_I2S0 0xC0B00000
#define S5P6442_PA_I2S1 0xF2200000
#define S5P6442_PA_GPIO (0xE0200000)
#define S5P6442_PA_CHIPID 0xE0000000
#define S5P6442_PA_VIC0 (0xE4000000)
#define S5P6442_PA_VIC1 (0xE4100000)
#define S5P6442_PA_VIC2 (0xE4200000)
#define S5P6442_PA_SYSCON 0xE0100000
#define S5P6442_PA_SROMC (0xE7000000)
#define S5P_PA_SROMC S5P6442_PA_SROMC
#define S5P6442_PA_GPIO 0xE0200000
#define S5P6442_PA_VIC0 0xE4000000
#define S5P6442_PA_VIC1 0xE4100000
#define S5P6442_PA_VIC2 0xE4200000
#define S5P6442_PA_SROMC 0xE7000000
#define S5P6442_PA_MDMA 0xE8000000
#define S5P6442_PA_PDMA 0xE9000000
#define S5P6442_PA_TIMER (0xEA000000)
#define S5P_PA_TIMER S5P6442_PA_TIMER
#define S5P6442_PA_TIMER 0xEA000000
#define S5P6442_PA_SYSTIMER (0xEA100000)
#define S5P6442_PA_SYSTIMER 0xEA100000
#define S5P6442_PA_WATCHDOG (0xEA200000)
#define S5P6442_PA_WATCHDOG 0xEA200000
#define S5P6442_PA_UART (0xEC000000)
#define S5P6442_PA_UART 0xEC000000
#define S5P_PA_UART0 (S5P6442_PA_UART + 0x0)
#define S5P_PA_UART1 (S5P6442_PA_UART + 0x400)
#define S5P_PA_UART2 (S5P6442_PA_UART + 0x800)
#define S5P_SZ_UART SZ_256
#define S5P6442_PA_IIC0 (0xEC100000)
#define S5P6442_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5P6442_PA_SDRAM
#define S5P6442_PA_IIC0 0xEC100000
#define S5P6442_PA_SPI 0xEC300000
/* I2S */
#define S5P6442_PA_I2S0 0xC0B00000
#define S5P6442_PA_I2S1 0xF2200000
/* PCM */
#define S5P6442_PA_PCM0 0xF2400000
#define S5P6442_PA_PCM1 0xF2500000
/* compatibiltiy defines. */
#define S3C_PA_WDT S5P6442_PA_WATCHDOG
#define S3C_PA_UART S5P6442_PA_UART
/* Compatibiltiy Defines */
#define S3C_PA_IIC S5P6442_PA_IIC0
#define S3C_PA_WDT S5P6442_PA_WATCHDOG
#define S5P_PA_CHIPID S5P6442_PA_CHIPID
#define S5P_PA_SDRAM S5P6442_PA_SDRAM
#define S5P_PA_SROMC S5P6442_PA_SROMC
#define S5P_PA_SYSCON S5P6442_PA_SYSCON
#define S5P_PA_TIMER S5P6442_PA_TIMER
/* UART */
#define S3C_PA_UART S5P6442_PA_UART
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

103
arch/arm/mach-s5p64x0/include/mach/map.h
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Memory map definitions
@ -16,30 +16,63 @@
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5P64X0_PA_SDRAM (0x20000000)
#define S5P64X0_PA_SDRAM 0x20000000
#define S5P64X0_PA_CHIPID 0xE0000000
#define S5P64X0_PA_SYSCON 0xE0100000
#define S5P64X0_PA_GPIO 0xE0308000
#define S5P64X0_PA_VIC0 0xE4000000
#define S5P64X0_PA_VIC1 0xE4100000
#define S5P64X0_PA_SROMC 0xE7000000
#define S5P64X0_PA_PDMA 0xE9000000
#define S5P64X0_PA_TIMER 0xEA000000
#define S5P64X0_PA_RTC 0xEA100000
#define S5P64X0_PA_WDT 0xEA200000
#define S5P6440_PA_IIC0 0xEC104000
#define S5P6440_PA_IIC1 0xEC20F000
#define S5P6450_PA_IIC0 0xEC100000
#define S5P6450_PA_IIC1 0xEC200000
#define S5P64X0_PA_SPI0 0xEC400000
#define S5P64X0_PA_SPI1 0xEC500000
#define S5P64X0_PA_HSOTG 0xED100000
#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5P64X0_PA_I2S 0xF2000000
#define S5P6450_PA_I2S1 0xF2800000
#define S5P6450_PA_I2S2 0xF2900000
#define S5P64X0_PA_PCM 0xF2100000
#define S5P64X0_PA_ADC 0xF3000000
/* Compatibiltiy Defines */
#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
#define S3C_PA_IIC S5P6440_PA_IIC0
#define S3C_PA_IIC1 S5P6440_PA_IIC1
#define S3C_PA_RTC S5P64X0_PA_RTC
#define S3C_PA_WDT S5P64X0_PA_WDT
#define S5P64X0_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
#define S5P64X0_PA_SYSCON (0xE0100000)
#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
#define S5P64X0_PA_GPIO (0xE0308000)
#define S5P64X0_PA_VIC0 (0xE4000000)
#define S5P64X0_PA_VIC1 (0xE4100000)
#define S5P64X0_PA_SROMC (0xE7000000)
#define S5P_PA_SROMC S5P64X0_PA_SROMC
#define S5P64X0_PA_PDMA (0xE9000000)
#define S5P64X0_PA_TIMER (0xEA000000)
#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
#define S5P_PA_TIMER S5P64X0_PA_TIMER
#define S5P64X0_PA_RTC (0xEA100000)
#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
#define S5P64X0_PA_WDT (0xEA200000)
/* UART */
#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
@ -53,36 +86,4 @@
#define S5P_SZ_UART SZ_256
#define S5P6440_PA_IIC0 (0xEC104000)
#define S5P6440_PA_IIC1 (0xEC20F000)
#define S5P6450_PA_IIC0 (0xEC100000)
#define S5P6450_PA_IIC1 (0xEC200000)
#define S5P64X0_PA_SPI0 (0xEC400000)
#define S5P64X0_PA_SPI1 (0xEC500000)
#define S5P64X0_PA_HSOTG (0xED100000)
#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5P64X0_PA_I2S (0xF2000000)
#define S5P6450_PA_I2S1 0xF2800000
#define S5P6450_PA_I2S2 0xF2900000
#define S5P64X0_PA_PCM (0xF2100000)
#define S5P64X0_PA_ADC (0xF3000000)
/* compatibiltiy defines. */
#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
#define S3C_PA_IIC S5P6440_PA_IIC0
#define S3C_PA_IIC1 S5P6440_PA_IIC1
#define S3C_PA_RTC S5P64X0_PA_RTC
#define S3C_PA_WDT S5P64X0_PA_WDT
#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
#endif /* __ASM_ARCH_MAP_H */

191
arch/arm/mach-s5pc100/include/mach/map.h
View File

@ -1,4 +1,7 @@
/* linux/arch/arm/mach-s5pc100/include/mach/map.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
@ -16,145 +19,115 @@
#include <plat/map-base.h>
#include <plat/map-s5p.h>
/*
* map-base.h has already defined virtual memory address
* S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s)
* S3C_VA_SYS S3C_ADDR(0x00100000) system control
* S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used)
* S3C_VA_TIMER S3C_ADDR(0x00300000) timer block
* S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
* S3C_VA_UART S3C_ADDR(0x01000000) UART
*
* S5PC100 specific virtual memory address can be defined here
* S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
*
*/
#define S5PC100_PA_SDRAM 0x20000000
#define S5PC100_PA_ONENAND_BUF (0xB0000000)
#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
#define S5PC100_PA_ONENAND 0xE7100000
#define S5PC100_PA_ONENAND_BUF 0xB0000000
/* Chip ID */
#define S5PC100_PA_CHIPID 0xE0000000
#define S5PC100_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5PC100_PA_CHIPID
#define S5PC100_PA_SYSCON 0xE0100000
#define S5PC100_PA_SYSCON (0xE0100000)
#define S5P_PA_SYSCON S5PC100_PA_SYSCON
#define S5PC100_PA_OTHERS 0xE0200000
#define S5PC100_PA_OTHERS (0xE0200000)
#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
#define S5PC100_PA_GPIO 0xE0300000
#define S5PC100_PA_GPIO (0xE0300000)
#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
#define S5PC100_PA_VIC0 0xE4000000
#define S5PC100_PA_VIC1 0xE4100000
#define S5PC100_PA_VIC2 0xE4200000
/* Interrupt */
#define S5PC100_PA_VIC0 (0xE4000000)
#define S5PC100_PA_VIC1 (0xE4100000)
#define S5PC100_PA_VIC2 (0xE4200000)
#define S5PC100_VA_VIC S3C_VA_IRQ
#define S5PC100_VA_VIC_OFFSET 0x10000
#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
#define S5PC100_PA_SROMC 0xE7000000
#define S5PC100_PA_SROMC (0xE7000000)
#define S5P_PA_SROMC S5PC100_PA_SROMC
#define S5PC100_PA_CFCON 0xE7800000
#define S5PC100_PA_ONENAND (0xE7100000)
#define S5PC100_PA_MDMA 0xE8100000
#define S5PC100_PA_PDMA0 0xE9000000
#define S5PC100_PA_PDMA1 0xE9200000
#define S5PC100_PA_CFCON (0xE7800000)
#define S5PC100_PA_TIMER 0xEA000000
#define S5PC100_PA_SYSTIMER 0xEA100000
#define S5PC100_PA_WATCHDOG 0xEA200000
#define S5PC100_PA_RTC 0xEA300000
/* DMA */
#define S5PC100_PA_MDMA (0xE8100000)
#define S5PC100_PA_PDMA0 (0xE9000000)
#define S5PC100_PA_PDMA1 (0xE9200000)
#define S5PC100_PA_UART 0xEC000000
/* Timer */
#define S5PC100_PA_TIMER (0xEA000000)
#define S5P_PA_TIMER S5PC100_PA_TIMER
#define S5PC100_PA_IIC0 0xEC100000
#define S5PC100_PA_IIC1 0xEC200000
#define S5PC100_PA_SYSTIMER (0xEA100000)
#define S5PC100_PA_SPI0 0xEC300000
#define S5PC100_PA_SPI1 0xEC400000
#define S5PC100_PA_SPI2 0xEC500000
#define S5PC100_PA_WATCHDOG (0xEA200000)
#define S5PC100_PA_RTC (0xEA300000)
#define S5PC100_PA_USB_HSOTG 0xED200000
#define S5PC100_PA_USB_HSPHY 0xED300000
#define S5PC100_PA_UART (0xEC000000)
#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0)
#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400)
#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800)
#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
#define S5P_SZ_UART SZ_256
#define S5PC100_PA_FB 0xEE000000
#define S5PC100_PA_IIC0 (0xEC100000)
#define S5PC100_PA_IIC1 (0xEC200000)
#define S5PC100_PA_FIMC0 0xEE200000
#define S5PC100_PA_FIMC1 0xEE300000
#define S5PC100_PA_FIMC2 0xEE400000
/* SPI */
#define S5PC100_PA_SPI0 0xEC300000
#define S5PC100_PA_SPI1 0xEC400000
#define S5PC100_PA_SPI2 0xEC500000
#define S5PC100_PA_I2S0 0xF2000000
#define S5PC100_PA_I2S1 0xF2100000
#define S5PC100_PA_I2S2 0xF2200000
/* USB HS OTG */
#define S5PC100_PA_USB_HSOTG (0xED200000)
#define S5PC100_PA_USB_HSPHY (0xED300000)
#define S5PC100_PA_AC97 0xF2300000
#define S5PC100_PA_FB (0xEE000000)
#define S5PC100_PA_PCM0 0xF2400000
#define S5PC100_PA_PCM1 0xF2500000
#define S5PC100_PA_FIMC0 (0xEE200000)
#define S5PC100_PA_FIMC1 (0xEE300000)
#define S5PC100_PA_FIMC2 (0xEE400000)
#define S5PC100_PA_SPDIF 0xF2600000
#define S5PC100_PA_I2S0 (0xF2000000)
#define S5PC100_PA_I2S1 (0xF2100000)
#define S5PC100_PA_I2S2 (0xF2200000)
#define S5PC100_PA_TSADC 0xF3000000
#define S5PC100_PA_AC97 0xF2300000
#define S5PC100_PA_KEYPAD 0xF3100000
/* PCM */
#define S5PC100_PA_PCM0 0xF2400000
#define S5PC100_PA_PCM1 0xF2500000
/* Compatibiltiy Defines */
#define S5PC100_PA_SPDIF 0xF2600000
#define S3C_PA_FB S5PC100_PA_FB
#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
#define S3C_PA_IIC S5PC100_PA_IIC0
#define S3C_PA_IIC1 S5PC100_PA_IIC1
#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
#define S3C_PA_ONENAND S5PC100_PA_ONENAND
#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
#define S3C_PA_RTC S5PC100_PA_RTC
#define S3C_PA_TSADC S5PC100_PA_TSADC
#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
#define S3C_PA_WDT S5PC100_PA_WATCHDOG
#define S5PC100_PA_TSADC (0xF3000000)
#define S5P_PA_CHIPID S5PC100_PA_CHIPID
#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
#define S5P_PA_SDRAM S5PC100_PA_SDRAM
#define S5P_PA_SROMC S5PC100_PA_SROMC
#define S5P_PA_SYSCON S5PC100_PA_SYSCON
#define S5P_PA_TIMER S5PC100_PA_TIMER
/* KEYPAD */
#define S5PC100_PA_KEYPAD (0xF3100000)
#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
#define S5PC100_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5PC100_PA_SDRAM
#define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
/* compatibiltiy defines. */
#define S3C_PA_UART S5PC100_PA_UART
#define S3C_PA_IIC S5PC100_PA_IIC0
#define S3C_PA_IIC1 S5PC100_PA_IIC1
#define S3C_PA_FB S5PC100_PA_FB
#define S3C_PA_G2D S5PC100_PA_G2D
#define S3C_PA_G3D S5PC100_PA_G3D
#define S3C_PA_JPEG S5PC100_PA_JPEG
#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
#define S5P_VA_VIC0 S5PC1XX_VA_VIC(0)
#define S5P_VA_VIC1 S5PC1XX_VA_VIC(1)
#define S5P_VA_VIC2 S5PC1XX_VA_VIC(2)
#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
#define S3C_PA_WDT S5PC100_PA_WATCHDOG
#define S3C_PA_TSADC S5PC100_PA_TSADC
#define S3C_PA_ONENAND S5PC100_PA_ONENAND
#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
#define S3C_PA_RTC S5PC100_PA_RTC
/* UART */
#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
#define S3C_PA_UART S5PC100_PA_UART
#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#endif /* __ASM_ARCH_C100_MAP_H */
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

168
arch/arm/mach-s5pv210/include/mach/map.h
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s5pv210/include/mach/map.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - Memory map definitions
@ -16,122 +16,120 @@
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5PV210_PA_SROM_BANK5 (0xA8000000)
#define S5PV210_PA_SDRAM 0x20000000
#define S5PC110_PA_ONENAND (0xB0000000)
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
#define S5PV210_PA_SROM_BANK5 0xA8000000
#define S5PC110_PA_ONENAND_DMA (0xB0600000)
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
#define S5PC110_PA_ONENAND 0xB0000000
#define S5PC110_PA_ONENAND_DMA 0xB0600000
#define S5PV210_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5PV210_PA_CHIPID
#define S5PV210_PA_CHIPID 0xE0000000
#define S5PV210_PA_SYSCON (0xE0100000)
#define S5P_PA_SYSCON S5PV210_PA_SYSCON
#define S5PV210_PA_SYSCON 0xE0100000
#define S5PV210_PA_GPIO (0xE0200000)
#define S5PV210_PA_GPIO 0xE0200000
/* SPI */
#define S5PV210_PA_SPI0 0xE1300000
#define S5PV210_PA_SPI1 0xE1400000
#define S5PV210_PA_SPDIF 0xE1100000
#define S5PV210_PA_KEYPAD (0xE1600000)
#define S5PV210_PA_SPI0 0xE1300000
#define S5PV210_PA_SPI1 0xE1400000
#define S5PV210_PA_IIC0 (0xE1800000)
#define S5PV210_PA_IIC1 (0xFAB00000)
#define S5PV210_PA_IIC2 (0xE1A00000)
#define S5PV210_PA_KEYPAD 0xE1600000
#define S5PV210_PA_TIMER (0xE2500000)
#define S5P_PA_TIMER S5PV210_PA_TIMER
#define S5PV210_PA_ADC 0xE1700000
#define S5PV210_PA_SYSTIMER (0xE2600000)
#define S5PV210_PA_IIC0 0xE1800000
#define S5PV210_PA_IIC1 0xFAB00000
#define S5PV210_PA_IIC2 0xE1A00000
#define S5PV210_PA_WATCHDOG (0xE2700000)
#define S5PV210_PA_AC97 0xE2200000
#define S5PV210_PA_RTC (0xE2800000)
#define S5PV210_PA_UART (0xE2900000)
#define S5PV210_PA_PCM0 0xE2300000
#define S5PV210_PA_PCM1 0xE1200000
#define S5PV210_PA_PCM2 0xE2B00000
#define S5P_PA_UART0 (S5PV210_PA_UART + 0x0)
#define S5P_PA_UART1 (S5PV210_PA_UART + 0x400)
#define S5P_PA_UART2 (S5PV210_PA_UART + 0x800)
#define S5P_PA_UART3 (S5PV210_PA_UART + 0xC00)
#define S5PV210_PA_TIMER 0xE2500000
#define S5PV210_PA_SYSTIMER 0xE2600000
#define S5PV210_PA_WATCHDOG 0xE2700000
#define S5PV210_PA_RTC 0xE2800000
#define S5P_SZ_UART SZ_256
#define S5PV210_PA_UART 0xE2900000
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S5PV210_PA_SROMC 0xE8000000
#define S5PV210_PA_SROMC (0xE8000000)
#define S5P_PA_SROMC S5PV210_PA_SROMC
#define S5PV210_PA_CFCON 0xE8200000
#define S5PV210_PA_CFCON (0xE8200000)
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
#define S5PV210_PA_MDMA 0xFA200000
#define S5PV210_PA_PDMA0 0xE0900000
#define S5PV210_PA_PDMA1 0xE0A00000
#define S5PV210_PA_HSOTG 0xEC000000
#define S5PV210_PA_HSPHY 0xEC100000
#define S5PV210_PA_FB (0xF8000000)
#define S5PV210_PA_IIS0 0xEEE30000
#define S5PV210_PA_IIS1 0xE2100000
#define S5PV210_PA_IIS2 0xE2A00000
#define S5PV210_PA_FIMC0 (0xFB200000)
#define S5PV210_PA_FIMC1 (0xFB300000)
#define S5PV210_PA_FIMC2 (0xFB400000)
#define S5PV210_PA_DMC0 0xF0000000
#define S5PV210_PA_DMC1 0xF1400000
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
#define S5PV210_PA_VIC0 0xF2000000
#define S5PV210_PA_VIC1 0xF2100000
#define S5PV210_PA_VIC2 0xF2200000
#define S5PV210_PA_VIC3 0xF2300000
#define S5PV210_PA_HSOTG (0xEC000000)
#define S5PV210_PA_HSPHY (0xEC100000)
#define S5PV210_PA_FB 0xF8000000
#define S5PV210_PA_VIC0 (0xF2000000)
#define S5PV210_PA_VIC1 (0xF2100000)
#define S5PV210_PA_VIC2 (0xF2200000)
#define S5PV210_PA_VIC3 (0xF2300000)
#define S5PV210_PA_MDMA 0xFA200000
#define S5PV210_PA_PDMA0 0xE0900000
#define S5PV210_PA_PDMA1 0xE0A00000
#define S5PV210_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
#define S5PV210_PA_MIPI_CSIS 0xFA600000
/* S/PDIF */
#define S5PV210_PA_SPDIF 0xE1100000
#define S5PV210_PA_FIMC0 0xFB200000
#define S5PV210_PA_FIMC1 0xFB300000
#define S5PV210_PA_FIMC2 0xFB400000
/* I2S */
#define S5PV210_PA_IIS0 0xEEE30000
#define S5PV210_PA_IIS1 0xE2100000
#define S5PV210_PA_IIS2 0xE2A00000
/* Compatibiltiy Defines */
/* PCM */
#define S5PV210_PA_PCM0 0xE2300000
#define S5PV210_PA_PCM1 0xE1200000
#define S5PV210_PA_PCM2 0xE2B00000
#define S3C_PA_FB S5PV210_PA_FB
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
#define S3C_PA_IIC S5PV210_PA_IIC0
#define S3C_PA_IIC1 S5PV210_PA_IIC1
#define S3C_PA_IIC2 S5PV210_PA_IIC2
#define S3C_PA_RTC S5PV210_PA_RTC
#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
/* AC97 */
#define S5PV210_PA_AC97 0xE2200000
#define S5P_PA_CHIPID S5PV210_PA_CHIPID
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
#define S5P_PA_SROMC S5PV210_PA_SROMC
#define S5P_PA_SYSCON S5PV210_PA_SYSCON
#define S5P_PA_TIMER S5PV210_PA_TIMER
#define S5PV210_PA_ADC (0xE1700000)
#define SAMSUNG_PA_ADC S5PV210_PA_ADC
#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
#define S5PV210_PA_DMC0 (0xF0000000)
#define S5PV210_PA_DMC1 (0xF1400000)
/* UART */
#define S5PV210_PA_MIPI_CSIS 0xFA600000
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
/* compatibiltiy defines. */
#define S3C_PA_UART S5PV210_PA_UART
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
#define S3C_PA_IIC S5PV210_PA_IIC0
#define S3C_PA_IIC1 S5PV210_PA_IIC1
#define S3C_PA_IIC2 S5PV210_PA_IIC2
#define S3C_PA_FB S5PV210_PA_FB
#define S3C_PA_RTC S5PV210_PA_RTC
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
#define S3C_PA_UART S5PV210_PA_UART
#define SAMSUNG_PA_ADC S5PV210_PA_ADC
#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

15
arch/arm/mach-s5pv210/mach-aquila.c
View File

@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = {
static struct regulator_init_data aquila_ldo3_data = {
.constraints = {
.name = "VUSB/MIPI_1.1V",
.name = "VUSB+MIPI_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = {
static struct regulator_init_data aquila_ldo8_data = {
.constraints = {
.name = "VUSB/VADC_3.3V",
.name = "VUSB+VADC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = {
static struct regulator_init_data aquila_ldo9_data = {
.constraints = {
.name = "VCC/VCAM_2.8V",
.name = "VCC+VCAM_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
@ -381,9 +381,12 @@ static struct max8998_platform_data aquila_max8998_pdata = {
.buck1_set1 = S5PV210_GPH0(3),
.buck1_set2 = S5PV210_GPH0(4),
.buck2_set3 = S5PV210_GPH0(5),
.buck1_max_voltage1 = 1200000,
.buck1_max_voltage2 = 1200000,
.buck2_max_voltage = 1200000,
.buck1_voltage1 = 1200000,
.buck1_voltage2 = 1200000,
.buck1_voltage3 = 1200000,
.buck1_voltage4 = 1200000,
.buck2_voltage1 = 1200000,
.buck2_voltage2 = 1200000,
};
#endif

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