- Fix a regression in 16-bit Atmel NAND flash which was introduced in 3.1
- Fix breakage with MTD suspend caused by the API rework - Fix a problem with resetting the MX28 BCH module - A couple of other trivial fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iEYEABECAAYFAk8s6HsACgkQdwG7hYl686MIiACgxpNoUWFvq8z+2UGXxsLnNrio hhcAn31H7TY3KUuIQBo4CqG2dEjNwpCw =DRWp -----END PGP SIGNATURE----- Merge tag 'for-linus-3.3' of git://git.infradead.org/~dwmw2/mtd-3.3 - Fix a regression in 16-bit Atmel NAND flash which was introduced in 3.1 - Fix breakage with MTD suspend caused by the API rework - Fix a problem with resetting the MX28 BCH module - A couple of other trivial fixes * tag 'for-linus-3.3-20120204' of git://git.infradead.org/~dwmw2/mtd-3.3: Revert "mtd: atmel_nand: optimize read/write buffer functions" mtd: fix MTD suspend jffs2: do not initialize variable unnecessarily mtd: gpmi-nand bugfix: reset the BCH module when it is not MX23 mtd: nand: fix typo in comment
This commit is contained in:
Linus Torvalds
commit
71b1b20b8a
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@ -119,7 +119,7 @@ static int mtd_cls_suspend(struct device *dev, pm_message_t state)
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{
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struct mtd_info *mtd = dev_get_drvdata(dev);
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return mtd_suspend(mtd);
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return mtd ? mtd_suspend(mtd) : 0;
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}
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static int mtd_cls_resume(struct device *dev)
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@ -161,6 +161,37 @@ static int atmel_nand_device_ready(struct mtd_info *mtd)
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!!host->board->rdy_pin_active_low;
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}
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/*
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* Minimal-overhead PIO for data access.
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*/
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static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
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}
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static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
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}
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static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
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}
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static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
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}
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static void dma_complete_func(void *completion)
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{
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complete(completion);
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@ -235,27 +266,33 @@ err_buf:
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static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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struct atmel_nand_host *host = chip->priv;
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if (use_dma && len > mtd->oobsize)
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/* only use DMA for bigger than oob size: better performances */
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if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
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return;
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/* if no DMA operation possible, use PIO */
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memcpy_fromio(buf, chip->IO_ADDR_R, len);
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if (host->board->bus_width_16)
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atmel_read_buf16(mtd, buf, len);
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else
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atmel_read_buf8(mtd, buf, len);
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}
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static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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struct atmel_nand_host *host = chip->priv;
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if (use_dma && len > mtd->oobsize)
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/* only use DMA for bigger than oob size: better performances */
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if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
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return;
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/* if no DMA operation possible, use PIO */
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memcpy_toio(chip->IO_ADDR_W, buf, len);
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if (host->board->bus_width_16)
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atmel_write_buf16(mtd, buf, len);
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else
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atmel_write_buf8(mtd, buf, len);
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}
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/*
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@ -69,17 +69,19 @@ static int clear_poll_bit(void __iomem *addr, u32 mask)
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* [1] enable the module.
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* [2] reset the module.
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*
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* In most of the cases, it's ok. But there is a hardware bug in the BCH block.
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* In most of the cases, it's ok.
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* But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
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* If you try to soft reset the BCH block, it becomes unusable until
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* the next hard reset. This case occurs in the NAND boot mode. When the board
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* boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
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* So If the driver tries to reset the BCH again, the BCH will not work anymore.
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* You will see a DMA timeout in this case.
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* You will see a DMA timeout in this case. The bug has been fixed
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* in the following chips, such as MX28.
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*
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* To avoid this bug, just add a new parameter `just_enable` for
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* the mxs_reset_block(), and rewrite it here.
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*/
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int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
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static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
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{
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int ret;
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int timeout = 0x400;
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@ -206,7 +208,15 @@ int bch_set_geometry(struct gpmi_nand_data *this)
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if (ret)
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goto err_out;
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ret = gpmi_reset_block(r->bch_regs, true);
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/*
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* Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
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* chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
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* On the other hand, the MX28 needs the reset, because one case has been
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* seen where the BCH produced ECC errors constantly after 10000
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* consecutive reboots. The latter case has not been seen on the MX23 yet,
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* still we don't know if it could happen there as well.
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*/
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ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
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if (ret)
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goto err_out;
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@ -2588,7 +2588,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
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instr->state = MTD_ERASING;
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while (len) {
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/* Heck if we have a bad block, we do not erase bad blocks! */
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/* Check if we have a bad block, we do not erase bad blocks! */
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if (nand_block_checkbad(mtd, ((loff_t) page) <<
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chip->page_shift, 0, allowbbt)) {
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pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
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@ -335,7 +335,7 @@ static int jffs2_block_check_erase(struct jffs2_sb_info *c, struct jffs2_erasebl
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void *ebuf;
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uint32_t ofs;
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size_t retlen;
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int ret = -EIO;
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int ret;
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unsigned long *wordebuf;
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ret = mtd_point(c->mtd, jeb->offset, c->sector_size, &retlen,
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@ -427,9 +427,7 @@ static inline int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
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static inline int mtd_suspend(struct mtd_info *mtd)
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{
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if (!mtd->suspend)
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return -EOPNOTSUPP;
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return mtd->suspend(mtd);
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return mtd->suspend ? mtd->suspend(mtd) : 0;
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}
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static inline void mtd_resume(struct mtd_info *mtd)
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