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MIPS: Octeon: Update DMA mapping operations for OCTEON II processors. 

OCTEON II has a new dma to phys mapping method for PCIe.  Define
OCTEON_DMA_BAR_TYPE_PCIE2 to denote this case, and handle it.

OCTEON II also needs a swiotlb if the OHCI USB driver is enabled, so
allocate this too.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2983/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney 2011-11-22 14:47:04 +00:00 committed by Ralf Baechle
parent 26afc5e399
commit 714c1f5c1a
2 changed files with 23 additions and 3 deletions
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23
arch/mips/cavium-octeon/dma-octeon.c
View File

@ -61,6 +61,16 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
return daddr; return daddr;
} }
static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
return octeon_hole_phys_to_dma(paddr);
}
static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
{
return octeon_hole_dma_to_phys(daddr);
}
static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr) static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
{ {
if (paddr >= 0x410000000ull && paddr < 0x420000000ull) if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
@ -262,11 +272,11 @@ void __init plat_swiotlb_setup(void)
for (i = 0 ; i < boot_mem_map.nr_map; i++) { for (i = 0 ; i < boot_mem_map.nr_map; i++) {
struct boot_mem_map_entry *e = &boot_mem_map.map[i]; struct boot_mem_map_entry *e = &boot_mem_map.map[i];
if (e->type != BOOT_MEM_RAM) if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
continue; continue;
/* These addresses map low for PCI. */ /* These addresses map low for PCI. */
if (e->addr > 0x410000000ull) if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX))
continue; continue;
addr_size += e->size; addr_size += e->size;
@ -295,6 +305,11 @@ void __init plat_swiotlb_setup(void)
*/ */
swiotlbsize = 64 * (1<<20); swiotlbsize = 64 * (1<<20);
} }
#endif
#ifdef CONFIG_USB_OCTEON_OHCI
/* OCTEON II ohci is only 32-bit. */
if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul)
swiotlbsize = 64 * (1<<20);
#endif #endif
swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT; swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE); swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
@ -330,6 +345,10 @@ struct dma_map_ops *octeon_pci_dma_map_ops;
void __init octeon_pci_dma_init(void) void __init octeon_pci_dma_init(void)
{ {
switch (octeon_dma_bar_type) { switch (octeon_dma_bar_type) {
case OCTEON_DMA_BAR_TYPE_PCIE2:
_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
break;
case OCTEON_DMA_BAR_TYPE_PCIE: case OCTEON_DMA_BAR_TYPE_PCIE:
_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma; _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys; _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;

3
arch/mips/include/asm/octeon/pci-octeon.h
View File

@ -56,7 +56,8 @@ enum octeon_dma_bar_type {
OCTEON_DMA_BAR_TYPE_INVALID, OCTEON_DMA_BAR_TYPE_INVALID,
OCTEON_DMA_BAR_TYPE_SMALL, OCTEON_DMA_BAR_TYPE_SMALL,
OCTEON_DMA_BAR_TYPE_BIG, OCTEON_DMA_BAR_TYPE_BIG,
OCTEON_DMA_BAR_TYPE_PCIE OCTEON_DMA_BAR_TYPE_PCIE,
OCTEON_DMA_BAR_TYPE_PCIE2
}; };
/* /*