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[MIPS] VSMP: Synchronize cp0 counters on bootup. 

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2006-10-31 18:33:09 +00:00
parent e79f55a8c7
commit 70e46f48cb
3 changed files with 7 additions and 2 deletions
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2
arch/mips/kernel/smp-mt.c
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@ -153,6 +153,8 @@ static void __init smp_copy_vpe_config(void)
/* Propagate Config7 */ /* Propagate Config7 */
write_vpe_c0_config7(read_c0_config7()); write_vpe_c0_config7(read_c0_config7());
write_vpe_c0_count(read_c0_count());
} }
static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0, static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0,

5
arch/mips/mips-boards/generic/time.c
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@ -209,6 +209,7 @@ static unsigned int __init estimate_cpu_frequency(void)
#endif #endif
#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
unsigned long flags; unsigned long flags;
unsigned int start;
local_irq_save(flags); local_irq_save(flags);
@ -217,13 +218,13 @@ static unsigned int __init estimate_cpu_frequency(void)
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
/* Start r4k counter. */ /* Start r4k counter. */
write_c0_count(0); start = read_c0_count();
/* Read counter exactly on falling edge of update flag */ /* Read counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP); while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
count = read_c0_count(); count = read_c0_count() - start;
/* restore interrupts */ /* restore interrupts */
local_irq_restore(flags); local_irq_restore(flags);

2
include/asm-mips/mipsmtregs.h
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@ -352,6 +352,8 @@ do { \
#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
#define read_vpe_c0_vpeconf0() mftc0(1, 2) #define read_vpe_c0_vpeconf0() mftc0(1, 2)
#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
#define read_vpe_c0_count() mftc0(9, 0)
#define write_vpe_c0_count(val) mttc0(9, 0, val)
#define read_vpe_c0_status() mftc0(12, 0) #define read_vpe_c0_status() mftc0(12, 0)
#define write_vpe_c0_status(val) mttc0(12, 0, val) #define write_vpe_c0_status(val) mttc0(12, 0, val)
#define read_vpe_c0_cause() mftc0(13, 0) #define read_vpe_c0_cause() mftc0(13, 0)