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drm/nouveau/ltc: convert to new-style nvkm_subdev 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:21 +10:00
parent b7a2bc1886
commit 70bc7182cb
13 changed files with 240 additions and 347 deletions
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35
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
View File

@ -1,31 +1,36 @@
#ifndef __NVKM_LTC_H__ #ifndef __NVKM_LTC_H__
#define __NVKM_LTC_H__ #define __NVKM_LTC_H__
#include <core/subdev.h> #include <core/subdev.h>
struct nvkm_mm_node; #include <core/mm.h>
#define NVKM_LTC_MAX_ZBC_CNT 16 #define NVKM_LTC_MAX_ZBC_CNT 16
struct nvkm_ltc { struct nvkm_ltc {
const struct nvkm_ltc_func *func;
struct nvkm_subdev subdev; struct nvkm_subdev subdev;
int (*tags_alloc)(struct nvkm_ltc *, u32 count, u32 ltc_nr;
struct nvkm_mm_node **); u32 lts_nr;
void (*tags_free)(struct nvkm_ltc *, struct nvkm_mm_node **);
void (*tags_clear)(struct nvkm_ltc *, u32 first, u32 count); u32 num_tags;
u32 tag_base;
struct nvkm_mm tags;
struct nvkm_mm_node *tag_ram;
int zbc_min; int zbc_min;
int zbc_max; int zbc_max;
int (*zbc_color_get)(struct nvkm_ltc *, int index, const u32[4]); u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4];
int (*zbc_depth_get)(struct nvkm_ltc *, int index, const u32); u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
}; };
static inline struct nvkm_ltc * int nvkm_ltc_tags_alloc(struct nvkm_ltc *, u32 count, struct nvkm_mm_node **);
nvkm_ltc(void *obj) void nvkm_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **);
{ void nvkm_ltc_tags_clear(struct nvkm_ltc *, u32 first, u32 count);
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_LTC);
}
extern struct nvkm_oclass *gf100_ltc_oclass; int nvkm_ltc_zbc_color_get(struct nvkm_ltc *, int index, const u32[4]);
extern struct nvkm_oclass *gk104_ltc_oclass; int nvkm_ltc_zbc_depth_get(struct nvkm_ltc *, int index, const u32);
extern struct nvkm_oclass *gm107_ltc_oclass;
int gf100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
int gk104_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
#endif #endif

42
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -1300,7 +1300,7 @@ nvc0_chipset = {
.i2c = g94_i2c_new, .i2c = g94_i2c_new,
.ibus = gf100_ibus_new, .ibus = gf100_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new, .ltc = gf100_ltc_new,
// .mc = gf100_mc_new, // .mc = gf100_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1335,7 +1335,7 @@ nvc1_chipset = {
.i2c = g94_i2c_new, .i2c = g94_i2c_new,
.ibus = gf100_ibus_new, .ibus = gf100_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new, .ltc = gf100_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1369,7 +1369,7 @@ nvc3_chipset = {
.i2c = g94_i2c_new, .i2c = g94_i2c_new,
.ibus = gf100_ibus_new, .ibus = gf100_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new, .ltc = gf100_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1403,7 +1403,7 @@ nvc4_chipset = {
.i2c = g94_i2c_new, .i2c = g94_i2c_new,
.ibus = gf100_ibus_new, .ibus = gf100_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new, .ltc = gf100_ltc_new,
// .mc = gf100_mc_new, // .mc = gf100_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1438,7 +1438,7 @@ nvc8_chipset = {
.i2c = g94_i2c_new, .i2c = g94_i2c_new,
.ibus = gf100_ibus_new, .ibus = gf100_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new, .ltc = gf100_ltc_new,
// .mc = gf100_mc_new, // .mc = gf100_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1473,7 +1473,7 @@ nvce_chipset = {
.i2c = g94_i2c_new, .i2c = g94_i2c_new,
.ibus = gf100_ibus_new, .ibus = gf100_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new, .ltc = gf100_ltc_new,
// .mc = gf100_mc_new, // .mc = gf100_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1508,7 +1508,7 @@ nvcf_chipset = {
.i2c = g94_i2c_new, .i2c = g94_i2c_new,
.ibus = gf100_ibus_new, .ibus = gf100_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new, .ltc = gf100_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1542,7 +1542,7 @@ nvd7_chipset = {
.i2c = gf117_i2c_new, .i2c = gf117_i2c_new,
.ibus = gf100_ibus_new, .ibus = gf100_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new, .ltc = gf100_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1574,7 +1574,7 @@ nvd9_chipset = {
.i2c = gf119_i2c_new, .i2c = gf119_i2c_new,
.ibus = gf100_ibus_new, .ibus = gf100_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new, .ltc = gf100_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1608,7 +1608,7 @@ nve4_chipset = {
.i2c = gk104_i2c_new, .i2c = gk104_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new, .ltc = gk104_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1644,7 +1644,7 @@ nve6_chipset = {
.i2c = gk104_i2c_new, .i2c = gk104_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new, .ltc = gk104_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1680,7 +1680,7 @@ nve7_chipset = {
.i2c = gk104_i2c_new, .i2c = gk104_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new, .ltc = gk104_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1712,7 +1712,7 @@ nvea_chipset = {
.fuse = gf100_fuse_new, .fuse = gf100_fuse_new,
.ibus = gk20a_ibus_new, .ibus = gk20a_ibus_new,
.imem = gk20a_instmem_new, .imem = gk20a_instmem_new,
// .ltc = gk104_ltc_new, .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new, // .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .pmu = gk20a_pmu_new, // .pmu = gk20a_pmu_new,
@ -1740,7 +1740,7 @@ nvf0_chipset = {
.i2c = gk104_i2c_new, .i2c = gk104_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new, .ltc = gk104_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1776,7 +1776,7 @@ nvf1_chipset = {
.i2c = gf119_i2c_new, .i2c = gf119_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new, .ltc = gk104_ltc_new,
// .mc = gf106_mc_new, // .mc = gf106_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1812,7 +1812,7 @@ nv106_chipset = {
.i2c = gk104_i2c_new, .i2c = gk104_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new, .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new, // .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1847,7 +1847,7 @@ nv108_chipset = {
.i2c = gk104_i2c_new, .i2c = gk104_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new, .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new, // .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1882,7 +1882,7 @@ nv117_chipset = {
.i2c = gf119_i2c_new, .i2c = gf119_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gm107_ltc_new, .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new, // .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1911,7 +1911,7 @@ nv124_chipset = {
.i2c = gm204_i2c_new, .i2c = gm204_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gm107_ltc_new, .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new, // .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1940,7 +1940,7 @@ nv126_chipset = {
.i2c = gm204_i2c_new, .i2c = gm204_i2c_new,
.ibus = gk104_ibus_new, .ibus = gk104_ibus_new,
.imem = nv50_instmem_new, .imem = nv50_instmem_new,
// .ltc = gm107_ltc_new, .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new, // .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new, // .mxm = nv50_mxm_new,
@ -1965,7 +1965,7 @@ nv12b_chipset = {
.fuse = gm107_fuse_new, .fuse = gm107_fuse_new,
.ibus = gk20a_ibus_new, .ibus = gk20a_ibus_new,
.imem = gk20a_instmem_new, .imem = gk20a_instmem_new,
// .ltc = gm107_ltc_new, .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new, // .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,
// .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new,

9
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -32,7 +32,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -53,7 +52,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -74,7 +72,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -94,7 +91,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -115,7 +111,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -135,7 +130,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -155,7 +149,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -176,7 +169,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -196,7 +188,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -32,7 +32,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -54,7 +53,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -76,7 +74,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -96,7 +93,6 @@ gk104_identify(struct nvkm_device *device)
case 0xea: case 0xea:
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
@ -112,7 +108,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -134,7 +129,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -156,7 +150,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -177,7 +170,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -32,7 +32,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
@ -64,7 +63,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0 #if 0
@ -93,7 +91,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0 #if 0
@ -118,7 +115,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;

10
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -58,7 +58,7 @@ static int
gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
const u32 ds[4], const u32 l2[4]) const u32 ds[4], const u32 l2[4])
{ {
struct nvkm_ltc *ltc = nvkm_ltc(gr); struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i; int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
@ -85,7 +85,7 @@ gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
gr->zbc_color[zbc].format = format; gr->zbc_color[zbc].format = format;
ltc->zbc_color_get(ltc, zbc, l2); nvkm_ltc_zbc_color_get(ltc, zbc, l2);
gf100_gr_zbc_clear_color(gr, zbc); gf100_gr_zbc_clear_color(gr, zbc);
return zbc; return zbc;
} }
@ -105,7 +105,7 @@ static int
gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
const u32 ds, const u32 l2) const u32 ds, const u32 l2)
{ {
struct nvkm_ltc *ltc = nvkm_ltc(gr); struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i; int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
@ -130,7 +130,7 @@ gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
gr->zbc_depth[zbc].format = format; gr->zbc_depth[zbc].format = format;
gr->zbc_depth[zbc].ds = ds; gr->zbc_depth[zbc].ds = ds;
gr->zbc_depth[zbc].l2 = l2; gr->zbc_depth[zbc].l2 = l2;
ltc->zbc_depth_get(ltc, zbc, l2); nvkm_ltc_zbc_depth_get(ltc, zbc, l2);
gf100_gr_zbc_clear_depth(gr, zbc); gf100_gr_zbc_clear_depth(gr, zbc);
return zbc; return zbc;
} }
@ -680,7 +680,7 @@ gf100_gr_zbc_init(struct gf100_gr *gr)
0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
struct nvkm_ltc *ltc = nvkm_ltc(gr); struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int index; int index;
if (!gr->zbc_color[0].format) { if (!gr->zbc_color[0].format) {

4
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
View File

@ -434,7 +434,7 @@ gf100_ram_put(struct nvkm_ram *ram, struct nvkm_mem **pmem)
mutex_lock(&ram->fb->subdev.mutex); mutex_lock(&ram->fb->subdev.mutex);
if (mem->tag) if (mem->tag)
ltc->tags_free(ltc, &mem->tag); nvkm_ltc_tags_free(ltc, &mem->tag);
__nv50_ram_put(ram, mem); __nv50_ram_put(ram, mem);
mutex_unlock(&ram->fb->subdev.mutex); mutex_unlock(&ram->fb->subdev.mutex);
@ -472,7 +472,7 @@ gf100_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin,
/* compression only works with lpages */ /* compression only works with lpages */
if (align == (1 << (17 - NVKM_RAM_MM_SHIFT))) { if (align == (1 << (17 - NVKM_RAM_MM_SHIFT))) {
int n = size >> 5; int n = size >> 5;
ltc->tags_alloc(ltc, n, &mem->tag); nvkm_ltc_tags_alloc(ltc, n, &mem->tag);
} }
if (unlikely(!mem->tag)) if (unlikely(!mem->tag))

132
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
View File

@ -23,102 +23,110 @@
*/ */
#include "priv.h" #include "priv.h"
static int #include <subdev/fb.h>
nvkm_ltc_tags_alloc(struct nvkm_ltc *obj, u32 n, struct nvkm_mm_node **pnode)
{
struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
int ret;
ret = nvkm_mm_head(&ltc->tags, 0, 1, n, n, 1, pnode); int
nvkm_ltc_tags_alloc(struct nvkm_ltc *ltc, u32 n, struct nvkm_mm_node **pnode)
{
int ret = nvkm_mm_head(&ltc->tags, 0, 1, n, n, 1, pnode);
if (ret) if (ret)
*pnode = NULL; *pnode = NULL;
return ret; return ret;
} }
static void void
nvkm_ltc_tags_free(struct nvkm_ltc *obj, struct nvkm_mm_node **pnode) nvkm_ltc_tags_free(struct nvkm_ltc *ltc, struct nvkm_mm_node **pnode)
{ {
struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
nvkm_mm_free(&ltc->tags, pnode); nvkm_mm_free(&ltc->tags, pnode);
} }
static void void
nvkm_ltc_tags_clear(struct nvkm_ltc *obj, u32 first, u32 count) nvkm_ltc_tags_clear(struct nvkm_ltc *ltc, u32 first, u32 count)
{ {
struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
const u32 limit = first + count - 1; const u32 limit = first + count - 1;
BUG_ON((first > limit) || (limit >= ltc->num_tags)); BUG_ON((first > limit) || (limit >= ltc->num_tags));
impl->cbc_clear(ltc, first, limit); ltc->func->cbc_clear(ltc, first, limit);
impl->cbc_wait(ltc); ltc->func->cbc_wait(ltc);
} }
static int int
nvkm_ltc_zbc_color_get(struct nvkm_ltc *obj, int index, const u32 color[4]) nvkm_ltc_zbc_color_get(struct nvkm_ltc *ltc, int index, const u32 color[4])
{ {
struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
memcpy(ltc->zbc_color[index], color, sizeof(ltc->zbc_color[index])); memcpy(ltc->zbc_color[index], color, sizeof(ltc->zbc_color[index]));
impl->zbc_clear_color(ltc, index, color); ltc->func->zbc_clear_color(ltc, index, color);
return index;
}
static int
nvkm_ltc_zbc_depth_get(struct nvkm_ltc *obj, int index, const u32 depth)
{
struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
ltc->zbc_depth[index] = depth;
impl->zbc_clear_depth(ltc, index, depth);
return index; return index;
} }
int int
_nvkm_ltc_init(struct nvkm_object *object) nvkm_ltc_zbc_depth_get(struct nvkm_ltc *ltc, int index, const u32 depth)
{ {
struct nvkm_ltc_priv *ltc = (void *)object; ltc->zbc_depth[index] = depth;
const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object); ltc->func->zbc_clear_depth(ltc, index, depth);
int ret, i; return index;
}
ret = nvkm_subdev_init_old(&ltc->base.subdev); static void
if (ret) nvkm_ltc_intr(struct nvkm_subdev *subdev)
return ret; {
struct nvkm_ltc *ltc = nvkm_ltc(subdev);
ltc->func->intr(ltc);
}
for (i = ltc->base.zbc_min; i <= ltc->base.zbc_max; i++) { static int
impl->zbc_clear_color(ltc, i, ltc->zbc_color[i]); nvkm_ltc_oneinit(struct nvkm_subdev *subdev)
impl->zbc_clear_depth(ltc, i, ltc->zbc_depth[i]); {
struct nvkm_ltc *ltc = nvkm_ltc(subdev);
return ltc->func->oneinit(ltc);
}
static int
nvkm_ltc_init(struct nvkm_subdev *subdev)
{
struct nvkm_ltc *ltc = nvkm_ltc(subdev);
int i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
ltc->func->zbc_clear_color(ltc, i, ltc->zbc_color[i]);
ltc->func->zbc_clear_depth(ltc, i, ltc->zbc_depth[i]);
} }
ltc->func->init(ltc);
return 0; return 0;
} }
static void *
nvkm_ltc_dtor(struct nvkm_subdev *subdev)
{
struct nvkm_ltc *ltc = nvkm_ltc(subdev);
struct nvkm_ram *ram = ltc->subdev.device->fb->ram;
nvkm_mm_fini(&ltc->tags);
if (ram)
nvkm_mm_free(&ram->vram, &ltc->tag_ram);
return ltc;
}
static const struct nvkm_subdev_func
nvkm_ltc = {
.dtor = nvkm_ltc_dtor,
.oneinit = nvkm_ltc_oneinit,
.init = nvkm_ltc_init,
.intr = nvkm_ltc_intr,
};
int int
nvkm_ltc_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_ltc_new_(const struct nvkm_ltc_func *func, struct nvkm_device *device,
struct nvkm_oclass *oclass, int length, void **pobject) int index, struct nvkm_ltc **pltc)
{ {
const struct nvkm_ltc_impl *impl = (void *)oclass; struct nvkm_ltc *ltc;
struct nvkm_ltc_priv *ltc;
int ret;
ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PLTCG", if (!(ltc = *pltc = kzalloc(sizeof(*ltc), GFP_KERNEL)))
"l2c", length, pobject); return -ENOMEM;
ltc = *pobject;
if (ret)
return ret;
memset(ltc->zbc_color, 0x00, sizeof(ltc->zbc_color)); nvkm_subdev_ctor(&nvkm_ltc, device, index, 0, &ltc->subdev);
memset(ltc->zbc_depth, 0x00, sizeof(ltc->zbc_depth)); ltc->func = func;
ltc->zbc_min = 1; /* reserve 0 for disabled */
ltc->base.subdev.intr = impl->intr; ltc->zbc_max = min(func->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1;
ltc->base.tags_alloc = nvkm_ltc_tags_alloc;
ltc->base.tags_free = nvkm_ltc_tags_free;
ltc->base.tags_clear = nvkm_ltc_tags_clear;
ltc->base.zbc_min = 1; /* reserve 0 for disabled */
ltc->base.zbc_max = min(impl->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1;
ltc->base.zbc_color_get = nvkm_ltc_zbc_color_get;
ltc->base.zbc_depth_get = nvkm_ltc_zbc_depth_get;
return 0; return 0;
} }

126
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
View File

@ -28,18 +28,18 @@
#include <subdev/timer.h> #include <subdev/timer.h>
void void
gf100_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit) gf100_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit)
{ {
struct nvkm_device *device = ltc->base.subdev.device; struct nvkm_device *device = ltc->subdev.device;
nvkm_wr32(device, 0x17e8cc, start); nvkm_wr32(device, 0x17e8cc, start);
nvkm_wr32(device, 0x17e8d0, limit); nvkm_wr32(device, 0x17e8d0, limit);
nvkm_wr32(device, 0x17e8c8, 0x00000004); nvkm_wr32(device, 0x17e8c8, 0x00000004);
} }
void void
gf100_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) gf100_ltc_cbc_wait(struct nvkm_ltc *ltc)
{ {
struct nvkm_device *device = ltc->base.subdev.device; struct nvkm_device *device = ltc->subdev.device;
int c, s; int c, s;
for (c = 0; c < ltc->ltc_nr; c++) { for (c = 0; c < ltc->ltc_nr; c++) {
for (s = 0; s < ltc->lts_nr; s++) { for (s = 0; s < ltc->lts_nr; s++) {
@ -53,9 +53,9 @@ gf100_ltc_cbc_wait(struct nvkm_ltc_priv *ltc)
} }
void void
gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4]) gf100_ltc_zbc_clear_color(struct nvkm_ltc *ltc, int i, const u32 color[4])
{ {
struct nvkm_device *device = ltc->base.subdev.device; struct nvkm_device *device = ltc->subdev.device;
nvkm_mask(device, 0x17ea44, 0x0000000f, i); nvkm_mask(device, 0x17ea44, 0x0000000f, i);
nvkm_wr32(device, 0x17ea48, color[0]); nvkm_wr32(device, 0x17ea48, color[0]);
nvkm_wr32(device, 0x17ea4c, color[1]); nvkm_wr32(device, 0x17ea4c, color[1]);
@ -64,9 +64,9 @@ gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4])
} }
void void
gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth) gf100_ltc_zbc_clear_depth(struct nvkm_ltc *ltc, int i, const u32 depth)
{ {
struct nvkm_device *device = ltc->base.subdev.device; struct nvkm_device *device = ltc->subdev.device;
nvkm_mask(device, 0x17ea44, 0x0000000f, i); nvkm_mask(device, 0x17ea44, 0x0000000f, i);
nvkm_wr32(device, 0x17ea58, depth); nvkm_wr32(device, 0x17ea58, depth);
} }
@ -90,9 +90,9 @@ gf100_ltc_lts_intr_name[] = {
}; };
static void static void
gf100_ltc_lts_intr(struct nvkm_ltc_priv *ltc, int c, int s) gf100_ltc_lts_intr(struct nvkm_ltc *ltc, int c, int s)
{ {
struct nvkm_subdev *subdev = &ltc->base.subdev; struct nvkm_subdev *subdev = &ltc->subdev;
struct nvkm_device *device = subdev->device; struct nvkm_device *device = subdev->device;
u32 base = 0x141000 + (c * 0x2000) + (s * 0x400); u32 base = 0x141000 + (c * 0x2000) + (s * 0x400);
u32 intr = nvkm_rd32(device, base + 0x020); u32 intr = nvkm_rd32(device, base + 0x020);
@ -108,10 +108,9 @@ gf100_ltc_lts_intr(struct nvkm_ltc_priv *ltc, int c, int s)
} }
void void
gf100_ltc_intr(struct nvkm_subdev *subdev) gf100_ltc_intr(struct nvkm_ltc *ltc)
{ {
struct nvkm_ltc_priv *ltc = (void *)subdev; struct nvkm_device *device = ltc->subdev.device;
struct nvkm_device *device = ltc->base.subdev.device;
u32 mask; u32 mask;
mask = nvkm_rd32(device, 0x00017c); mask = nvkm_rd32(device, 0x00017c);
@ -123,44 +122,12 @@ gf100_ltc_intr(struct nvkm_subdev *subdev)
} }
} }
static int
gf100_ltc_init(struct nvkm_object *object)
{
struct nvkm_ltc_priv *ltc = (void *)object;
struct nvkm_device *device = ltc->base.subdev.device;
u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
int ret;
ret = nvkm_ltc_init(ltc);
if (ret)
return ret;
nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);
nvkm_wr32(device, 0x17e8d4, ltc->tag_base);
nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
return 0;
}
void
gf100_ltc_dtor(struct nvkm_object *object)
{
struct nvkm_ltc_priv *ltc = (void *)object;
struct nvkm_ram *ram = ltc->base.subdev.device->fb->ram;
nvkm_mm_fini(&ltc->tags);
if (ram)
nvkm_mm_free(&ram->vram, &ltc->tag_ram);
nvkm_ltc_destroy(ltc);
}
/* TODO: Figure out tag memory details and drop the over-cautious allocation. /* TODO: Figure out tag memory details and drop the over-cautious allocation.
*/ */
int int
gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *ltc) gf100_ltc_oneinit_tag_ram(struct nvkm_ltc *ltc)
{ {
struct nvkm_ram *ram = ltc->base.subdev.device->fb->ram; struct nvkm_ram *ram = ltc->subdev.device->fb->ram;
u32 tag_size, tag_margin, tag_align; u32 tag_size, tag_margin, tag_align;
int ret; int ret;
@ -205,54 +172,53 @@ gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *ltc)
} }
mm_init: mm_init:
ret = nvkm_mm_init(&ltc->tags, 0, ltc->num_tags, 1); return nvkm_mm_init(&ltc->tags, 0, ltc->num_tags, 1);
return ret;
} }
int int
gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_ltc_oneinit(struct nvkm_ltc *ltc)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nvkm_device *device = (void *)parent; struct nvkm_device *device = ltc->subdev.device;
struct nvkm_ltc_priv *ltc; const u32 parts = nvkm_rd32(device, 0x022438);
u32 parts, mask; const u32 mask = nvkm_rd32(device, 0x022554);
int ret, i; const u32 slice = nvkm_rd32(device, 0x17e8dc) >> 28;
int i;
ret = nvkm_ltc_create(parent, engine, oclass, &ltc);
*pobject = nv_object(ltc);
if (ret)
return ret;
parts = nvkm_rd32(device, 0x022438);
mask = nvkm_rd32(device, 0x022554);
for (i = 0; i < parts; i++) { for (i = 0; i < parts; i++) {
if (!(mask & (1 << i))) if (!(mask & (1 << i)))
ltc->ltc_nr++; ltc->ltc_nr++;
} }
ltc->lts_nr = nvkm_rd32(device, 0x17e8dc) >> 28; ltc->lts_nr = slice;
ret = gf100_ltc_init_tag_ram(ltc); return gf100_ltc_oneinit_tag_ram(ltc);
if (ret)
return ret;
nv_subdev(ltc)->intr = gf100_ltc_intr;
return 0;
} }
struct nvkm_oclass * static void
gf100_ltc_oclass = &(struct nvkm_ltc_impl) { gf100_ltc_init(struct nvkm_ltc *ltc)
.base.handle = NV_SUBDEV(LTC, 0xc0), {
.base.ofuncs = &(struct nvkm_ofuncs) { struct nvkm_device *device = ltc->subdev.device;
.ctor = gf100_ltc_ctor, u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
.dtor = gf100_ltc_dtor,
.init = gf100_ltc_init, nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
.fini = _nvkm_ltc_fini, nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);
}, nvkm_wr32(device, 0x17e8d4, ltc->tag_base);
nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
}
static const struct nvkm_ltc_func
gf100_ltc = {
.oneinit = gf100_ltc_oneinit,
.init = gf100_ltc_init,
.intr = gf100_ltc_intr, .intr = gf100_ltc_intr,
.cbc_clear = gf100_ltc_cbc_clear, .cbc_clear = gf100_ltc_cbc_clear,
.cbc_wait = gf100_ltc_cbc_wait, .cbc_wait = gf100_ltc_cbc_wait,
.zbc = 16, .zbc = 16,
.zbc_clear_color = gf100_ltc_zbc_clear_color, .zbc_clear_color = gf100_ltc_zbc_clear_color,
.zbc_clear_depth = gf100_ltc_zbc_clear_depth, .zbc_clear_depth = gf100_ltc_zbc_clear_depth,
}.base; };
int
gf100_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc)
{
return nvkm_ltc_new_(&gf100_ltc, device, index, pltc);
}

34
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c
View File

@ -23,38 +23,32 @@
*/ */
#include "priv.h" #include "priv.h"
static int static void
gk104_ltc_init(struct nvkm_object *object) gk104_ltc_init(struct nvkm_ltc *ltc)
{ {
struct nvkm_ltc_priv *ltc = (void *)object; struct nvkm_device *device = ltc->subdev.device;
struct nvkm_device *device = ltc->base.subdev.device;
u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
int ret;
ret = nvkm_ltc_init(ltc);
if (ret)
return ret;
nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr); nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);
nvkm_wr32(device, 0x17e000, ltc->ltc_nr); nvkm_wr32(device, 0x17e000, ltc->ltc_nr);
nvkm_wr32(device, 0x17e8d4, ltc->tag_base); nvkm_wr32(device, 0x17e8d4, ltc->tag_base);
nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
return 0;
} }
struct nvkm_oclass * static const struct nvkm_ltc_func
gk104_ltc_oclass = &(struct nvkm_ltc_impl) { gk104_ltc = {
.base.handle = NV_SUBDEV(LTC, 0xe4), .oneinit = gf100_ltc_oneinit,
.base.ofuncs = &(struct nvkm_ofuncs) { .init = gk104_ltc_init,
.ctor = gf100_ltc_ctor,
.dtor = gf100_ltc_dtor,
.init = gk104_ltc_init,
.fini = _nvkm_ltc_fini,
},
.intr = gf100_ltc_intr, .intr = gf100_ltc_intr,
.cbc_clear = gf100_ltc_cbc_clear, .cbc_clear = gf100_ltc_cbc_clear,
.cbc_wait = gf100_ltc_cbc_wait, .cbc_wait = gf100_ltc_cbc_wait,
.zbc = 16, .zbc = 16,
.zbc_clear_color = gf100_ltc_zbc_clear_color, .zbc_clear_color = gf100_ltc_zbc_clear_color,
.zbc_clear_depth = gf100_ltc_zbc_clear_depth, .zbc_clear_depth = gf100_ltc_zbc_clear_depth,
}.base; };
int
gk104_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc)
{
return nvkm_ltc_new_(&gk104_ltc, device, index, pltc);
}

103
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
View File

@ -27,18 +27,18 @@
#include <subdev/timer.h> #include <subdev/timer.h>
static void static void
gm107_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit) gm107_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit)
{ {
struct nvkm_device *device = ltc->base.subdev.device; struct nvkm_device *device = ltc->subdev.device;
nvkm_wr32(device, 0x17e270, start); nvkm_wr32(device, 0x17e270, start);
nvkm_wr32(device, 0x17e274, limit); nvkm_wr32(device, 0x17e274, limit);
nvkm_wr32(device, 0x17e26c, 0x00000004); nvkm_wr32(device, 0x17e26c, 0x00000004);
} }
static void static void
gm107_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) gm107_ltc_cbc_wait(struct nvkm_ltc *ltc)
{ {
struct nvkm_device *device = ltc->base.subdev.device; struct nvkm_device *device = ltc->subdev.device;
int c, s; int c, s;
for (c = 0; c < ltc->ltc_nr; c++) { for (c = 0; c < ltc->ltc_nr; c++) {
for (s = 0; s < ltc->lts_nr; s++) { for (s = 0; s < ltc->lts_nr; s++) {
@ -52,9 +52,9 @@ gm107_ltc_cbc_wait(struct nvkm_ltc_priv *ltc)
} }
static void static void
gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4]) gm107_ltc_zbc_clear_color(struct nvkm_ltc *ltc, int i, const u32 color[4])
{ {
struct nvkm_device *device = ltc->base.subdev.device; struct nvkm_device *device = ltc->subdev.device;
nvkm_mask(device, 0x17e338, 0x0000000f, i); nvkm_mask(device, 0x17e338, 0x0000000f, i);
nvkm_wr32(device, 0x17e33c, color[0]); nvkm_wr32(device, 0x17e33c, color[0]);
nvkm_wr32(device, 0x17e340, color[1]); nvkm_wr32(device, 0x17e340, color[1]);
@ -63,17 +63,17 @@ gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4])
} }
static void static void
gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth) gm107_ltc_zbc_clear_depth(struct nvkm_ltc *ltc, int i, const u32 depth)
{ {
struct nvkm_device *device = ltc->base.subdev.device; struct nvkm_device *device = ltc->subdev.device;
nvkm_mask(device, 0x17e338, 0x0000000f, i); nvkm_mask(device, 0x17e338, 0x0000000f, i);
nvkm_wr32(device, 0x17e34c, depth); nvkm_wr32(device, 0x17e34c, depth);
} }
static void static void
gm107_ltc_lts_isr(struct nvkm_ltc_priv *ltc, int c, int s) gm107_ltc_lts_isr(struct nvkm_ltc *ltc, int c, int s)
{ {
struct nvkm_subdev *subdev = &ltc->base.subdev; struct nvkm_subdev *subdev = &ltc->subdev;
struct nvkm_device *device = subdev->device; struct nvkm_device *device = subdev->device;
u32 base = 0x140000 + (c * 0x2000) + (s * 0x400); u32 base = 0x140000 + (c * 0x2000) + (s * 0x400);
u32 stat = nvkm_rd32(device, base + 0x00c); u32 stat = nvkm_rd32(device, base + 0x00c);
@ -85,10 +85,9 @@ gm107_ltc_lts_isr(struct nvkm_ltc_priv *ltc, int c, int s)
} }
static void static void
gm107_ltc_intr(struct nvkm_subdev *subdev) gm107_ltc_intr(struct nvkm_ltc *ltc)
{ {
struct nvkm_ltc_priv *ltc = (void *)subdev; struct nvkm_device *device = ltc->subdev.device;
struct nvkm_device *device = ltc->base.subdev.device;
u32 mask; u32 mask;
mask = nvkm_rd32(device, 0x00017c); mask = nvkm_rd32(device, 0x00017c);
@ -101,66 +100,48 @@ gm107_ltc_intr(struct nvkm_subdev *subdev)
} }
static int static int
gm107_ltc_init(struct nvkm_object *object) gm107_ltc_oneinit(struct nvkm_ltc *ltc)
{ {
struct nvkm_ltc_priv *ltc = (void *)object; struct nvkm_device *device = ltc->subdev.device;
struct nvkm_device *device = ltc->base.subdev.device; const u32 parts = nvkm_rd32(device, 0x022438);
u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); const u32 mask = nvkm_rd32(device, 0x021c14);
int ret; const u32 slice = nvkm_rd32(device, 0x17e280) >> 28;
int i;
ret = nvkm_ltc_init(ltc);
if (ret)
return ret;
nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
nvkm_wr32(device, 0x17e278, ltc->tag_base);
nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
return 0;
}
static int
gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_device *device = (void *)parent;
struct nvkm_ltc_priv *ltc;
u32 parts, mask;
int ret, i;
ret = nvkm_ltc_create(parent, engine, oclass, &ltc);
*pobject = nv_object(ltc);
if (ret)
return ret;
parts = nvkm_rd32(device, 0x022438);
mask = nvkm_rd32(device, 0x021c14);
for (i = 0; i < parts; i++) { for (i = 0; i < parts; i++) {
if (!(mask & (1 << i))) if (!(mask & (1 << i)))
ltc->ltc_nr++; ltc->ltc_nr++;
} }
ltc->lts_nr = nvkm_rd32(device, 0x17e280) >> 28; ltc->lts_nr = slice;
ret = gf100_ltc_init_tag_ram(ltc); return gf100_ltc_oneinit_tag_ram(ltc);
if (ret)
return ret;
return 0;
} }
struct nvkm_oclass * static void
gm107_ltc_oclass = &(struct nvkm_ltc_impl) { gm107_ltc_init(struct nvkm_ltc *ltc)
.base.handle = NV_SUBDEV(LTC, 0xff), {
.base.ofuncs = &(struct nvkm_ofuncs) { struct nvkm_device *device = ltc->subdev.device;
.ctor = gm107_ltc_ctor, u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
.dtor = gf100_ltc_dtor,
.init = gm107_ltc_init, nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
.fini = _nvkm_ltc_fini, nvkm_wr32(device, 0x17e278, ltc->tag_base);
}, nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
}
static const struct nvkm_ltc_func
gm107_ltc = {
.oneinit = gm107_ltc_oneinit,
.init = gm107_ltc_init,
.intr = gm107_ltc_intr, .intr = gm107_ltc_intr,
.cbc_clear = gm107_ltc_cbc_clear, .cbc_clear = gm107_ltc_cbc_clear,
.cbc_wait = gm107_ltc_cbc_wait, .cbc_wait = gm107_ltc_cbc_wait,
.zbc = 16, .zbc = 16,
.zbc_clear_color = gm107_ltc_zbc_clear_color, .zbc_clear_color = gm107_ltc_zbc_clear_color,
.zbc_clear_depth = gm107_ltc_zbc_clear_depth, .zbc_clear_depth = gm107_ltc_zbc_clear_depth,
}.base; };
int
gm107_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc)
{
return nvkm_ltc_new_(&gm107_ltc, device, index, pltc);
}

76
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h
View File

@ -1,69 +1,29 @@
#ifndef __NVKM_LTC_PRIV_H__ #ifndef __NVKM_LTC_PRIV_H__
#define __NVKM_LTC_PRIV_H__ #define __NVKM_LTC_PRIV_H__
#define nvkm_ltc(p) container_of((p), struct nvkm_ltc, subdev)
#include <subdev/ltc.h> #include <subdev/ltc.h>
#include <core/mm.h> int nvkm_ltc_new_(const struct nvkm_ltc_func *, struct nvkm_device *,
struct nvkm_fb; int index, struct nvkm_ltc **);
struct nvkm_ltc_priv { struct nvkm_ltc_func {
struct nvkm_ltc base; int (*oneinit)(struct nvkm_ltc *);
u32 ltc_nr; void (*init)(struct nvkm_ltc *);
u32 lts_nr; void (*intr)(struct nvkm_ltc *);
u32 num_tags; void (*cbc_clear)(struct nvkm_ltc *, u32 start, u32 limit);
u32 tag_base; void (*cbc_wait)(struct nvkm_ltc *);
struct nvkm_mm tags;
struct nvkm_mm_node *tag_ram;
u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4];
u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
};
#define nvkm_ltc_create(p,e,o,d) \
nvkm_ltc_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_ltc_destroy(p) ({ \
struct nvkm_ltc_priv *_priv = (p); \
_nvkm_ltc_dtor(nv_object(_priv)); \
})
#define nvkm_ltc_init(p) ({ \
struct nvkm_ltc_priv *_priv = (p); \
_nvkm_ltc_init(nv_object(_priv)); \
})
#define nvkm_ltc_fini(p,s) ({ \
struct nvkm_ltc_priv *_priv = (p); \
_nvkm_ltc_fini(nv_object(_priv), (s)); \
})
int nvkm_ltc_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
#define _nvkm_ltc_dtor _nvkm_subdev_dtor
int _nvkm_ltc_init(struct nvkm_object *);
#define _nvkm_ltc_fini _nvkm_subdev_fini
int gf100_ltc_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void gf100_ltc_dtor(struct nvkm_object *);
int gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *);
int gf100_ltc_tags_alloc(struct nvkm_ltc *, u32, struct nvkm_mm_node **);
void gf100_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **);
struct nvkm_ltc_impl {
struct nvkm_oclass base;
void (*intr)(struct nvkm_subdev *);
void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit);
void (*cbc_wait)(struct nvkm_ltc_priv *);
int zbc; int zbc;
void (*zbc_clear_color)(struct nvkm_ltc_priv *, int, const u32[4]); void (*zbc_clear_color)(struct nvkm_ltc *, int, const u32[4]);
void (*zbc_clear_depth)(struct nvkm_ltc_priv *, int, const u32); void (*zbc_clear_depth)(struct nvkm_ltc *, int, const u32);
}; };
void gf100_ltc_intr(struct nvkm_subdev *); int gf100_ltc_oneinit(struct nvkm_ltc *);
void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32); int gf100_ltc_oneinit_tag_ram(struct nvkm_ltc *);
void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *); void gf100_ltc_intr(struct nvkm_ltc *);
void gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *, int, const u32[4]); void gf100_ltc_cbc_clear(struct nvkm_ltc *, u32, u32);
void gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *, int, const u32); void gf100_ltc_cbc_wait(struct nvkm_ltc *);
void gf100_ltc_zbc_clear_color(struct nvkm_ltc *, int, const u32[4]);
void gf100_ltc_zbc_clear_depth(struct nvkm_ltc *, int, const u32);
#endif #endif

4
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
View File

@ -108,11 +108,11 @@ gf100_vm_map(struct nvkm_vma *vma, struct nvkm_memory *pgt,
pte <<= 3; pte <<= 3;
if (mem->tag) { if (mem->tag) {
struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu); struct nvkm_ltc *ltc = vma->vm->mmu->subdev.device->ltc;
u32 tag = mem->tag->offset + (delta >> 17); u32 tag = mem->tag->offset + (delta >> 17);
phys |= (u64)tag << (32 + 12); phys |= (u64)tag << (32 + 12);
next |= (u64)1 << (32 + 12); next |= (u64)1 << (32 + 12);
ltc->tags_clear(ltc, tag, cnt); nvkm_ltc_tags_clear(ltc, tag, cnt);
} }
nvkm_kmap(pgt); nvkm_kmap(pgt);