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drm/i915: Store cdclk PLL reference clock under dev_priv 

Future platforms will have multiple options for the cdclk PLL reference
clock, so let's start tracking that under dev_priv alreday on SKL,
although on SKL it's always 24 MHz.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-15-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
This commit is contained in:
Ville Syrjälä 2016-05-13 23:41:33 +03:00
parent 63911d7295
commit 709e05c3c4
2 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1823,7 +1823,7 @@ struct drm_i915_private {
unsigned int czclk_freq;
struct {
unsigned int vco;
unsigned int vco, ref;
} cdclk_pll;
/**

14
drivers/gpu/drm/i915/intel_display.c
View File

@ -5255,8 +5255,9 @@ static void intel_update_cdclk(struct drm_device *dev)
dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz\n",
dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco);
DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
dev_priv->cdclk_pll.ref);
else
DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
dev_priv->cdclk_freq);
@ -5462,6 +5463,8 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
{
u32 val;
dev_priv->cdclk_pll.ref = 24000;
val = I915_READ(LCPLL1_CTL);
if ((val & LCPLL_PLL_ENABLE) == 0) {
dev_priv->cdclk_pll.vco = 0;
@ -5650,7 +5653,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
{
skl_set_cdclk(dev_priv, 24000, 0);
skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
}
void skl_init_cdclk(struct drm_i915_private *dev_priv)
@ -6572,7 +6575,7 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
skl_dpll0_update(dev_priv);
if (dev_priv->cdclk_pll.vco == 0)
return 24000; /* 24MHz is the cd freq with NSSC ref */
return dev_priv->cdclk_pll.ref;
cdctl = I915_READ(CDCLK_CTL);
@ -6604,8 +6607,7 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
}
}
/* error case, do as if DPLL0 isn't enabled */
return 24000;
return dev_priv->cdclk_pll.ref;
}
static int broxton_get_display_clock_speed(struct drm_device *dev)