ASoC: nau8825: support different clock source for FLL function
Extend FLL clock source selection. The source can be from MCLK, BCLK or FS. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -1069,6 +1069,37 @@ static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
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return 0;
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}
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static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
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{
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int ret = 0;
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nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
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if (IS_ERR(nau8825->mclk)) {
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dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
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return 0;
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}
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if (!nau8825->mclk_freq) {
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ret = clk_prepare_enable(nau8825->mclk);
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if (ret) {
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dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
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return ret;
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}
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}
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if (nau8825->mclk_freq != freq) {
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freq = clk_round_rate(nau8825->mclk, freq);
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ret = clk_set_rate(nau8825->mclk, freq);
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if (ret) {
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dev_err(nau8825->dev, "Unable to set mclk rate\n");
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return ret;
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}
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nau8825->mclk_freq = freq;
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}
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return 0;
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}
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static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
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unsigned int freq)
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{
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@ -1080,29 +1111,9 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
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regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
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NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
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regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
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/* We selected MCLK source but the clock itself managed externally */
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if (!nau8825->mclk)
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break;
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if (!nau8825->mclk_freq) {
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ret = clk_prepare_enable(nau8825->mclk);
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if (ret) {
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dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
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return ret;
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}
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}
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if (nau8825->mclk_freq != freq) {
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nau8825->mclk_freq = freq;
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freq = clk_round_rate(nau8825->mclk, freq);
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ret = clk_set_rate(nau8825->mclk, freq);
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if (ret) {
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dev_err(nau8825->dev, "Unable to set mclk rate\n");
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return ret;
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}
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}
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ret = nau8825_mclk_prepare(nau8825, freq);
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if (ret)
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return ret;
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break;
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case NAU8825_CLK_INTERNAL:
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@ -1110,7 +1121,32 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
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NAU8825_DCO_EN);
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regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
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NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
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if (nau8825->mclk_freq) {
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clk_disable_unprepare(nau8825->mclk);
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nau8825->mclk_freq = 0;
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}
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break;
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case NAU8825_CLK_FLL_MCLK:
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regmap_update_bits(regmap, NAU8825_REG_FLL3,
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NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK);
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ret = nau8825_mclk_prepare(nau8825, freq);
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if (ret)
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return ret;
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break;
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case NAU8825_CLK_FLL_BLK:
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regmap_update_bits(regmap, NAU8825_REG_FLL3,
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NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK);
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if (nau8825->mclk_freq) {
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clk_disable_unprepare(nau8825->mclk);
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nau8825->mclk_freq = 0;
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}
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break;
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case NAU8825_CLK_FLL_FS:
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regmap_update_bits(regmap, NAU8825_REG_FLL3,
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NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS);
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if (nau8825->mclk_freq) {
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clk_disable_unprepare(nau8825->mclk);
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nau8825->mclk_freq = 0;
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@ -113,6 +113,11 @@
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/* FLL3 (0x06) */
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#define NAU8825_FLL_INTEGER_MASK (0x3ff << 0)
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#define NAU8825_FLL_CLK_SRC_SFT 10
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#define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT)
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#define NAU8825_FLL_CLK_SRC_MCLK (0 << NAU8825_FLL_CLK_SRC_SFT)
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#define NAU8825_FLL_CLK_SRC_BLK (0x2 << NAU8825_FLL_CLK_SRC_SFT)
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#define NAU8825_FLL_CLK_SRC_FS (0x3 << NAU8825_FLL_CLK_SRC_SFT)
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/* FLL4 (0x07) */
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#define NAU8825_FLL_REF_DIV_MASK (0x3 << 10)
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@ -320,6 +325,9 @@
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enum {
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NAU8825_CLK_MCLK = 0,
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NAU8825_CLK_INTERNAL,
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NAU8825_CLK_FLL_MCLK,
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NAU8825_CLK_FLL_BLK,
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NAU8825_CLK_FLL_FS,
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};
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struct nau8825 {
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